1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 9 #ifndef _RTE_DEVICE_H 10 #define _RTE_DEVICE_H 11 12 #include "pin_mux.h" 13 14 /* UART Select, UART0-UART9. */ 15 /* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART 16 * instance. */ 17 #define RTE_USART0 0 18 #define RTE_USART0_DMA_EN 0 19 #define RTE_USART1 0 20 #define RTE_USART1_DMA_EN 0 21 #define RTE_USART2 0 22 #define RTE_USART2_DMA_EN 0 23 #define RTE_USART3 0 24 #define RTE_USART3_DMA_EN 0 25 #define RTE_USART4 0 26 #define RTE_USART4_DMA_EN 0 27 #define RTE_USART5 0 28 #define RTE_USART5_DMA_EN 0 29 #define RTE_USART6 0 30 #define RTE_USART6_DMA_EN 0 31 #define RTE_USART7 0 32 #define RTE_USART7_DMA_EN 0 33 #define RTE_USART8 0 34 #define RTE_USART8_DMA_EN 0 35 #define RTE_USART9 0 36 #define RTE_USART9_DMA_EN 0 37 38 /* USART configuration. */ 39 #define USART_RX_BUFFER_LEN 64 40 #define USART0_RX_BUFFER_ENABLE 0 41 #define USART1_RX_BUFFER_ENABLE 0 42 #define USART2_RX_BUFFER_ENABLE 0 43 #define USART3_RX_BUFFER_ENABLE 0 44 #define USART4_RX_BUFFER_ENABLE 0 45 #define USART5_RX_BUFFER_ENABLE 0 46 #define USART6_RX_BUFFER_ENABLE 0 47 #define USART7_RX_BUFFER_ENABLE 0 48 #define USART8_RX_BUFFER_ENABLE 0 49 #define USART9_RX_BUFFER_ENABLE 0 50 51 #define RTE_USART0_PIN_INIT USART0_InitPins 52 #define RTE_USART0_PIN_DEINIT USART0_DeinitPins 53 #define RTE_USART0_DMA_TX_CH 1 54 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 55 #define RTE_USART0_DMA_RX_CH 0 56 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 57 58 #define RTE_USART1_PIN_INIT USART1_InitPins 59 #define RTE_USART1_PIN_DEINIT USART1_DeinitPins 60 #define RTE_USART1_DMA_TX_CH 3 61 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 62 #define RTE_USART1_DMA_RX_CH 2 63 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 64 65 #define RTE_USART2_PIN_INIT USART2_InitPins 66 #define RTE_USART2_PIN_DEINIT USART2_DeinitPins 67 #define RTE_USART2_DMA_TX_CH 5 68 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 69 #define RTE_USART2_DMA_RX_CH 4 70 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 71 72 #define RTE_USART3_PIN_INIT USART3_InitPins 73 #define RTE_USART3_PIN_DEINIT USART3_DeinitPins 74 #define RTE_USART3_DMA_TX_CH 7 75 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 76 #define RTE_USART3_DMA_RX_CH 6 77 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 78 79 #define RTE_USART4_PIN_INIT USART4_InitPins 80 #define RTE_USART4_PIN_DEINIT USART4_DeinitPins 81 #define RTE_USART4_DMA_TX_CH 9 82 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 83 #define RTE_USART4_DMA_RX_CH 8 84 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 85 86 #define RTE_USART5_PIN_INIT USART5_InitPins 87 #define RTE_USART5_PIN_DEINIT USART5_DeinitPins 88 #define RTE_USART5_DMA_TX_CH 11 89 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 90 #define RTE_USART5_DMA_RX_CH 10 91 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 92 93 #define RTE_USART6_PIN_INIT USART6_InitPins 94 #define RTE_USART6_PIN_DEINIT USART6_DeinitPins 95 #define RTE_USART6_DMA_TX_CH 13 96 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 97 #define RTE_USART6_DMA_RX_CH 12 98 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 99 100 #define RTE_USART7_PIN_INIT USART7_InitPins 101 #define RTE_USART7_PIN_DEINIT USART7_DeinitPins 102 #define RTE_USART7_DMA_TX_CH 15 103 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 104 #define RTE_USART7_DMA_RX_CH 14 105 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 106 107 #define RTE_USART8_PIN_INIT USART8_InitPins 108 #define RTE_USART8_PIN_DEINIT USART8_DeinitPins 109 #define RTE_USART8_DMA_TX_CH 17 110 #define RTE_USART8_DMA_TX_DMA_BASE DMA0 111 #define RTE_USART8_DMA_RX_CH 16 112 #define RTE_USART8_DMA_RX_DMA_BASE DMA0 113 114 #define RTE_USART9_PIN_INIT USART9_InitPins 115 #define RTE_USART9_PIN_DEINIT USART9_DeinitPins 116 #define RTE_USART9_DMA_TX_CH 19 117 #define RTE_USART9_DMA_TX_DMA_BASE DMA0 118 #define RTE_USART9_DMA_RX_CH 18 119 #define RTE_USART9_DMA_RX_DMA_BASE DMA0 120 121 /* I2C Select, I2C0 -I2C9*/ 122 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 123 */ 124 #define RTE_I2C0 0 125 #define RTE_I2C0_DMA_EN 0 126 #define RTE_I2C1 0 127 #define RTE_I2C1_DMA_EN 0 128 #define RTE_I2C2 0 129 #define RTE_I2C2_DMA_EN 0 130 #define RTE_I2C3 0 131 #define RTE_I2C3_DMA_EN 0 132 #define RTE_I2C4 0 133 #define RTE_I2C4_DMA_EN 0 134 #define RTE_I2C5 0 135 #define RTE_I2C5_DMA_EN 0 136 #define RTE_I2C6 0 137 #define RTE_I2C6_DMA_EN 0 138 #define RTE_I2C7 0 139 #define RTE_I2C7_DMA_EN 0 140 #define RTE_I2C8 0 141 #define RTE_I2C8_DMA_EN 0 142 #define RTE_I2C9 0 143 #define RTE_I2C9_DMA_EN 0 144 145 /*I2C configuration*/ 146 #define RTE_I2C0_Master_DMA_BASE DMA0 147 #define RTE_I2C0_Master_DMA_CH 1 148 149 #define RTE_I2C1_Master_DMA_BASE DMA0 150 #define RTE_I2C1_Master_DMA_CH 3 151 152 #define RTE_I2C2_Master_DMA_BASE DMA0 153 #define RTE_I2C2_Master_DMA_CH 5 154 155 #define RTE_I2C3_Master_DMA_BASE DMA0 156 #define RTE_I2C3_Master_DMA_CH 7 157 158 #define RTE_I2C4_Master_DMA_BASE DMA0 159 #define RTE_I2C4_Master_DMA_CH 9 160 161 #define RTE_I2C5_Master_DMA_BASE DMA0 162 #define RTE_I2C5_Master_DMA_CH 11 163 164 #define RTE_I2C6_Master_DMA_BASE DMA0 165 #define RTE_I2C6_Master_DMA_CH 13 166 167 #define RTE_I2C7_Master_DMA_BASE DMA0 168 #define RTE_I2C7_Master_DMA_CH 15 169 170 #define RTE_I2C8_Master_DMA_BASE DMA0 171 #define RTE_I2C8_Master_DMA_CH 17 172 173 #define RTE_I2C9_Master_DMA_BASE DMA0 174 #define RTE_I2C9_Master_DMA_CH 19 175 176 /* SPI select, SPI0 - SPI9.*/ 177 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 178 */ 179 #define RTE_SPI0 0 180 #define RTE_SPI0_DMA_EN 0 181 #define RTE_SPI1 0 182 #define RTE_SPI1_DMA_EN 0 183 #define RTE_SPI2 0 184 #define RTE_SPI2_DMA_EN 0 185 #define RTE_SPI3 0 186 #define RTE_SPI3_DMA_EN 0 187 #define RTE_SPI4 0 188 #define RTE_SPI4_DMA_EN 0 189 #define RTE_SPI5 0 190 #define RTE_SPI5_DMA_EN 0 191 #define RTE_SPI6 0 192 #define RTE_SPI6_DMA_EN 0 193 #define RTE_SPI7 0 194 #define RTE_SPI7_DMA_EN 0 195 #define RTE_SPI8 0 196 #define RTE_SPI8_DMA_EN 0 197 #define RTE_SPI9 0 198 #define RTE_SPI9_DMA_EN 0 199 200 /* SPI configuration. */ 201 #define RTE_SPI0_SSEL_NUM kSPI_Ssel0 202 #define RTE_SPI0_PIN_INIT SPI0_InitPins 203 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 204 #define RTE_SPI0_DMA_TX_CH 1 205 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 206 #define RTE_SPI0_DMA_RX_CH 0 207 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 208 209 #define RTE_SPI1_SSEL_NUM kSPI_Ssel0 210 #define RTE_SPI1_PIN_INIT SPI1_InitPins 211 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 212 #define RTE_SPI1_DMA_TX_CH 3 213 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 214 #define RTE_SPI1_DMA_RX_CH 2 215 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 216 217 #define RTE_SPI2_SSEL_NUM kSPI_Ssel0 218 #define RTE_SPI2_PIN_INIT SPI2_InitPins 219 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 220 #define RTE_SPI2_DMA_TX_CH 5 221 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 222 #define RTE_SPI2_DMA_RX_CH 4 223 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 224 225 #define RTE_SPI3_SSEL_NUM kSPI_Ssel0 226 #define RTE_SPI3_PIN_INIT SPI3_InitPins 227 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 228 #define RTE_SPI3_DMA_TX_CH 7 229 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 230 #define RTE_SPI3_DMA_RX_CH 6 231 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 232 233 #define RTE_SPI4_SSEL_NUM kSPI_Ssel0 234 #define RTE_SPI4_PIN_INIT SPI4_InitPins 235 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 236 #define RTE_SPI4_DMA_TX_CH 9 237 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 238 #define RTE_SPI4_DMA_RX_CH 8 239 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 240 241 #define RTE_SPI5_SSEL_NUM kSPI_Ssel0 242 #define RTE_SPI5_PIN_INIT SPI5_InitPins 243 #define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins 244 #define RTE_SPI5_DMA_TX_CH 11 245 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 246 #define RTE_SPI5_DMA_RX_CH 10 247 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 248 249 #define RTE_SPI6_SSEL_NUM kSPI_Ssel0 250 #define RTE_SPI6_PIN_INIT SPI6_InitPins 251 #define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins 252 #define RTE_SPI6_DMA_TX_CH 13 253 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 254 #define RTE_SPI6_DMA_RX_CH 12 255 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 256 257 #define RTE_SPI7_SSEL_NUM kSPI_Ssel0 258 #define RTE_SPI7_PIN_INIT SPI7_InitPins 259 #define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins 260 #define RTE_SPI7_DMA_TX_CH 15 261 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 262 #define RTE_SPI7_DMA_RX_CH 14 263 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 264 265 #define RTE_SPI8_SSEL_NUM kSPI_Ssel0 266 #define RTE_SPI8_PIN_INIT SPI8_InitPins 267 #define RTE_SPI8_PIN_DEINIT SPI8_DeinitPins 268 #define RTE_SPI8_DMA_TX_CH 17 269 #define RTE_SPI8_DMA_TX_DMA_BASE DMA0 270 #define RTE_SPI8_DMA_RX_CH 16 271 #define RTE_SPI8_DMA_RX_DMA_BASE DMA0 272 273 #define RTE_SPI9_SSEL_NUM kSPI_Ssel0 274 #define RTE_SPI9_PIN_INIT SPI9_InitPins 275 #define RTE_SPI9_PIN_DEINIT SPI9_DeinitPins 276 #define RTE_SPI9_DMA_TX_CH 23 277 #define RTE_SPI9_DMA_TX_DMA_BASE DMA0 278 #define RTE_SPI9_DMA_RX_CH 22 279 #define RTE_SPI9_DMA_RX_DMA_BASE DMA0 280 281 #endif /* _RTE_DEVICE_H */ 282
