1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select, UART0-UART9. */ 16 /* User needs to provide the implementation of USARTX_GetFreq/USARTX_InitPins/USARTX_DeinitPins for the enabled USART 17 * instance. */ 18 #define RTE_USART0 0 19 #define RTE_USART0_DMA_EN 0 20 #define RTE_USART1 0 21 #define RTE_USART1_DMA_EN 0 22 #define RTE_USART2 0 23 #define RTE_USART2_DMA_EN 0 24 #define RTE_USART3 0 25 #define RTE_USART3_DMA_EN 0 26 #define RTE_USART4 0 27 #define RTE_USART4_DMA_EN 0 28 #define RTE_USART5 0 29 #define RTE_USART5_DMA_EN 0 30 #define RTE_USART6 0 31 #define RTE_USART6_DMA_EN 0 32 #define RTE_USART7 0 33 #define RTE_USART7_DMA_EN 0 34 #define RTE_USART8 0 35 #define RTE_USART8_DMA_EN 0 36 #define RTE_USART9 0 37 #define RTE_USART9_DMA_EN 0 38 39 /* USART configuration. */ 40 #define USART_RX_BUFFER_LEN 64 41 #define USART0_RX_BUFFER_ENABLE 0 42 #define USART1_RX_BUFFER_ENABLE 0 43 #define USART2_RX_BUFFER_ENABLE 0 44 #define USART3_RX_BUFFER_ENABLE 0 45 #define USART4_RX_BUFFER_ENABLE 0 46 #define USART5_RX_BUFFER_ENABLE 0 47 #define USART6_RX_BUFFER_ENABLE 0 48 #define USART7_RX_BUFFER_ENABLE 0 49 #define USART8_RX_BUFFER_ENABLE 0 50 #define USART9_RX_BUFFER_ENABLE 0 51 52 #define RTE_USART0_PIN_INIT USART0_InitPins 53 #define RTE_USART0_PIN_DEINIT USART0_DeinitPins 54 #define RTE_USART0_DMA_TX_CH 1 55 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 56 #define RTE_USART0_DMA_RX_CH 0 57 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 58 59 #define RTE_USART1_PIN_INIT USART1_InitPins 60 #define RTE_USART1_PIN_DEINIT USART1_DeinitPins 61 #define RTE_USART1_DMA_TX_CH 3 62 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 63 #define RTE_USART1_DMA_RX_CH 2 64 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 65 66 #define RTE_USART2_PIN_INIT USART2_InitPins 67 #define RTE_USART2_PIN_DEINIT USART2_DeinitPins 68 #define RTE_USART2_DMA_TX_CH 5 69 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 70 #define RTE_USART2_DMA_RX_CH 4 71 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 72 73 #define RTE_USART3_PIN_INIT USART3_InitPins 74 #define RTE_USART3_PIN_DEINIT USART3_DeinitPins 75 #define RTE_USART3_DMA_TX_CH 7 76 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 77 #define RTE_USART3_DMA_RX_CH 6 78 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 79 80 #define RTE_USART4_PIN_INIT USART4_InitPins 81 #define RTE_USART4_PIN_DEINIT USART4_DeinitPins 82 #define RTE_USART4_DMA_TX_CH 9 83 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 84 #define RTE_USART4_DMA_RX_CH 8 85 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 86 87 #define RTE_USART5_PIN_INIT USART5_InitPins 88 #define RTE_USART5_PIN_DEINIT USART5_DeinitPins 89 #define RTE_USART5_DMA_TX_CH 11 90 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 91 #define RTE_USART5_DMA_RX_CH 10 92 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 93 94 #define RTE_USART6_PIN_INIT USART6_InitPins 95 #define RTE_USART6_PIN_DEINIT USART6_DeinitPins 96 #define RTE_USART6_DMA_TX_CH 13 97 #define RTE_USART6_DMA_TX_DMA_BASE DMA0 98 #define RTE_USART6_DMA_RX_CH 12 99 #define RTE_USART6_DMA_RX_DMA_BASE DMA0 100 101 #define RTE_USART7_PIN_INIT USART7_InitPins 102 #define RTE_USART7_PIN_DEINIT USART7_DeinitPins 103 #define RTE_USART7_DMA_TX_CH 15 104 #define RTE_USART7_DMA_TX_DMA_BASE DMA0 105 #define RTE_USART7_DMA_RX_CH 14 106 #define RTE_USART7_DMA_RX_DMA_BASE DMA0 107 108 #define RTE_USART8_PIN_INIT USART8_InitPins 109 #define RTE_USART8_PIN_DEINIT USART8_DeinitPins 110 #define RTE_USART8_DMA_TX_CH 17 111 #define RTE_USART8_DMA_TX_DMA_BASE DMA0 112 #define RTE_USART8_DMA_RX_CH 16 113 #define RTE_USART8_DMA_RX_DMA_BASE DMA0 114 115 #define RTE_USART9_PIN_INIT USART9_InitPins 116 #define RTE_USART9_PIN_DEINIT USART9_DeinitPins 117 #define RTE_USART9_DMA_TX_CH 19 118 #define RTE_USART9_DMA_TX_DMA_BASE DMA0 119 #define RTE_USART9_DMA_RX_CH 18 120 #define RTE_USART9_DMA_RX_DMA_BASE DMA0 121 122 /* I2C Select, I2C0 -I2C9*/ 123 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 124 */ 125 #define RTE_I2C0 0 126 #define RTE_I2C0_DMA_EN 0 127 #define RTE_I2C1 0 128 #define RTE_I2C1_DMA_EN 0 129 #define RTE_I2C2 0 130 #define RTE_I2C2_DMA_EN 0 131 #define RTE_I2C3 0 132 #define RTE_I2C3_DMA_EN 0 133 #define RTE_I2C4 0 134 #define RTE_I2C4_DMA_EN 0 135 #define RTE_I2C5 0 136 #define RTE_I2C5_DMA_EN 0 137 #define RTE_I2C6 0 138 #define RTE_I2C6_DMA_EN 0 139 #define RTE_I2C7 0 140 #define RTE_I2C7_DMA_EN 0 141 #define RTE_I2C8 0 142 #define RTE_I2C8_DMA_EN 0 143 #define RTE_I2C9 0 144 #define RTE_I2C9_DMA_EN 0 145 146 /*I2C configuration*/ 147 #define RTE_I2C0_Master_DMA_BASE DMA0 148 #define RTE_I2C0_Master_DMA_CH 1 149 150 #define RTE_I2C1_Master_DMA_BASE DMA0 151 #define RTE_I2C1_Master_DMA_CH 3 152 153 #define RTE_I2C2_Master_DMA_BASE DMA0 154 #define RTE_I2C2_Master_DMA_CH 5 155 156 #define RTE_I2C3_Master_DMA_BASE DMA0 157 #define RTE_I2C3_Master_DMA_CH 7 158 159 #define RTE_I2C4_Master_DMA_BASE DMA0 160 #define RTE_I2C4_Master_DMA_CH 9 161 162 #define RTE_I2C5_Master_DMA_BASE DMA0 163 #define RTE_I2C5_Master_DMA_CH 11 164 165 #define RTE_I2C6_Master_DMA_BASE DMA0 166 #define RTE_I2C6_Master_DMA_CH 13 167 168 #define RTE_I2C7_Master_DMA_BASE DMA0 169 #define RTE_I2C7_Master_DMA_CH 15 170 171 #define RTE_I2C8_Master_DMA_BASE DMA0 172 #define RTE_I2C8_Master_DMA_CH 17 173 174 #define RTE_I2C9_Master_DMA_BASE DMA0 175 #define RTE_I2C9_Master_DMA_CH 19 176 177 /* SPI select, SPI0 - SPI9.*/ 178 /* User needs to provide the implementation of SPIX_GetFreq/SPIX_InitPins/SPIX_DeinitPins for the enabled SPI instance. 179 */ 180 #define RTE_SPI0 0 181 #define RTE_SPI0_DMA_EN 0 182 #define RTE_SPI1 0 183 #define RTE_SPI1_DMA_EN 0 184 #define RTE_SPI2 0 185 #define RTE_SPI2_DMA_EN 0 186 #define RTE_SPI3 0 187 #define RTE_SPI3_DMA_EN 0 188 #define RTE_SPI4 0 189 #define RTE_SPI4_DMA_EN 0 190 #define RTE_SPI5 0 191 #define RTE_SPI5_DMA_EN 0 192 #define RTE_SPI6 0 193 #define RTE_SPI6_DMA_EN 0 194 #define RTE_SPI7 0 195 #define RTE_SPI7_DMA_EN 0 196 #define RTE_SPI8 0 197 #define RTE_SPI8_DMA_EN 0 198 #define RTE_SPI9 0 199 #define RTE_SPI9_DMA_EN 0 200 201 /* SPI configuration. */ 202 #define RTE_SPI0_SSEL_NUM kSPI_Ssel0 203 #define RTE_SPI0_PIN_INIT SPI0_InitPins 204 #define RTE_SPI0_PIN_DEINIT SPI0_DeinitPins 205 #define RTE_SPI0_DMA_TX_CH 1 206 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 207 #define RTE_SPI0_DMA_RX_CH 0 208 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 209 210 #define RTE_SPI1_SSEL_NUM kSPI_Ssel0 211 #define RTE_SPI1_PIN_INIT SPI1_InitPins 212 #define RTE_SPI1_PIN_DEINIT SPI1_DeinitPins 213 #define RTE_SPI1_DMA_TX_CH 3 214 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 215 #define RTE_SPI1_DMA_RX_CH 2 216 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 217 218 #define RTE_SPI2_SSEL_NUM kSPI_Ssel0 219 #define RTE_SPI2_PIN_INIT SPI2_InitPins 220 #define RTE_SPI2_PIN_DEINIT SPI2_DeinitPins 221 #define RTE_SPI2_DMA_TX_CH 5 222 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 223 #define RTE_SPI2_DMA_RX_CH 4 224 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 225 226 #define RTE_SPI3_SSEL_NUM kSPI_Ssel0 227 #define RTE_SPI3_PIN_INIT SPI3_InitPins 228 #define RTE_SPI3_PIN_DEINIT SPI3_DeinitPins 229 #define RTE_SPI3_DMA_TX_CH 7 230 #define RTE_SPI3_DMA_TX_DMA_BASE DMA0 231 #define RTE_SPI3_DMA_RX_CH 6 232 #define RTE_SPI3_DMA_RX_DMA_BASE DMA0 233 234 #define RTE_SPI4_SSEL_NUM kSPI_Ssel0 235 #define RTE_SPI4_PIN_INIT SPI4_InitPins 236 #define RTE_SPI4_PIN_DEINIT SPI4_DeinitPins 237 #define RTE_SPI4_DMA_TX_CH 9 238 #define RTE_SPI4_DMA_TX_DMA_BASE DMA0 239 #define RTE_SPI4_DMA_RX_CH 8 240 #define RTE_SPI4_DMA_RX_DMA_BASE DMA0 241 242 #define RTE_SPI5_SSEL_NUM kSPI_Ssel0 243 #define RTE_SPI5_PIN_INIT SPI5_InitPins 244 #define RTE_SPI5_PIN_DEINIT SPI5_DeinitPins 245 #define RTE_SPI5_DMA_TX_CH 11 246 #define RTE_SPI5_DMA_TX_DMA_BASE DMA0 247 #define RTE_SPI5_DMA_RX_CH 10 248 #define RTE_SPI5_DMA_RX_DMA_BASE DMA0 249 250 #define RTE_SPI6_SSEL_NUM kSPI_Ssel0 251 #define RTE_SPI6_PIN_INIT SPI6_InitPins 252 #define RTE_SPI6_PIN_DEINIT SPI6_DeinitPins 253 #define RTE_SPI6_DMA_TX_CH 13 254 #define RTE_SPI6_DMA_TX_DMA_BASE DMA0 255 #define RTE_SPI6_DMA_RX_CH 12 256 #define RTE_SPI6_DMA_RX_DMA_BASE DMA0 257 258 #define RTE_SPI7_SSEL_NUM kSPI_Ssel0 259 #define RTE_SPI7_PIN_INIT SPI7_InitPins 260 #define RTE_SPI7_PIN_DEINIT SPI7_DeinitPins 261 #define RTE_SPI7_DMA_TX_CH 15 262 #define RTE_SPI7_DMA_TX_DMA_BASE DMA0 263 #define RTE_SPI7_DMA_RX_CH 14 264 #define RTE_SPI7_DMA_RX_DMA_BASE DMA0 265 266 #define RTE_SPI8_SSEL_NUM kSPI_Ssel0 267 #define RTE_SPI8_PIN_INIT SPI8_InitPins 268 #define RTE_SPI8_PIN_DEINIT SPI8_DeinitPins 269 #define RTE_SPI8_DMA_TX_CH 17 270 #define RTE_SPI8_DMA_TX_DMA_BASE DMA0 271 #define RTE_SPI8_DMA_RX_CH 16 272 #define RTE_SPI8_DMA_RX_DMA_BASE DMA0 273 274 #define RTE_SPI9_SSEL_NUM kSPI_Ssel0 275 #define RTE_SPI9_PIN_INIT SPI9_InitPins 276 #define RTE_SPI9_PIN_DEINIT SPI9_DeinitPins 277 #define RTE_SPI9_DMA_TX_CH 23 278 #define RTE_SPI9_DMA_TX_DMA_BASE DMA0 279 #define RTE_SPI9_DMA_RX_CH 22 280 #define RTE_SPI9_DMA_RX_DMA_BASE DMA0 281 282 #endif /* _RTE_DEVICE_H */ 283
