1/* ---------------------------------------------------------------------------------------*/
2/*  @file:    startup_LPC54114_cm0plus.S                                                  */
3/*  @purpose: CMSIS Cortex-M0 Core Device Startup File                                    */
4/*            LPC54114_cm0plus                                                            */
5/*  @version: 1.0                                                                         */
6/*  @date:    2016-11-2                                                                   */
7/*  @build:   b161214                                                                     */
8/* ---------------------------------------------------------------------------------------*/
9/*                                                                                        */
10/* Copyright 1997-2016 Freescale Semiconductor, Inc.                                      */
11/* Copyright 2016-2018 NXP                                                                */
12/*                                                                                        */
13/* SPDX-License-Identifier: BSD-3-Clause                           */
14/*****************************************************************************/
15/* Version: GCC for ARM Embedded Processors                                  */
16/*****************************************************************************/
17    .syntax unified
18    .arch armv7-m
19
20    .section .isr_vector, "a"
21    .align 2
22    .globl __Vectors
23__Vectors:
24    .long   __StackTop                                      /* Top of Stack */
25    .long   Reset_Handler                                   /* Reset Handler */
26    .long   NMI_Handler                                     /* NMI Handler*/
27    .long   HardFault_Handler                               /* Hard Fault Handler*/
28    .long   0                                               /* Reserved*/
29    .long   0                                               /* Reserved*/
30    .long   0                                               /* Reserved*/
31    .long   0                                               /* Reserved*/
32    .long   0                                               /* Reserved*/
33    .long   0                                               /* Reserved*/
34    .long   0                                               /* Reserved*/
35    .long   SVC_Handler                                     /* SVCall Handler*/
36    .long   0                                               /* Reserved*/
37    .long   0                                               /* Reserved*/
38    .long   PendSV_Handler                                  /* PendSV Handler*/
39    .long   SysTick_Handler                                 /* SysTick Handler*/
40
41                                                            /* External Interrupts*/
42    .long   WDT_BOD_IRQHandler                              /* Watchdog Timer, Brownout detect */
43    .long   DMA0_IRQHandler                                 /* DMA controller interrupt */
44    .long   GINT0_IRQHandler                                /* GPIO group 0 */
45    .long   GINT1_IRQHandler                                /* GPIO group 1 */
46    .long   PIN_INT0_IRQHandler                             /* Pin interrupt 0 or pattern match engine slice 0 */
47    .long   PIN_INT1_IRQHandler                             /* Pin interrupt 1 or pattern match engine slice 1 */
48    .long   PIN_INT2_IRQHandler                             /* Pin interrupt 2 or pattern match engine slice 2 */
49    .long   PIN_INT3_IRQHandler                             /* Pin interrupt 3 or pattern match engine slice 3 */
50    .long   UTICK0_IRQHandler                               /* Micro-tick Timer */
51    .long   MRT0_IRQHandler                                 /* Multi-rate timer */
52    .long   CTIMER0_IRQHandler                              /* Standard counter/timer CTIMER0 */
53    .long   CTIMER1_IRQHandler                              /* Standard counter/timer CTIMER1 */
54    .long   SCT0_IRQHandler                                 /* SCTimer/PWM */
55    .long   CTIMER3_IRQHandler                              /* Standard counter/timer CTIMER3 */
56    .long   FLEXCOMM0_IRQHandler                            /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
57    .long   FLEXCOMM1_IRQHandler                            /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
58    .long   FLEXCOMM2_IRQHandler                            /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
59    .long   FLEXCOMM3_IRQHandler                            /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
60    .long   FLEXCOMM4_IRQHandler                            /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
61    .long   FLEXCOMM5_IRQHandler                            /* Flexcomm Interface 5 (USART, SPI, I2C, FLEXCOMM) */
62    .long   FLEXCOMM6_IRQHandler                            /* Flexcomm Interface 6 (USART, SPI, I2C, FLEXCOMM) */
63    .long   FLEXCOMM7_IRQHandler                            /* Flexcomm Interface 7 (USART, SPI, I2C, FLEXCOMM) */
64    .long   ADC0_SEQA_IRQHandler                            /* ADC0 sequence A completion */
65    .long   ADC0_SEQB_IRQHandler                            /* ADC0 sequence B completion */
66    .long   ADC0_THCMP_IRQHandler                           /* ADC0 threshold compare and error. */
67    .long   DMIC0_IRQHandler                                /* RTC alarm and wake-up interrupts */
68    .long   HWVAD0_IRQHandler                               /* Hardware Voice Activity Detector */
69    .long   USB0_NEEDCLK_IRQHandler                         /* USB Activity Wake-up Interrupt */
70    .long   USB0_IRQHandler                                 /* USB device */
71    .long   RTC_IRQHandler                                  /* RTC alarm and wake-up interrupts */
72    .long   IOH_IRQHandler                                  /* IOH interrupt */
73    .long   MAILBOX_IRQHandler                              /* Mailbox interrupt */
74    .size    __Vectors, . - __Vectors
75
76
77
78    .text
79    .thumb
80#ifndef  SLAVEBOOT
81rel_vals:
82    .long   0xE000ED00   /* cpu_id */
83    .long   0x40000800   /* cpu_ctrl */
84    .long   0x40000804   /* coproc_boot */
85    .long   0x40000808   /* coproc_stack */
86    .short  0x0FFF
87    .short  0x0C24
88#endif
89/* Reset Handler */
90
91    .thumb_func
92    .align 2
93    .globl   Reset_Handler
94    .weak    Reset_Handler
95    .type    Reset_Handler, %function
96
97Reset_Handler:
98#ifndef  SLAVEBOOT
99/* Both the M0+ and M4 core come via this shared startup code,
100 * but the M0+ and M4 core have different vector tables.
101 * Determine if the core executing this code is the master or
102 * the slave and handle each core state individually. */
103
104shared_boot_entry:
105    ldr     r6, =rel_vals
106
107    /* Flag for slave core (0) */
108    movs    r4, 0
109    movs    r5, 1
110
111    /* Determine which core (M0+ or M4) this code is running on */
112    /* r2 = (((*cpu_id) >> 4) & 0xFFF); (M4 core == 0xC24) */
113get_current_core_id:
114    ldr     r0, [r6, #0]
115    ldr     r1, [r0]                        /* r1 = CPU ID status */
116    lsrs    r1, r1, #4                      /* Right justify 12 CPU ID bits */
117    ldrh    r2, [r6, #16]                   /* Mask for CPU ID bits */
118    ands    r2, r1, r2                      /* r2 = ARM COrtex CPU ID */
119    ldrh    r3, [r6, #18]                   /* Mask for CPU ID bits */
120    cmp     r3, r2                          /* Core ID matches M4 identifier */
121    bne     get_master_status
122    mov     r4, r5                          /* Set flag for master core (1) */
123
124    /* Determine if M4 core is the master or slave */
125    /* r3 = ((*cpu_ctrl) & 1); (0 == m0+, 1 == M4) */
126get_master_status:
127    ldr     r0, [r6, #4]
128    ldr     r3, [r0]                        /* r3 = SYSCON co-processor CPU control status */
129
130    ands    r3, r3, r5                      /* r3 = (Bit 0: 1 = M4 is master, 0 = M4 is slave) */
131
132    /* Select boot based on selected master core and core ID */
133
134select_boot:
135    eors    r3, r3, r4                      /* r4 = (Bit 0: 0 = master, 1 = slave) */
136
137    bne     slave_boot
138    b       normal_boot
139
140    /* Slave boot */
141slave_boot:
142    ldr     r0, [r6, #8]
143    ldr     r2, [r0]                        /* r1 = SYSCON co-processor boot address */
144
145    cmp     r2, #0                          /* Slave boot address = 0 (not set up)? */
146
147    beq     cpu_sleep
148    ldr     r0, [r6, #12]
149    ldr     r1, [r0]                        /* r5 = SYSCON co-processor stack address */
150
151    mov     sp, r1                          /* Update slave CPU stack pointer */
152
153    /* Be sure to update VTOR for the slave MCU to point to the */
154    /* slave vector table in boot memory */
155    bx      r2                              /* Jump to slave boot address */
156
157    /* Slave isn't yet setup for system boot from the master */
158    /* so sleep until the master sets it up and then reboots it */
159cpu_sleep:
160    mov     sp, r5                          /* Will force exception if something happens */
161cpu_sleep_wfi:
162    wfi                                     /* Sleep forever until master reboots */
163    b       cpu_sleep_wfi
164#endif /* defined(SLAVEBOOT) */
165
166#ifndef __START
167#define __START _start
168#endif
169#ifndef __ATOLLIC__
170normal_boot:
171#ifndef __NO_SYSTEM_INIT
172    ldr   r0,=SystemInit
173    blx   r0
174#endif
175/*     Loop to copy data from read only memory to RAM. The ranges
176 *      of copy from/to are specified by following symbols evaluated in
177 *      linker script.
178 *      __etext: End of code section, i.e., begin of data sections to copy from.
179 *      __data_start__/__data_end__: RAM address range that data should be
180 *      copied to. Both must be aligned to 4 bytes boundary.  */
181
182    ldr    r1, =__etext
183    ldr    r2, =__data_start__
184    ldr    r3, =__data_end__
185
186    subs    r3, r2
187    ble     .LC0
188
189.LC1:
190    subs    r3, 4
191    ldr    r0, [r1,r3]
192    str    r0, [r2,r3]
193    bgt    .LC1
194.LC0:
195
196#ifdef __STARTUP_CLEAR_BSS
197/*     This part of work usually is done in C library startup code. Otherwise,
198 *     define this macro to enable it in this startup.
199 *
200 *     Loop to zero out BSS section, which uses following symbols
201 *     in linker script:
202 *      __bss_start__: start of BSS section. Must align to 4
203 *      __bss_end__: end of BSS section. Must align to 4
204 */
205    ldr r1, =__bss_start__
206    ldr r2, =__bss_end__
207
208    subs    r2, r1
209    ble .LC3
210
211    movs    r0, 0
212.LC2:
213    str r0, [r1, r2]
214    subs    r2, 4
215    bge .LC2
216.LC3:
217#endif /* __STARTUP_CLEAR_BSS */
218    ldr   r0,=__START
219    blx   r0
220#else
221    ldr   r0,=__libc_init_array
222    blx   r0
223    ldr   r0,=main
224    bx    r0
225#endif
226
227    .pool
228    .size Reset_Handler, . - Reset_Handler
229
230    .align  1
231    .thumb_func
232    .weak DefaultISR
233    .type DefaultISR, %function
234DefaultISR:
235    b DefaultISR
236    .size DefaultISR, . - DefaultISR
237
238    .align 1
239    .thumb_func
240    .weak NMI_Handler
241    .type NMI_Handler, %function
242NMI_Handler:
243    ldr   r0,=NMI_Handler
244    bx    r0
245    .size NMI_Handler, . - NMI_Handler
246
247    .align 1
248    .thumb_func
249    .weak HardFault_Handler
250    .type HardFault_Handler, %function
251HardFault_Handler:
252    ldr   r0,=HardFault_Handler
253    bx    r0
254    .size HardFault_Handler, . - HardFault_Handler
255
256    .align 1
257    .thumb_func
258    .weak SVC_Handler
259    .type SVC_Handler, %function
260SVC_Handler:
261    ldr   r0,=SVC_Handler
262    bx    r0
263    .size SVC_Handler, . - SVC_Handler
264
265    .align 1
266    .thumb_func
267    .weak PendSV_Handler
268    .type PendSV_Handler, %function
269PendSV_Handler:
270    ldr   r0,=PendSV_Handler
271    bx    r0
272    .size PendSV_Handler, . - PendSV_Handler
273
274    .align 1
275    .thumb_func
276    .weak SysTick_Handler
277    .type SysTick_Handler, %function
278SysTick_Handler:
279    ldr   r0,=SysTick_Handler
280    bx    r0
281    .size SysTick_Handler, . - SysTick_Handler
282
283    .align 1
284    .thumb_func
285    .weak WDT_BOD_IRQHandler
286    .type WDT_BOD_IRQHandler, %function
287WDT_BOD_IRQHandler:
288    ldr   r0,=WDT_BOD_DriverIRQHandler
289    bx    r0
290    .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler
291
292
293    .align 1
294    .thumb_func
295    .weak DMA0_IRQHandler
296    .type DMA0_IRQHandler, %function
297DMA0_IRQHandler:
298    ldr   r0,=DMA0_DriverIRQHandler
299    bx    r0
300    .size DMA0_IRQHandler, . - DMA0_IRQHandler
301
302    .align 1
303    .thumb_func
304    .weak GINT0_IRQHandler
305    .type GINT0_IRQHandler, %function
306GINT0_IRQHandler:
307    ldr   r0,=GINT0_DriverIRQHandler
308    bx    r0
309    .size GINT0_IRQHandler, . - GINT0_IRQHandler
310
311    .align 1
312    .thumb_func
313    .weak GINT1_IRQHandler
314    .type GINT1_IRQHandler, %function
315GINT1_IRQHandler:
316    ldr   r0,=GINT1_DriverIRQHandler
317    bx    r0
318    .size GINT1_IRQHandler, . - GINT1_IRQHandler
319
320    .align 1
321    .thumb_func
322    .weak PIN_INT0_IRQHandler
323    .type PIN_INT0_IRQHandler, %function
324PIN_INT0_IRQHandler:
325    ldr   r0,=PIN_INT0_DriverIRQHandler
326    bx    r0
327    .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler
328
329    .align 1
330    .thumb_func
331    .weak PIN_INT1_IRQHandler
332    .type PIN_INT1_IRQHandler, %function
333PIN_INT1_IRQHandler:
334    ldr   r0,=PIN_INT1_DriverIRQHandler
335    bx    r0
336    .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler
337
338    .align 1
339    .thumb_func
340    .weak PIN_INT2_IRQHandler
341    .type PIN_INT2_IRQHandler, %function
342PIN_INT2_IRQHandler:
343    ldr   r0,=PIN_INT2_DriverIRQHandler
344    bx    r0
345    .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler
346
347    .align 1
348    .thumb_func
349    .weak PIN_INT3_IRQHandler
350    .type PIN_INT3_IRQHandler, %function
351PIN_INT3_IRQHandler:
352    ldr   r0,=PIN_INT3_DriverIRQHandler
353    bx    r0
354    .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler
355
356    .align 1
357    .thumb_func
358    .weak UTICK0_IRQHandler
359    .type UTICK0_IRQHandler, %function
360UTICK0_IRQHandler:
361    ldr   r0,=UTICK0_DriverIRQHandler
362    bx    r0
363    .size UTICK0_IRQHandler, . - UTICK0_IRQHandler
364
365    .align 1
366    .thumb_func
367    .weak MRT0_IRQHandler
368    .type MRT0_IRQHandler, %function
369MRT0_IRQHandler:
370    ldr   r0,=MRT0_DriverIRQHandler
371    bx    r0
372    .size MRT0_IRQHandler, . - MRT0_IRQHandler
373
374    .align 1
375    .thumb_func
376    .weak CTIMER0_IRQHandler
377    .type CTIMER0_IRQHandler, %function
378CTIMER0_IRQHandler:
379    ldr   r0,=CTIMER0_DriverIRQHandler
380    bx    r0
381    .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler
382
383    .align 1
384    .thumb_func
385    .weak CTIMER1_IRQHandler
386    .type CTIMER1_IRQHandler, %function
387CTIMER1_IRQHandler:
388    ldr   r0,=CTIMER1_DriverIRQHandler
389    bx    r0
390    .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler
391
392
393    .align 1
394    .thumb_func
395    .weak SCT0_IRQHandler
396    .type SCT0_IRQHandler, %function
397SCT0_IRQHandler:
398    ldr   r0,=SCT0_DriverIRQHandler
399    bx    r0
400    .size SCT0_IRQHandler, . - SCT0_IRQHandler
401
402    .align 1
403    .thumb_func
404    .weak CTIMER3_IRQHandler
405    .type CTIMER3_IRQHandler, %function
406CTIMER3_IRQHandler:
407    ldr   r0,=CTIMER3_DriverIRQHandler
408    bx    r0
409    .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler
410
411    .align 1
412    .thumb_func
413    .weak FLEXCOMM0_IRQHandler
414    .type FLEXCOMM0_IRQHandler, %function
415FLEXCOMM0_IRQHandler:
416    ldr   r0,=FLEXCOMM0_DriverIRQHandler
417    bx    r0
418    .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler
419
420    .align 1
421    .thumb_func
422    .weak FLEXCOMM1_IRQHandler
423    .type FLEXCOMM1_IRQHandler, %function
424FLEXCOMM1_IRQHandler:
425    ldr   r0,=FLEXCOMM1_DriverIRQHandler
426    bx    r0
427    .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler
428
429    .align 1
430    .thumb_func
431    .weak FLEXCOMM2_IRQHandler
432    .type FLEXCOMM2_IRQHandler, %function
433FLEXCOMM2_IRQHandler:
434    ldr   r0,=FLEXCOMM2_DriverIRQHandler
435    bx    r0
436    .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler
437
438    .align 1
439    .thumb_func
440    .weak FLEXCOMM3_IRQHandler
441    .type FLEXCOMM3_IRQHandler, %function
442FLEXCOMM3_IRQHandler:
443    ldr   r0,=FLEXCOMM3_DriverIRQHandler
444    bx    r0
445    .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler
446
447    .align 1
448    .thumb_func
449    .weak FLEXCOMM4_IRQHandler
450    .type FLEXCOMM4_IRQHandler, %function
451FLEXCOMM4_IRQHandler:
452    ldr   r0,=FLEXCOMM4_DriverIRQHandler
453    bx    r0
454    .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler
455
456    .align 1
457    .thumb_func
458    .weak FLEXCOMM5_IRQHandler
459    .type FLEXCOMM5_IRQHandler, %function
460FLEXCOMM5_IRQHandler:
461    ldr   r0,=FLEXCOMM5_DriverIRQHandler
462    bx    r0
463    .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler
464
465    .align 1
466    .thumb_func
467    .weak FLEXCOMM6_IRQHandler
468    .type FLEXCOMM6_IRQHandler, %function
469FLEXCOMM6_IRQHandler:
470    ldr   r0,=FLEXCOMM6_DriverIRQHandler
471    bx    r0
472    .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler
473
474    .align 1
475    .thumb_func
476    .weak FLEXCOMM7_IRQHandler
477    .type FLEXCOMM7_IRQHandler, %function
478FLEXCOMM7_IRQHandler:
479    ldr   r0,=FLEXCOMM7_DriverIRQHandler
480    bx    r0
481    .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler
482
483
484    .align 1
485    .thumb_func
486    .weak ADC0_SEQA_IRQHandler
487    .type ADC0_SEQA_IRQHandler, %function
488ADC0_SEQA_IRQHandler:
489    ldr   r0,=ADC0_SEQA_DriverIRQHandler
490    bx    r0
491    .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler
492
493    .align 1
494    .thumb_func
495    .weak ADC0_SEQB_IRQHandler
496    .type ADC0_SEQB_IRQHandler, %function
497ADC0_SEQB_IRQHandler:
498    ldr   r0,=ADC0_SEQB_DriverIRQHandler
499    bx    r0
500    .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler
501
502    .align 1
503    .thumb_func
504    .weak ADC0_THCMP_IRQHandler
505    .type ADC0_THCMP_IRQHandler, %function
506ADC0_THCMP_IRQHandler:
507    ldr   r0,=ADC0_THCMP_DriverIRQHandler
508    bx    r0
509    .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler
510
511    .align 1
512    .thumb_func
513    .weak DMIC0_IRQHandler
514    .type DMIC0_IRQHandler, %function
515DMIC0_IRQHandler:
516    ldr   r0,=DMIC0_DriverIRQHandler
517    bx    r0
518    .size DMIC0_IRQHandler, . - DMIC0_IRQHandler
519
520    .align 1
521    .thumb_func
522    .weak HWVAD0_IRQHandler
523    .type HWVAD0_IRQHandler, %function
524HWVAD0_IRQHandler:
525    ldr   r0,=HWVAD0_DriverIRQHandler
526    bx    r0
527    .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler
528
529    .align 1
530    .thumb_func
531    .weak USB0_NEEDCLK_IRQHandler
532    .type USB0_NEEDCLK_IRQHandler, %function
533USB0_NEEDCLK_IRQHandler:
534    ldr   r0,=USB0_NEEDCLK_DriverIRQHandler
535    bx    r0
536    .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler
537
538    .align 1
539    .thumb_func
540    .weak USB0_IRQHandler
541    .type USB0_IRQHandler, %function
542USB0_IRQHandler:
543    ldr   r0,=USB0_DriverIRQHandler
544    bx    r0
545    .size USB0_IRQHandler, . - USB0_IRQHandler
546
547    .align 1
548    .thumb_func
549    .weak RTC_IRQHandler
550    .type RTC_IRQHandler, %function
551RTC_IRQHandler:
552    ldr   r0,=RTC_DriverIRQHandler
553    bx    r0
554    .size RTC_IRQHandler, . - RTC_IRQHandler
555
556    .align 1
557    .thumb_func
558    .weak IOH_IRQHandler
559    .type IOH_IRQHandler, %function
560IOH_IRQHandler:
561    ldr   r0,=IOH_DriverIRQHandler
562    bx    r0
563    .size IOH_IRQHandler, . - IOH_IRQHandler
564
565    .align 1
566    .thumb_func
567    .weak MAILBOX_IRQHandler
568    .type MAILBOX_IRQHandler, %function
569MAILBOX_IRQHandler:
570    ldr   r0,=MAILBOX_DriverIRQHandler
571    bx    r0
572    .size MAILBOX_IRQHandler, . - MAILBOX_IRQHandler
573
574
575/*    Macro to define default handlers. Default handler
576 *    will be weak symbol and just dead loops. They can be
577 *    overwritten by other handlers */
578    .macro def_irq_handler  handler_name
579    .weak \handler_name
580    .set  \handler_name, DefaultISR
581    .endm
582
583/* Exception Handlers */
584    def_irq_handler     WDT_BOD_DriverIRQHandler       /* Windowed watchdog timer, Brownout detect */
585    def_irq_handler     DMA0_DriverIRQHandler          /* DMA controller */
586    def_irq_handler     GINT0_DriverIRQHandler         /* GPIO group 0 */
587    def_irq_handler     GINT1_DriverIRQHandler         /* GPIO group 1 */
588    def_irq_handler     PIN_INT0_DriverIRQHandler      /* Pin interrupt 0 or pattern match engine slice 0 */
589    def_irq_handler     PIN_INT1_DriverIRQHandler      /* Pin interrupt 1or pattern match engine slice 1 */
590    def_irq_handler     PIN_INT2_DriverIRQHandler      /* Pin interrupt 2 or pattern match engine slice 2 */
591    def_irq_handler     PIN_INT3_DriverIRQHandler      /* Pin interrupt 3 or pattern match engine slice 3 */
592    def_irq_handler     UTICK0_DriverIRQHandler        /* Micro-tick Timer */
593    def_irq_handler     MRT0_DriverIRQHandler          /* Multi-rate timer */
594    def_irq_handler     CTIMER0_DriverIRQHandler       /* Standard counter/timer CTIMER0 */
595    def_irq_handler     CTIMER1_DriverIRQHandler       /* Standard counter/timer CTIMER1 */
596    def_irq_handler     SCT0_DriverIRQHandler          /* SCTimer/PWM */
597    def_irq_handler     CTIMER3_DriverIRQHandler       /* Standard counter/timer CTIMER3 */
598    def_irq_handler     FLEXCOMM0_DriverIRQHandler     /* Flexcomm Interface 0 (USART, SPI, I2C) */
599    def_irq_handler     FLEXCOMM1_DriverIRQHandler     /* Flexcomm Interface 1 (USART, SPI, I2C) */
600    def_irq_handler     FLEXCOMM2_DriverIRQHandler     /* Flexcomm Interface 2 (USART, SPI, I2C) */
601    def_irq_handler     FLEXCOMM3_DriverIRQHandler     /* Flexcomm Interface 3 (USART, SPI, I2C) */
602    def_irq_handler     FLEXCOMM4_DriverIRQHandler     /* Flexcomm Interface 4 (USART, SPI, I2C) */
603    def_irq_handler     FLEXCOMM5_DriverIRQHandler     /* Flexcomm Interface 5 (USART, SPI, I2C) */
604    def_irq_handler     FLEXCOMM6_DriverIRQHandler     /* Flexcomm Interface 6 (USART, SPI, I2C, I2S) */
605    def_irq_handler     FLEXCOMM7_DriverIRQHandler     /* Flexcomm Interface 7 (USART, SPI, I2C, I2S) */
606    def_irq_handler     ADC0_SEQA_DriverIRQHandler     /* ADC0 sequence A completion. */
607    def_irq_handler     ADC0_SEQB_DriverIRQHandler     /* ADC0 sequence B completion. */
608    def_irq_handler     ADC0_THCMP_DriverIRQHandler    /* ADC0 threshold compare and error. */
609    def_irq_handler     DMIC0_DriverIRQHandler         /* Digital microphone and DMIC subsystem */
610    def_irq_handler     HWVAD0_DriverIRQHandler        /* Hardware Voice sActivity Detector */
611    def_irq_handler     USB0_NEEDCLK_DriverIRQHandler  /* USB Activity Wake-up Interrupt */
612    def_irq_handler     USB0_DriverIRQHandler          /* USB device */
613    def_irq_handler     RTC_DriverIRQHandler           /* RTC alarm and wake-up interrupts */
614    def_irq_handler     IOH_DriverIRQHandler           /* IOH */
615    def_irq_handler     MAILBOX_DriverIRQHandler       /* Mailbox interrupt (present on selected devices) */
616
617    .end
618