1 /*
2  * Copyright (c) 2016, Freescale Semiconductor, Inc.
3  * Copyright 2016, NXP
4  * All rights reserved.
5  *
6  *
7  * SPDX-License-Identifier: BSD-3-Clause
8  */
9 
10 #ifndef _FSL_RESET_H_
11 #define _FSL_RESET_H_
12 
13 #include <assert.h>
14 #include <stdbool.h>
15 #include <stdint.h>
16 #include <string.h>
17 #include "fsl_device_registers.h"
18 
19 /*! @addtogroup reset */
20 /*! @{ */
21 
22 /*! @file */
23 
24 /*******************************************************************************
25  * Definitions
26  ******************************************************************************/
27 
28 /*! @name Driver version */
29 /*@{*/
30 /*! @brief reset driver version 2.0.0. */
31 #define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
32 /*@}*/
33 
34 /*!
35  * @brief Enumeration for peripheral reset control bits
36  *
37  * Defines the enumeration for peripheral reset control bits in PRESETCTRL/ASYNCPRESETCTRL registers
38  */
39 typedef enum _SYSCON_RSTn
40 {
41     kSPIFI_RST_SHIFT_RSTn = 0 | 10U,         /**< SPIFI reset control */
42     kMUX_RST_SHIFT_RSTn = 0 | 11U,           /**< Input mux reset control */
43     kIOCON_RST_SHIFT_RSTn = 0 | 13U,         /**< IOCON reset control */
44     kGPIO0_RST_SHIFT_RSTn = 0 | 14U,         /**< GPIO0 reset control */
45     kGPIO1_RST_SHIFT_RSTn = 0 | 15U,         /**< GPIO1 reset control */
46     kGPIO2_RST_SHIFT_RSTn = 0 | 16U,         /**< GPIO2 reset control */
47     kGPIO3_RST_SHIFT_RSTn = 0 | 17U,         /**< GPIO3 reset control */
48     kPINT_RST_SHIFT_RSTn = 0 | 18U,          /**< Pin interrupt (PINT) reset control */
49     kGINT_RST_SHIFT_RSTn = 0 | 19U,          /**< Grouped interrupt (PINT) reset control. */
50     kDMA_RST_SHIFT_RSTn = 0 | 20U,           /**< DMA reset control */
51     kCRC_RST_SHIFT_RSTn = 0 | 21U,           /**< CRC reset control */
52     kWWDT_RST_SHIFT_RSTn = 0 | 22U,          /**< Watchdog timer reset control */
53     kADC0_RST_SHIFT_RSTn = 0 | 27U,          /**< ADC0 reset control */
54 
55     kMRT_RST_SHIFT_RSTn = 65536 | 0U,        /**< Multi-rate timer (MRT) reset control */
56     kSCT0_RST_SHIFT_RSTn = 65536 | 2U,       /**< SCTimer/PWM 0 (SCT0) reset control */
57     kMCAN0_RST_SHIFT_RSTn = 65536 | 7U,      /**< MCAN0 reset control */
58     kMCAN1_RST_SHIFT_RSTn = 65536 | 8U,      /**< MCAN1 reset control */
59     kUTICK_RST_SHIFT_RSTn = 65536 | 10U,     /**< Micro-tick timer reset control */
60     kFC0_RST_SHIFT_RSTn = 65536 | 11U,       /**< Flexcomm Interface 0 reset control */
61     kFC1_RST_SHIFT_RSTn = 65536 | 12U,       /**< Flexcomm Interface 1 reset control */
62     kFC2_RST_SHIFT_RSTn = 65536 | 13U,       /**< Flexcomm Interface 2 reset control */
63     kFC3_RST_SHIFT_RSTn = 65536 | 14U,       /**< Flexcomm Interface 3 reset control */
64     kFC4_RST_SHIFT_RSTn = 65536 | 15U,       /**< Flexcomm Interface 4 reset control */
65     kFC5_RST_SHIFT_RSTn = 65536 | 16U,       /**< Flexcomm Interface 5 reset control */
66     kFC6_RST_SHIFT_RSTn = 65536 | 17U,       /**< Flexcomm Interface 6 reset control */
67     kFC7_RST_SHIFT_RSTn = 65536 | 18U,       /**< Flexcomm Interface 7 reset control */
68     kDMIC_RST_SHIFT_RSTn = 65536 | 19U,      /**< Digital microphone interface reset control */
69     kCT32B2_RST_SHIFT_RSTn = 65536 | 22U,    /**< CT32B2 reset control */
70     kUSB0D_RST_SHIFT_RSTn = 65536 | 25U,     /**< USB0D reset control */
71     kCT32B0_RST_SHIFT_RSTn = 65536 | 26U,    /**< CT32B0 reset control */
72     kCT32B1_RST_SHIFT_RSTn = 65536 | 27U,    /**< CT32B1 reset control */
73 
74     kLCD_RST_SHIFT_RSTn = 131072 | 2U,       /**< LCD reset control */
75     kSDIO_RST_SHIFT_RSTn = 131072 | 3U,      /**< SDIO reset control */
76     kUSB1H_RST_SHIFT_RSTn = 131072 | 4U,     /**< USB1H reset control */
77     kUSB1D_RST_SHIFT_RSTn = 131072 | 5U,     /**< USB1D reset control */
78     kUSB1RAM_RST_SHIFT_RSTn = 131072 | 6U,   /**< USB1RAM reset control */
79     kEMC_RST_SHIFT_RSTn = 131072 | 7U,       /**< EMC reset control */
80     kETH_RST_SHIFT_RSTn = 131072 | 8U,       /**< ETH reset control */
81     kGPIO4_RST_SHIFT_RSTn = 131072 | 9U,     /**< GPIO4 reset control */
82     kGPIO5_RST_SHIFT_RSTn = 131072 | 10U,    /**< GPIO5 reset control */
83     kAES_RST_SHIFT_RSTn = 131072 | 11U,      /**< AES reset control */
84     kOTP_RST_SHIFT_RSTn = 131072 | 12U,      /**< OTP reset control */
85     kRNG_RST_SHIFT_RSTn = 131072 | 13U,      /**< RNG  reset control */
86     kFC8_RST_SHIFT_RSTn = 131072 | 14U,      /**< Flexcomm Interface 8 reset control */
87     kFC9_RST_SHIFT_RSTn = 131072 | 15U,      /**< Flexcomm Interface 9 reset control */
88     kUSB0HMR_RST_SHIFT_RSTn = 131072 | 16U,  /**< USB0HMR reset control */
89     kUSB0HSL_RST_SHIFT_RSTn = 131072 | 17U,  /**< USB0HSL reset control */
90     kSHA_RST_SHIFT_RSTn = 131072 | 18U,      /**< SHA reset control */
91     kSC0_RST_SHIFT_RSTn = 131072 | 19U,      /**< SC0 reset control */
92     kSC1_RST_SHIFT_RSTn = 131072 | 20U,      /**< SC1 reset control */
93     kFC10_RST_SHIFT_RSTn = 131072 | 21U,     /**< Flexcomm Interface 10 reset control */
94 
95     kCT32B3_RST_SHIFT_RSTn = 67108864 | 13U, /**< CT32B3 reset control */
96     kCT32B4_RST_SHIFT_RSTn = 67108864 | 14U, /**< CT32B4 reset control */
97 } SYSCON_RSTn_t;
98 
99 /** Array initializers with peripheral reset bits **/
100 #define ADC_RSTS             \
101     {                        \
102         kADC0_RST_SHIFT_RSTn \
103     } /* Reset bits for ADC peripheral */
104 #define AES_RSTS             \
105     {                        \
106         kAES_RST_SHIFT_RSTn  \
107     } /* Reset bits for AES peripheral */
108 #define CRC_RSTS            \
109     {                       \
110         kCRC_RST_SHIFT_RSTn \
111     } /* Reset bits for CRC peripheral */
112 #define CTIMER_RSTS                                                                                     \
113     {                                                                                                   \
114         kCT32B0_RST_SHIFT_RSTn, kCT32B1_RST_SHIFT_RSTn, kCT32B2_RST_SHIFT_RSTn, kCT32B3_RST_SHIFT_RSTn, \
115             kCT32B4_RST_SHIFT_RSTn                                                                      \
116     } /* Reset bits for CTIMER peripheral */
117 #define DMA_RSTS_N            \
118     {                       \
119         kDMA_RST_SHIFT_RSTn \
120     } /* Reset bits for DMA peripheral */
121 #define DMIC_RSTS            \
122     {                        \
123         kDMIC_RST_SHIFT_RSTn \
124     } /* Reset bits for DMIC peripheral */
125 #define EMC_RSTS             \
126     {                        \
127         kEMC_RST_SHIFT_RSTn  \
128     } /* Reset bits for EMC peripheral */
129 #define ETH_RST              \
130     {                        \
131         kETH_RST_SHIFT_RSTn  \
132     } /* Reset bits for EMC peripheral */
133 #define FLEXCOMM_RSTS                                                                                            \
134     {                                                                                                            \
135         kFC0_RST_SHIFT_RSTn, kFC1_RST_SHIFT_RSTn, kFC2_RST_SHIFT_RSTn, kFC3_RST_SHIFT_RSTn, kFC4_RST_SHIFT_RSTn, \
136             kFC5_RST_SHIFT_RSTn, kFC6_RST_SHIFT_RSTn, kFC7_RST_SHIFT_RSTn, kFC8_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn, kFC9_RST_SHIFT_RSTn   \
137     } /* Reset bits for FLEXCOMM peripheral */
138 #define GINT_RSTS                                  \
139     {                                              \
140         kGINT_RST_SHIFT_RSTn, kGINT_RST_SHIFT_RSTn \
141     } /* Reset bits for GINT peripheral. GINT0 & GINT1 share same slot */
142 #define GPIO_RSTS_N                                    \
143     {                                                \
144         kGPIO0_RST_SHIFT_RSTn, kGPIO1_RST_SHIFT_RSTn, kGPIO2_RST_SHIFT_RSTn, kGPIO3_RST_SHIFT_RSTn,  \
145         kGPIO4_RST_SHIFT_RSTn, kGPIO5_RST_SHIFT_RSTn                                                 \
146     } /* Reset bits for GPIO peripheral */
147 #define INPUTMUX_RSTS       \
148     {                       \
149         kMUX_RST_SHIFT_RSTn \
150     } /* Reset bits for INPUTMUX peripheral */
151 #define IOCON_RSTS            \
152     {                         \
153         kIOCON_RST_SHIFT_RSTn \
154     } /* Reset bits for IOCON peripheral */
155 #define FLASH_RSTS                                 \
156     {                                              \
157         kFLASH_RST_SHIFT_RSTn, kFMC_RST_SHIFT_RSTn \
158     } /* Reset bits for Flash peripheral */
159 #define LCD_RSTS                                 \
160     {                                            \
161         kLCD_RST_SHIFT_RSTn                      \
162     } /* Reset bits for LCD peripheral */
163 #define MRT_RSTS            \
164     {                       \
165         kMRT_RST_SHIFT_RSTn \
166     } /* Reset bits for MRT peripheral */
167 #define MCAN_RSTS                                   \
168     {                                               \
169         kMCAN0_RST_SHIFT_RSTn,kMCAN1_RST_SHIFT_RSTn \
170     } /* Reset bits for MCAN0&MACN1 peripheral */
171 #define OTP_RSTS            \
172     {                       \
173         kOTP_RST_SHIFT_RSTn \
174     } /* Reset bits for OTP peripheral */
175 #define PINT_RSTS            \
176     {                        \
177         kPINT_RST_SHIFT_RSTn \
178     } /* Reset bits for PINT peripheral */
179 #define RNG_RSTS             \
180     {                        \
181         kRNG_RST_SHIFT_RSTn  \
182     } /* Reset bits for RNG peripheral */
183 #define SDIO_RST             \
184     {                        \
185         kSDIO_RST_SHIFT_RSTn \
186     } /* Reset bits for SDIO peripheral */
187 #define SCT_RSTS             \
188     {                        \
189         kSCT0_RST_SHIFT_RSTn \
190     } /* Reset bits for SCT peripheral */
191 #define SHA_RST              \
192     {                        \
193         kSHA_RST_SHIFT_RSTn  \
194     } /* Reset bits for SHA peripheral */
195 #define SPIFI_RSTS            \
196     {                         \
197         kSPIFI_RST_SHIFT_RSTn \
198     } /* Reset bits for SPIFI peripheral */
199 #define USB0D_RST             \
200     {                         \
201         kUSB0D_RST_SHIFT_RSTn \
202     } /* Reset bits for USB0D peripheral */
203 #define USB0HMR_RST             \
204     {                           \
205         kUSB0HMR_RST_SHIFT_RSTn \
206     } /* Reset bits for USB0HMR peripheral */
207 #define USB0HSL_RST             \
208     {                           \
209         kUSB0HSL_RST_SHIFT_RSTn \
210     } /* Reset bits for USB0HSL peripheral */
211 #define USB1H_RST             \
212     {                         \
213         kUSB1H_RST_SHIFT_RSTn \
214     } /* Reset bits for USB1H peripheral */
215 #define USB1D_RST             \
216     {                         \
217         kUSB1D_RST_SHIFT_RSTn \
218     } /* Reset bits for USB1D peripheral */
219 #define USB1RAM_RST             \
220     {                           \
221         kUSB1RAM_RST_SHIFT_RSTn \
222     } /* Reset bits for USB1RAM peripheral */
223 #define UTICK_RSTS            \
224     {                         \
225         kUTICK_RST_SHIFT_RSTn \
226     } /* Reset bits for UTICK peripheral */
227 #define WWDT_RSTS            \
228     {                        \
229         kWWDT_RST_SHIFT_RSTn \
230     } /* Reset bits for WWDT peripheral */
231 
232 typedef SYSCON_RSTn_t reset_ip_name_t;
233 
234 /*******************************************************************************
235  * API
236  ******************************************************************************/
237 #if defined(__cplusplus)
238 extern "C" {
239 #endif
240 
241 /*!
242  * @brief Assert reset to peripheral.
243  *
244  * Asserts reset signal to specified peripheral module.
245  *
246  * @param peripheral Assert reset to this peripheral. The enum argument contains encoding of reset register
247  *                   and reset bit position in the reset register.
248  */
249 void RESET_SetPeripheralReset(reset_ip_name_t peripheral);
250 
251 /*!
252  * @brief Clear reset to peripheral.
253  *
254  * Clears reset signal to specified peripheral module, allows it to operate.
255  *
256  * @param peripheral Clear reset to this peripheral. The enum argument contains encoding of reset register
257  *                   and reset bit position in the reset register.
258  */
259 void RESET_ClearPeripheralReset(reset_ip_name_t peripheral);
260 
261 /*!
262  * @brief Reset peripheral module.
263  *
264  * Reset peripheral module.
265  *
266  * @param peripheral Peripheral to reset. The enum argument contains encoding of reset register
267  *                   and reset bit position in the reset register.
268  */
269 void RESET_PeripheralReset(reset_ip_name_t peripheral);
270 
271 #if defined(__cplusplus)
272 }
273 #endif
274 
275 /*! @} */
276 
277 #endif /* _FSL_RESET_H_ */
278