1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2017,2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to setup clock using clock driver functions:
14 *
15 * 1. Call CLOCK_InitXXX() to configure corresponding SCG clock source.
16 * Note: The clock could not be set when it is being used as system clock.
17 * In default out of reset, the CPU is clocked from FIRC(IRC48M),
18 * so before setting FIRC, change to use another avaliable clock source.
19 *
20 * 2. Call CLOCK_SetXtal0Freq() to set XTAL0 frequency based on board settings.
21 *
22 * 3. Call CLOCK_SetXxxModeSysClkConfig() to set SCG mode for Xxx run mode.
23 * Wait until the system clock source is changed to target source.
24 *
25 * 4. If power mode change is needed, call SMC_SetPowerModeProtection() to allow
26 * corresponding power mode and SMC_SetPowerModeXxx() to change to Xxx mode.
27 * Supported run mode and clock restrictions could be found in Reference Manual.
28 */
29
30 /* clang-format off */
31 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
32 !!GlobalInfo
33 product: Clocks v7.0
34 processor: MKE18F512xxx16
35 package_id: MKE18F512VLL16
36 mcu_data: ksdk2_0
37 processor_version: 0.7.1
38 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
39 /* clang-format on */
40
41 #include "fsl_smc.h"
42 #include "clock_config.h"
43
44 /*******************************************************************************
45 * Definitions
46 ******************************************************************************/
47
48 /*******************************************************************************
49 * Variables
50 ******************************************************************************/
51 /* System clock frequency. */
52 extern uint32_t SystemCoreClock;
53
54 /*******************************************************************************
55 * Code
56 ******************************************************************************/
57 /*FUNCTION**********************************************************************
58 *
59 * Function Name : CLOCK_CONFIG_FircSafeConfig
60 * Description : This function is used to safely configure FIRC clock.
61 * In default out of reset, the CPU is clocked from FIRC(IRC48M).
62 * Before setting FIRC, change to use SIRC as system clock,
63 * then configure FIRC. After FIRC is set, change back to use FIRC
64 * in case SIRC need to be configured.
65 * Param fircConfig : FIRC configuration.
66 *
67 *END**************************************************************************/
CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t * fircConfig)68 static void CLOCK_CONFIG_FircSafeConfig(const scg_firc_config_t *fircConfig)
69 {
70 scg_sys_clk_config_t curConfig;
71 const scg_sirc_config_t scgSircConfig = {.enableMode = kSCG_SircEnable,
72 .div1 = kSCG_AsyncClkDisable,
73 .div2 = kSCG_AsyncClkDivBy2,
74 .range = kSCG_SircRangeHigh};
75 scg_sys_clk_config_t sysClkSafeConfigSource = {
76 .divSlow = kSCG_SysClkDivBy4, /* Slow clock divider */
77 .divBus = kSCG_SysClkDivBy1, /* Bus clock divider */
78 .divCore = kSCG_SysClkDivBy1, /* Core clock divider */
79 .src = kSCG_SysClkSrcSirc /* System clock source */
80 };
81 /* Init Sirc. */
82 CLOCK_InitSirc(&scgSircConfig);
83 /* Change to use SIRC as system clock source to prepare to change FIRCCFG register. */
84 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
85 /* Wait for clock source switch finished. */
86 do
87 {
88 CLOCK_GetCurSysClkConfig(&curConfig);
89 } while (curConfig.src != sysClkSafeConfigSource.src);
90
91 /* Init Firc. */
92 CLOCK_InitFirc(fircConfig);
93 /* Change back to use FIRC as system clock source in order to configure SIRC if needed. */
94 sysClkSafeConfigSource.src = kSCG_SysClkSrcFirc;
95 CLOCK_SetRunModeSysClkConfig(&sysClkSafeConfigSource);
96 /* Wait for clock source switch finished. */
97 do
98 {
99 CLOCK_GetCurSysClkConfig(&curConfig);
100 } while (curConfig.src != sysClkSafeConfigSource.src);
101 }
102
103 /*******************************************************************************
104 ************************ BOARD_InitBootClocks function ************************
105 ******************************************************************************/
BOARD_InitBootClocks(void)106 void BOARD_InitBootClocks(void)
107 {
108 BOARD_BootClockRUN();
109 }
110
111 /*******************************************************************************
112 ********************* Configuration BOARD_BootClockVLPR ***********************
113 ******************************************************************************/
114 /* clang-format off */
115 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
116 !!Configuration
117 name: BOARD_BootClockVLPR
118 outputs:
119 - {id: Bus_clock.outFreq, value: 2 MHz}
120 - {id: Core_clock.outFreq, value: 4 MHz}
121 - {id: Flash_clock.outFreq, value: 500 kHz}
122 - {id: LPO1KCLK.outFreq, value: 1 kHz}
123 - {id: LPO_clock.outFreq, value: 128 kHz}
124 - {id: SOSCDIV1_CLK.outFreq, value: 8 MHz}
125 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
126 - {id: SOSC_CLK.outFreq, value: 8 MHz}
127 - {id: System_clock.outFreq, value: 4 MHz}
128 settings:
129 - {id: SCGMode, value: SOSC}
130 - {id: powerMode, value: VLPR}
131 - {id: SCG.DIVBUS.scale, value: '2'}
132 - {id: SCG.DIVCORE.scale, value: '2'}
133 - {id: SCG.DIVSLOW.scale, value: '8', locked: true}
134 - {id: SCG.FIRCDIV1.scale, value: '1'}
135 - {id: SCG.FIRCDIV2.scale, value: '1'}
136 - {id: SCG.SCSSEL.sel, value: SCG.SOSC}
137 - {id: SCG.SIRCDIV1.scale, value: '1'}
138 - {id: SCG.SIRCDIV2.scale, value: '2'}
139 - {id: SCG.SOSCDIV1.scale, value: '1'}
140 - {id: SCG.SOSCDIV2.scale, value: '1'}
141 - {id: SCG.SPLLDIV1.scale, value: '1'}
142 - {id: SCG.SPLLDIV2.scale, value: '2'}
143 - {id: SCG.SPLL_mul.scale, value: '30'}
144 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
145 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
146 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
147 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
148 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
149 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
150 sources:
151 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
152 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
153 /* clang-format on */
154
155 /*******************************************************************************
156 * Variables for BOARD_BootClockVLPR configuration
157 ******************************************************************************/
158 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockVLPR = {
159 .divSlow = kSCG_SysClkDivBy8, /* Slow Clock Divider: divided by 8 */
160 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
161 .divCore = kSCG_SysClkDivBy2, /* Core Clock Divider: divided by 2 */
162 .src = kSCG_SysClkSrcSysOsc, /* System OSC is selected as System Clock Source */
163 };
164 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockVLPR = {
165 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
166 .enableMode = kSCG_SysOscEnable |
167 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
168 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
169 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
170 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
171 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
172 };
173 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockVLPR = {
174 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
175 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
176 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
177 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
178 };
179 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockVLPR = {
180 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
181 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
182 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
183 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
184 .trimConfig = NULL, /* Fast IRC Trim disabled */
185 };
186 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockVLPR = {
187 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
188 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
189 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
190 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
191 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
192 .prediv = 0, /* Divided by 1 */
193 .mult = 14, /* Multiply Factor is 30 */
194 };
195 /*******************************************************************************
196 * Code for BOARD_BootClockVLPR configuration
197 ******************************************************************************/
BOARD_BootClockVLPR(void)198 void BOARD_BootClockVLPR(void)
199 {
200 /* Init SOSC according to board configuration. */
201 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockVLPR);
202 /* Set the XTAL0 frequency based on board settings. */
203 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockVLPR.freq);
204 /* Set SCG to SOSC mode. */
205 CLOCK_SetVlprModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockVLPR);
206 /* Allow SMC all power modes. */
207 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
208 /* Set VLPR power mode. */
209 SMC_SetPowerModeVlpr(SMC);
210 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
211 {
212 }
213 /* Set SystemCoreClock variable. */
214 SystemCoreClock = BOARD_BOOTCLOCKVLPR_CORE_CLOCK;
215 }
216
217 /*******************************************************************************
218 ********************** Configuration BOARD_BootClockRUN ***********************
219 ******************************************************************************/
220 /* clang-format off */
221 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
222 !!Configuration
223 name: BOARD_BootClockRUN
224 called_from_default_init: true
225 outputs:
226 - {id: Bus_clock.outFreq, value: 60 MHz}
227 - {id: Core_clock.outFreq, value: 120 MHz}
228 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
229 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
230 - {id: Flash_clock.outFreq, value: 24 MHz}
231 - {id: LPO1KCLK.outFreq, value: 1 kHz}
232 - {id: LPO_clock.outFreq, value: 128 kHz}
233 - {id: PLLDIV1_CLK.outFreq, value: 120 MHz}
234 - {id: PLLDIV2_CLK.outFreq, value: 60 MHz}
235 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
236 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
237 - {id: SIRC_CLK.outFreq, value: 8 MHz}
238 - {id: SOSCDIV1_CLK.outFreq, value: 8 MHz}
239 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
240 - {id: SOSC_CLK.outFreq, value: 8 MHz}
241 - {id: System_clock.outFreq, value: 120 MHz}
242 settings:
243 - {id: SCGMode, value: SPLL}
244 - {id: SCG.DIVBUS.scale, value: '2'}
245 - {id: SCG.DIVSLOW.scale, value: '5'}
246 - {id: SCG.FIRCDIV1.scale, value: '1'}
247 - {id: SCG.FIRCDIV2.scale, value: '1'}
248 - {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
249 - {id: SCG.SIRCDIV1.scale, value: '1'}
250 - {id: SCG.SIRCDIV2.scale, value: '2'}
251 - {id: SCG.SOSCDIV1.scale, value: '1'}
252 - {id: SCG.SOSCDIV2.scale, value: '1'}
253 - {id: SCG.SPLLDIV1.scale, value: '1'}
254 - {id: SCG.SPLLDIV2.scale, value: '2'}
255 - {id: SCG.SPLL_mul.scale, value: '30'}
256 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
257 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
258 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
259 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
260 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
261 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
262 sources:
263 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
264 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
265 /* clang-format on */
266
267 /*******************************************************************************
268 * Variables for BOARD_BootClockRUN configuration
269 ******************************************************************************/
270 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockRUN = {
271 .divSlow = kSCG_SysClkDivBy5, /* Slow Clock Divider: divided by 5 */
272 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
273 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
274 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
275 };
276 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockRUN = {
277 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
278 .enableMode = kSCG_SysOscEnable |
279 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
280 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
281 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
282 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
283 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
284 };
285 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockRUN = {
286 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
287 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
288 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
289 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
290 };
291 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockRUN = {
292 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
293 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
294 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
295 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
296 .trimConfig = NULL, /* Fast IRC Trim disabled */
297 };
298 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockRUN = {
299 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
300 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
301 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
302 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
303 .src = kSCG_SysPllSrcSysOsc, /* System PLL clock source is System OSC */
304 .prediv = 0, /* Divided by 1 */
305 .mult = 14, /* Multiply Factor is 30 */
306 };
307 /*******************************************************************************
308 * Code for BOARD_BootClockRUN configuration
309 ******************************************************************************/
BOARD_BootClockRUN(void)310 void BOARD_BootClockRUN(void)
311 {
312 scg_sys_clk_config_t curConfig;
313
314 /* Init SOSC according to board configuration. */
315 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockRUN);
316 /* Set the XTAL0 frequency based on board settings. */
317 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockRUN.freq);
318 /* Init FIRC. */
319 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockRUN);
320 /* Init SIRC. */
321 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockRUN);
322 /* Init SysPll. */
323 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockRUN);
324 /* Set SCG to SPLL mode. */
325 CLOCK_SetRunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockRUN);
326 /* Wait for clock source switch finished. */
327 do
328 {
329 CLOCK_GetCurSysClkConfig(&curConfig);
330 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockRUN.src);
331 /* Set SystemCoreClock variable. */
332 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
333 }
334
335 /*******************************************************************************
336 ********************* Configuration BOARD_BootClockHSRUN **********************
337 ******************************************************************************/
338 /* clang-format off */
339 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
340 !!Configuration
341 name: BOARD_BootClockHSRUN
342 outputs:
343 - {id: Bus_clock.outFreq, value: 84 MHz}
344 - {id: Core_clock.outFreq, value: 168 MHz}
345 - {id: FIRCDIV1_CLK.outFreq, value: 48 MHz}
346 - {id: FIRCDIV2_CLK.outFreq, value: 48 MHz}
347 - {id: Flash_clock.outFreq, value: 24 MHz}
348 - {id: LPO1KCLK.outFreq, value: 1 kHz}
349 - {id: LPO_clock.outFreq, value: 128 kHz}
350 - {id: PLLDIV1_CLK.outFreq, value: 168 MHz}
351 - {id: PLLDIV2_CLK.outFreq, value: 84 MHz}
352 - {id: SIRCDIV1_CLK.outFreq, value: 8 MHz}
353 - {id: SIRCDIV2_CLK.outFreq, value: 4 MHz}
354 - {id: SIRC_CLK.outFreq, value: 8 MHz}
355 - {id: SOSCDIV1_CLK.outFreq, value: 8 MHz}
356 - {id: SOSCDIV2_CLK.outFreq, value: 8 MHz}
357 - {id: SOSC_CLK.outFreq, value: 8 MHz}
358 - {id: System_clock.outFreq, value: 168 MHz}
359 settings:
360 - {id: SCGMode, value: SPLL}
361 - {id: powerMode, value: HSRUN}
362 - {id: SCG.DIVBUS.scale, value: '2'}
363 - {id: SCG.DIVSLOW.scale, value: '7'}
364 - {id: SCG.FIRCDIV1.scale, value: '1'}
365 - {id: SCG.FIRCDIV2.scale, value: '1'}
366 - {id: SCG.PREDIV.scale, value: '6'}
367 - {id: SCG.SCSSEL.sel, value: SCG.SPLL_DIV2_CLK}
368 - {id: SCG.SIRCDIV1.scale, value: '1'}
369 - {id: SCG.SIRCDIV2.scale, value: '2'}
370 - {id: SCG.SOSCDIV1.scale, value: '1'}
371 - {id: SCG.SOSCDIV2.scale, value: '1'}
372 - {id: SCG.SPLLDIV1.scale, value: '1'}
373 - {id: SCG.SPLLDIV2.scale, value: '2'}
374 - {id: SCG.SPLLSRCSEL.sel, value: SCG.FIRC}
375 - {id: SCG.SPLL_mul.scale, value: '42'}
376 - {id: SCG_SIRCCSR_SIRCLPEN_CFG, value: Disabled}
377 - {id: SCG_SOSCCFG_OSC_MODE_CFG, value: ModeOscLowPower}
378 - {id: SCG_SOSCCFG_RANGE_CFG, value: Medium}
379 - {id: SCG_SOSCCSR_SOSCEN_CFG, value: Enabled}
380 - {id: SCG_SOSCCSR_SOSCLPEN_CFG, value: Enabled}
381 - {id: SCG_SPLLCSR_SPLLEN_CFG, value: Enabled}
382 sources:
383 - {id: SCG.SOSC.outFreq, value: 8 MHz, enabled: true}
384 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
385 /* clang-format on */
386
387 /*******************************************************************************
388 * Variables for BOARD_BootClockHSRUN configuration
389 ******************************************************************************/
390 const scg_sys_clk_config_t g_sysClkConfig_BOARD_BootClockHSRUN = {
391 .divSlow = kSCG_SysClkDivBy7, /* Slow Clock Divider: divided by 7 */
392 .divBus = kSCG_SysClkDivBy2, /* Bus Clock Divider: divided by 2 */
393 .divCore = kSCG_SysClkDivBy1, /* Core Clock Divider: divided by 1 */
394 .src = kSCG_SysClkSrcSysPll, /* System PLL is selected as System Clock Source */
395 };
396 const scg_sosc_config_t g_scgSysOscConfig_BOARD_BootClockHSRUN = {
397 .freq = 8000000U, /* System Oscillator frequency: 8000000Hz */
398 .enableMode = kSCG_SysOscEnable |
399 kSCG_SysOscEnableInLowPower, /* Enable System OSC clock, Enable System OSC in low power mode */
400 .monitorMode = kSCG_SysOscMonitorDisable, /* Monitor disabled */
401 .div1 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 1: divided by 1 */
402 .div2 = kSCG_AsyncClkDivBy1, /* System OSC Clock Divider 2: divided by 1 */
403 .workMode = kSCG_SysOscModeOscLowPower, /* Oscillator low power */
404 };
405 const scg_sirc_config_t g_scgSircConfig_BOARD_BootClockHSRUN = {
406 .enableMode = kSCG_SircEnable, /* Enable SIRC clock */
407 .div1 = kSCG_AsyncClkDivBy1, /* Slow IRC Clock Divider 1: divided by 1 */
408 .div2 = kSCG_AsyncClkDivBy2, /* Slow IRC Clock Divider 2: divided by 2 */
409 .range = kSCG_SircRangeHigh, /* Slow IRC high range clock (8 MHz) */
410 };
411 const scg_firc_config_t g_scgFircConfig_BOARD_BootClockHSRUN = {
412 .enableMode = kSCG_FircEnable, /* Enable FIRC clock */
413 .div1 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 1: divided by 1 */
414 .div2 = kSCG_AsyncClkDivBy1, /* Fast IRC Clock Divider 2: divided by 1 */
415 .range = kSCG_FircRange48M, /* Fast IRC is trimmed to 48MHz */
416 .trimConfig = NULL, /* Fast IRC Trim disabled */
417 };
418 const scg_spll_config_t g_scgSysPllConfig_BOARD_BootClockHSRUN = {
419 .enableMode = kSCG_SysPllEnable, /* Enable SPLL clock */
420 .monitorMode = kSCG_SysPllMonitorDisable, /* Monitor disabled */
421 .div1 = kSCG_AsyncClkDivBy1, /* System PLL Clock Divider 1: divided by 1 */
422 .div2 = kSCG_AsyncClkDivBy2, /* System PLL Clock Divider 2: divided by 2 */
423 .src = kSCG_SysPllSrcFirc, /* System PLL clock source is Fast IRC */
424 .prediv = 5, /* Divided by 6 */
425 .mult = 26, /* Multiply Factor is 42 */
426 };
427 /*******************************************************************************
428 * Code for BOARD_BootClockHSRUN configuration
429 ******************************************************************************/
BOARD_BootClockHSRUN(void)430 void BOARD_BootClockHSRUN(void)
431 {
432 scg_sys_clk_config_t curConfig;
433
434 /* Init SOSC according to board configuration. */
435 CLOCK_InitSysOsc(&g_scgSysOscConfig_BOARD_BootClockHSRUN);
436 /* Set the XTAL0 frequency based on board settings. */
437 CLOCK_SetXtal0Freq(g_scgSysOscConfig_BOARD_BootClockHSRUN.freq);
438 /* Init FIRC. */
439 CLOCK_CONFIG_FircSafeConfig(&g_scgFircConfig_BOARD_BootClockHSRUN);
440 /* Set HSRUN power mode. */
441 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
442 SMC_SetPowerModeHsrun(SMC);
443 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateHsrun)
444 {
445 }
446
447 /* Init SIRC. */
448 CLOCK_InitSirc(&g_scgSircConfig_BOARD_BootClockHSRUN);
449 /* Init SysPll. */
450 CLOCK_InitSysPll(&g_scgSysPllConfig_BOARD_BootClockHSRUN);
451 /* Set SCG to SPLL mode. */
452 CLOCK_SetHsrunModeSysClkConfig(&g_sysClkConfig_BOARD_BootClockHSRUN);
453 /* Wait for clock source switch finished. */
454 do
455 {
456 CLOCK_GetCurSysClkConfig(&curConfig);
457 } while (curConfig.src != g_sysClkConfig_BOARD_BootClockHSRUN.src);
458 /* Set SystemCoreClock variable. */
459 SystemCoreClock = BOARD_BOOTCLOCKHSRUN_CORE_CLOCK;
460 }
461
