1 /*
2 * Copyright 2022 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /*
9 * How to setup clock using clock driver functions:
10 *
11 * 1. Call CLOCK_InitXXXPLL() to configure corresponding PLL clock.
12 *
13 * 2. Call CLOCK_InitXXXpfd() to configure corresponding PLL pfd clock.
14 *
15 * 3. Call CLOCK_SetMux() to configure corresponding clock source for target clock out.
16 *
17 * 4. Call CLOCK_SetDiv() to configure corresponding clock divider for target clock out.
18 *
19 * 5. Call CLOCK_SetXtalFreq() to set XTAL frequency based on board settings.
20 *
21 */
22
23 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
24 !!GlobalInfo
25 product: Clocks v10.0
26 processor: MIMXRT1021xxxxx
27 package_id: MIMXRT1021DAG5A
28 mcu_data: ksdk2_0
29 processor_version: 0.12.10
30 board: MIMXRT1020-EVK
31 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
32
33 #include "clock_config.h"
34 #include "fsl_iomuxc.h"
35
36 /*******************************************************************************
37 * Definitions
38 ******************************************************************************/
39
40 /*******************************************************************************
41 * Variables
42 ******************************************************************************/
43
44 /*******************************************************************************
45 ************************ BOARD_InitBootClocks function ************************
46 ******************************************************************************/
BOARD_InitBootClocks(void)47 void BOARD_InitBootClocks(void)
48 {
49 BOARD_BootClockRUN();
50 }
51
52 /*******************************************************************************
53 ********************** Configuration BOARD_BootClockRUN ***********************
54 ******************************************************************************/
55 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
56 !!Configuration
57 name: BOARD_BootClockRUN
58 called_from_default_init: true
59 outputs:
60 - {id: AHB_CLK_ROOT.outFreq, value: 500 MHz}
61 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
62 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
63 - {id: CLK_1M.outFreq, value: 1 MHz}
64 - {id: CLK_24M.outFreq, value: 24 MHz}
65 - {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
66 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
67 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
68 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
69 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 62.5 MHz}
70 - {id: IPG_CLK_ROOT.outFreq, value: 125 MHz}
71 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
72 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
73 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
74 - {id: PERCLK_CLK_ROOT.outFreq, value: 62.5 MHz}
75 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
76 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
77 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
78 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
79 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
80 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
81 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
82 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
83 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
84 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
85 - {id: SEMC_CLK_ROOT.outFreq, value: 62.5 MHz}
86 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
87 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
88 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
89 - {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
90 - {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
91 settings:
92 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
93 - {id: CCM.ARM_PODF.scale, value: '1', locked: true}
94 - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
95 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
96 - {id: CCM.IPG_PODF.scale, value: '4'}
97 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
98 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
99 - {id: CCM.PRE_PERIPH_CLK_SEL.sel, value: CCM.ARM_PODF}
100 - {id: CCM.SEMC_PODF.scale, value: '8'}
101 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
102 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
103 - {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
104 - {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
105 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
106 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
107 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
108 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
109 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
110 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
111 - {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
112 - {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
113 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
114 - {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '18', locked: true}
115 - {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
116 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
117 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
118 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
119 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
120 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
121 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
122 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
123 - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
124 - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
125 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
126 - {id: CCM_ANALOG.PLL4.div, value: '47'}
127 - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
128 - {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
129 - {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
130 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
131 sources:
132 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
133 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
134
135 /*******************************************************************************
136 * Variables for BOARD_BootClockRUN configuration
137 ******************************************************************************/
138 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN =
139 {
140 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
141 .numerator = 0, /* 30 bit numerator of fractional loop divider */
142 .denominator = 1, /* 30 bit denominator of fractional loop divider */
143 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
144 };
145 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN =
146 {
147 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
148 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
149 };
150 const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN =
151 {
152 .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
153 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
154 .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
155 .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
156 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
157 };
158 /*******************************************************************************
159 * Code for BOARD_BootClockRUN configuration
160 ******************************************************************************/
BOARD_BootClockRUN(void)161 void BOARD_BootClockRUN(void)
162 {
163 /* Init RTC OSC clock frequency. */
164 CLOCK_SetRtcXtalFreq(32768U);
165 /* Enable 1MHz clock output. */
166 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
167 /* Use free 1MHz clock output. */
168 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
169 /* Set XTAL 24MHz clock frequency. */
170 CLOCK_SetXtalFreq(24000000U);
171 /* Enable XTAL 24MHz clock source. */
172 CLOCK_InitExternalClk(0);
173 /* Enable internal RC. */
174 CLOCK_InitRcOsc24M();
175 /* Switch clock source to external OSC. */
176 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
177 /* Set Oscillator ready counter value. */
178 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
179 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
180 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
181 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
182 /* Setting the VDD_SOC to 1.25V. It is necessary to config AHB to 500Mhz. */
183 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
184 /* Waiting for DCDC_STS_DC_OK bit is asserted */
185 while (DCDC_REG0_STS_DC_OK_MASK != (DCDC_REG0_STS_DC_OK_MASK & DCDC->REG0))
186 {
187 }
188 /* Set AHB_PODF. */
189 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
190 /* Disable IPG clock gate. */
191 CLOCK_DisableClock(kCLOCK_Adc1);
192 CLOCK_DisableClock(kCLOCK_Adc2);
193 CLOCK_DisableClock(kCLOCK_Xbar1);
194 CLOCK_DisableClock(kCLOCK_Xbar2);
195 /* Set IPG_PODF. */
196 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
197 /* Set ARM_PODF. */
198 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
199 /* Set PERIPH_CLK2_PODF. */
200 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
201 /* Disable PERCLK clock gate. */
202 CLOCK_DisableClock(kCLOCK_Gpt1);
203 CLOCK_DisableClock(kCLOCK_Gpt1S);
204 CLOCK_DisableClock(kCLOCK_Gpt2);
205 CLOCK_DisableClock(kCLOCK_Gpt2S);
206 CLOCK_DisableClock(kCLOCK_Pit);
207 /* Set PERCLK_PODF. */
208 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
209 /* Disable USDHC1 clock gate. */
210 CLOCK_DisableClock(kCLOCK_Usdhc1);
211 /* Set USDHC1_PODF. */
212 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
213 /* Set Usdhc1 clock source. */
214 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
215 /* Disable USDHC2 clock gate. */
216 CLOCK_DisableClock(kCLOCK_Usdhc2);
217 /* Set USDHC2_PODF. */
218 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
219 /* Set Usdhc2 clock source. */
220 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
221 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
222 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
223 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
224 #ifndef SKIP_SYSCLK_INIT
225 /* Disable Semc clock gate. */
226 CLOCK_DisableClock(kCLOCK_Semc);
227 /* Set SEMC_PODF. */
228 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
229 /* Set Semc alt clock source. */
230 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
231 /* Set Semc clock source. */
232 CLOCK_SetMux(kCLOCK_SemcMux, 0);
233 #endif
234 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
235 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
236 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
237 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
238 /* Disable Flexspi clock gate. */
239 CLOCK_DisableClock(kCLOCK_FlexSpi);
240 /* Set FLEXSPI_PODF. */
241 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
242 /* Set Flexspi clock source. */
243 CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
244 #endif
245 /* Disable LPSPI clock gate. */
246 CLOCK_DisableClock(kCLOCK_Lpspi1);
247 CLOCK_DisableClock(kCLOCK_Lpspi2);
248 CLOCK_DisableClock(kCLOCK_Lpspi3);
249 CLOCK_DisableClock(kCLOCK_Lpspi4);
250 /* Set LPSPI_PODF. */
251 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
252 /* Set Lpspi clock source. */
253 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
254 /* Disable TRACE clock gate. */
255 CLOCK_DisableClock(kCLOCK_Trace);
256 /* Set TRACE_PODF. */
257 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
258 /* Set Trace clock source. */
259 CLOCK_SetMux(kCLOCK_TraceMux, 0);
260 /* Disable SAI1 clock gate. */
261 CLOCK_DisableClock(kCLOCK_Sai1);
262 /* Set SAI1_CLK_PRED. */
263 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
264 /* Set SAI1_CLK_PODF. */
265 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
266 /* Set Sai1 clock source. */
267 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
268 /* Disable SAI2 clock gate. */
269 CLOCK_DisableClock(kCLOCK_Sai2);
270 /* Set SAI2_CLK_PRED. */
271 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
272 /* Set SAI2_CLK_PODF. */
273 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
274 /* Set Sai2 clock source. */
275 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
276 /* Disable SAI3 clock gate. */
277 CLOCK_DisableClock(kCLOCK_Sai3);
278 /* Set SAI3_CLK_PRED. */
279 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
280 /* Set SAI3_CLK_PODF. */
281 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
282 /* Set Sai3 clock source. */
283 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
284 /* Disable Lpi2c clock gate. */
285 CLOCK_DisableClock(kCLOCK_Lpi2c1);
286 CLOCK_DisableClock(kCLOCK_Lpi2c2);
287 CLOCK_DisableClock(kCLOCK_Lpi2c3);
288 /* Set LPI2C_CLK_PODF. */
289 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
290 /* Set Lpi2c clock source. */
291 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
292 /* Disable CAN clock gate. */
293 CLOCK_DisableClock(kCLOCK_Can1);
294 CLOCK_DisableClock(kCLOCK_Can2);
295 CLOCK_DisableClock(kCLOCK_Can1S);
296 CLOCK_DisableClock(kCLOCK_Can2S);
297 /* Set CAN_CLK_PODF. */
298 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
299 /* Set Can clock source. */
300 CLOCK_SetMux(kCLOCK_CanMux, 2);
301 /* Disable UART clock gate. */
302 CLOCK_DisableClock(kCLOCK_Lpuart1);
303 CLOCK_DisableClock(kCLOCK_Lpuart2);
304 CLOCK_DisableClock(kCLOCK_Lpuart3);
305 CLOCK_DisableClock(kCLOCK_Lpuart4);
306 CLOCK_DisableClock(kCLOCK_Lpuart5);
307 CLOCK_DisableClock(kCLOCK_Lpuart6);
308 CLOCK_DisableClock(kCLOCK_Lpuart7);
309 CLOCK_DisableClock(kCLOCK_Lpuart8);
310 /* Set UART_CLK_PODF. */
311 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
312 /* Set Uart clock source. */
313 CLOCK_SetMux(kCLOCK_UartMux, 0);
314 /* Disable SPDIF clock gate. */
315 CLOCK_DisableClock(kCLOCK_Spdif);
316 /* Set SPDIF0_CLK_PRED. */
317 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
318 /* Set SPDIF0_CLK_PODF. */
319 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
320 /* Set Spdif clock source. */
321 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
322 /* Disable Flexio1 clock gate. */
323 CLOCK_DisableClock(kCLOCK_Flexio1);
324 /* Set FLEXIO1_CLK_PRED. */
325 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
326 /* Set FLEXIO1_CLK_PODF. */
327 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
328 /* Set Flexio1 clock source. */
329 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
330 /* Set Pll3 sw clock source. */
331 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
332 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
333 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
334 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
335 #ifndef SKIP_SYSCLK_INIT
336 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
337 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
338 #endif
339 /* Init System PLL. */
340 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN);
341 /* Init System pfd0. */
342 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
343 /* Init System pfd1. */
344 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
345 /* Init System pfd2. */
346 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
347 /* Init System pfd3. */
348 CLOCK_InitSysPfd(kCLOCK_Pfd3, 18);
349 #endif
350 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
351 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
352 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
353 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
354 /* Init Usb1 PLL. */
355 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN);
356 /* Init Usb1 pfd0. */
357 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
358 /* Init Usb1 pfd1. */
359 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
360 /* Init Usb1 pfd2. */
361 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
362 /* Init Usb1 pfd3. */
363 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
364 /* Disable Usb1 PLL output for USBPHY1. */
365 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
366 #endif
367 /* DeInit Audio PLL. */
368 CLOCK_DeinitAudioPll();
369 /* Bypass Audio PLL. */
370 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
371 /* Set divider for Audio PLL. */
372 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
373 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
374 /* Enable Audio PLL output. */
375 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
376 /* Init Enet PLL. */
377 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN);
378 /* Set preperiph clock source. */
379 CLOCK_SetMux(kCLOCK_PrePeriphMux, 3);
380 /* Set periph clock source. */
381 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
382 /* Set periph clock2 clock source. */
383 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
384 /* Set per clock source. */
385 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
386 /* Set clock out1 divider. */
387 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
388 /* Set clock out1 source. */
389 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
390 /* Set clock out2 divider. */
391 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
392 /* Set clock out2 source. */
393 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
394 /* Set clock out1 drives clock out1. */
395 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
396 /* Disable clock out1. */
397 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
398 /* Disable clock out2. */
399 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
400 /* Set SAI1 MCLK1 clock source. */
401 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
402 /* Set SAI1 MCLK2 clock source. */
403 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
404 /* Set SAI1 MCLK3 clock source. */
405 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
406 /* Set SAI2 MCLK3 clock source. */
407 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
408 /* Set SAI3 MCLK3 clock source. */
409 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
410 /* Set MQS configuration. */
411 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
412 /* Set ENET Ref clock source. */
413 #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
414 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
415 #elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
416 /* Backward compatibility for original bitfield name */
417 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
418 #else
419 #error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
420 #endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
421 /* Set GPT1 High frequency reference clock source. */
422 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
423 /* Set GPT2 High frequency reference clock source. */
424 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
425 /* Set SystemCoreClock variable. */
426 SystemCoreClock = BOARD_BOOTCLOCKRUN_CORE_CLOCK;
427 }
428
429 /*******************************************************************************
430 ******************* Configuration BOARD_BootClockRUN_400M *********************
431 ******************************************************************************/
432 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
433 !!Configuration
434 name: BOARD_BootClockRUN_400M
435 outputs:
436 - {id: AHB_CLK_ROOT.outFreq, value: 396 MHz}
437 - {id: CAN_CLK_ROOT.outFreq, value: 40 MHz}
438 - {id: CKIL_SYNC_CLK_ROOT.outFreq, value: 32.768 kHz}
439 - {id: CLK_1M.outFreq, value: 1 MHz}
440 - {id: CLK_24M.outFreq, value: 24 MHz}
441 - {id: ENET_500M_REF_CLK.outFreq, value: 500 MHz}
442 - {id: FLEXIO1_CLK_ROOT.outFreq, value: 30 MHz}
443 - {id: FLEXSPI_CLK_ROOT.outFreq, value: 132 MHz}
444 - {id: GPT1_ipg_clk_highfreq.outFreq, value: 49.5 MHz}
445 - {id: GPT2_ipg_clk_highfreq.outFreq, value: 49.5 MHz}
446 - {id: IPG_CLK_ROOT.outFreq, value: 99 MHz}
447 - {id: LPI2C_CLK_ROOT.outFreq, value: 60 MHz}
448 - {id: LPSPI_CLK_ROOT.outFreq, value: 105.6 MHz}
449 - {id: MQS_MCLK.outFreq, value: 1080/17 MHz}
450 - {id: PERCLK_CLK_ROOT.outFreq, value: 49.5 MHz}
451 - {id: SAI1_CLK_ROOT.outFreq, value: 1080/17 MHz}
452 - {id: SAI1_MCLK1.outFreq, value: 1080/17 MHz}
453 - {id: SAI1_MCLK2.outFreq, value: 1080/17 MHz}
454 - {id: SAI1_MCLK3.outFreq, value: 30 MHz}
455 - {id: SAI2_CLK_ROOT.outFreq, value: 1080/17 MHz}
456 - {id: SAI2_MCLK1.outFreq, value: 1080/17 MHz}
457 - {id: SAI2_MCLK3.outFreq, value: 30 MHz}
458 - {id: SAI3_CLK_ROOT.outFreq, value: 1080/17 MHz}
459 - {id: SAI3_MCLK1.outFreq, value: 1080/17 MHz}
460 - {id: SAI3_MCLK3.outFreq, value: 30 MHz}
461 - {id: SEMC_CLK_ROOT.outFreq, value: 49.5 MHz}
462 - {id: SPDIF0_CLK_ROOT.outFreq, value: 30 MHz}
463 - {id: TRACE_CLK_ROOT.outFreq, value: 132 MHz}
464 - {id: UART_CLK_ROOT.outFreq, value: 80 MHz}
465 - {id: USDHC1_CLK_ROOT.outFreq, value: 176 MHz}
466 - {id: USDHC2_CLK_ROOT.outFreq, value: 176 MHz}
467 settings:
468 - {id: CCM.AHB_PODF.scale, value: '1', locked: true}
469 - {id: CCM.ARM_PODF.scale, value: '1', locked: true}
470 - {id: CCM.FLEXSPI_PODF.scale, value: '4', locked: true}
471 - {id: CCM.FLEXSPI_SEL.sel, value: CCM_ANALOG.PLL2_PFD2_CLK}
472 - {id: CCM.IPG_PODF.scale, value: '4'}
473 - {id: CCM.LPSPI_PODF.scale, value: '5', locked: true}
474 - {id: CCM.PERCLK_PODF.scale, value: '2', locked: true}
475 - {id: CCM.SEMC_PODF.scale, value: '8'}
476 - {id: CCM.TRACE_CLK_SEL.sel, value: CCM_ANALOG.PLL2_MAIN_CLK}
477 - {id: CCM.TRACE_PODF.scale, value: '4', locked: true}
478 - {id: CCM.USDHC1_PODF.scale, value: '3', locked: true}
479 - {id: CCM.USDHC2_PODF.scale, value: '3', locked: true}
480 - {id: CCM_ANALOG.PLL2.denom, value: '1', locked: true}
481 - {id: CCM_ANALOG.PLL2.num, value: '0', locked: true}
482 - {id: CCM_ANALOG.PLL2_BYPASS.sel, value: CCM_ANALOG.PLL2_OUT_CLK}
483 - {id: CCM_ANALOG.PLL2_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD0}
484 - {id: CCM_ANALOG.PLL2_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD1}
485 - {id: CCM_ANALOG.PLL2_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD2}
486 - {id: CCM_ANALOG.PLL2_PFD2_DIV.scale, value: '18', locked: true}
487 - {id: CCM_ANALOG.PLL2_PFD2_MUL.scale, value: '18', locked: true}
488 - {id: CCM_ANALOG.PLL2_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL2_PFD3}
489 - {id: CCM_ANALOG.PLL2_PFD3_DIV.scale, value: '24', locked: true}
490 - {id: CCM_ANALOG.PLL2_PFD3_MUL.scale, value: '18', locked: true}
491 - {id: CCM_ANALOG.PLL3_BYPASS.sel, value: CCM_ANALOG.PLL3}
492 - {id: CCM_ANALOG.PLL3_PFD0_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD0}
493 - {id: CCM_ANALOG.PLL3_PFD0_DIV.scale, value: '22', locked: true}
494 - {id: CCM_ANALOG.PLL3_PFD0_MUL.scale, value: '18', locked: true}
495 - {id: CCM_ANALOG.PLL3_PFD1_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD1}
496 - {id: CCM_ANALOG.PLL3_PFD2_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD2}
497 - {id: CCM_ANALOG.PLL3_PFD3_BYPASS.sel, value: CCM_ANALOG.PLL3_PFD3}
498 - {id: CCM_ANALOG.PLL3_PFD3_DIV.scale, value: '18', locked: true}
499 - {id: CCM_ANALOG.PLL3_PFD3_MUL.scale, value: '18', locked: true}
500 - {id: CCM_ANALOG.PLL4.denom, value: '50'}
501 - {id: CCM_ANALOG.PLL4.div, value: '47'}
502 - {id: CCM_ANALOG.PLL6_BYPASS.sel, value: CCM_ANALOG.PLL6}
503 - {id: CCM_ANALOG_PLL_ENET_ENABLE_CFG, value: Disabled}
504 - {id: CCM_ANALOG_PLL_ENET_ENET_25M_REF_EN_CFG, value: Disabled}
505 - {id: CCM_ANALOG_PLL_USB1_POWER_CFG, value: 'Yes'}
506 sources:
507 - {id: XTALOSC24M.RTC_OSC.outFreq, value: 32.768 kHz, enabled: true}
508 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
509
510 /*******************************************************************************
511 * Variables for BOARD_BootClockRUN_400M configuration
512 ******************************************************************************/
513 const clock_sys_pll_config_t sysPllConfig_BOARD_BootClockRUN_400M =
514 {
515 .loopDivider = 1, /* PLL loop divider, Fout = Fin * ( 20 + loopDivider*2 + numerator / denominator ) */
516 .numerator = 0, /* 30 bit numerator of fractional loop divider */
517 .denominator = 1, /* 30 bit denominator of fractional loop divider */
518 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
519 };
520 const clock_usb_pll_config_t usb1PllConfig_BOARD_BootClockRUN_400M =
521 {
522 .loopDivider = 0, /* PLL loop divider, Fout = Fin * 20 */
523 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
524 };
525 const clock_enet_pll_config_t enetPllConfig_BOARD_BootClockRUN_400M =
526 {
527 .enableClkOutput = false, /* Disable the PLL providing the ENET 125MHz reference clock */
528 .enableClkOutput500M = true, /* Enable the PLL providing the ENET 500MHz reference clock */
529 .enableClkOutput25M = false, /* Disable the PLL providing the ENET 25MHz reference clock */
530 .loopDivider = 1, /* Set frequency of ethernet reference clock to 50 MHz */
531 .src = 0, /* Bypass clock source, 0 - OSC 24M, 1 - CLK1_P and CLK1_N */
532 };
533 /*******************************************************************************
534 * Code for BOARD_BootClockRUN_400M configuration
535 ******************************************************************************/
BOARD_BootClockRUN_400M(void)536 void BOARD_BootClockRUN_400M(void)
537 {
538 /* Init RTC OSC clock frequency. */
539 CLOCK_SetRtcXtalFreq(32768U);
540 /* Enable 1MHz clock output. */
541 XTALOSC24M->OSC_CONFIG2 |= XTALOSC24M_OSC_CONFIG2_ENABLE_1M_MASK;
542 /* Use free 1MHz clock output. */
543 XTALOSC24M->OSC_CONFIG2 &= ~XTALOSC24M_OSC_CONFIG2_MUX_1M_MASK;
544 /* Set XTAL 24MHz clock frequency. */
545 CLOCK_SetXtalFreq(24000000U);
546 /* Enable XTAL 24MHz clock source. */
547 CLOCK_InitExternalClk(0);
548 /* Enable internal RC. */
549 CLOCK_InitRcOsc24M();
550 /* Switch clock source to external OSC. */
551 CLOCK_SwitchOsc(kCLOCK_XtalOsc);
552 /* Set Oscillator ready counter value. */
553 CCM->CCR = (CCM->CCR & (~CCM_CCR_OSCNT_MASK)) | CCM_CCR_OSCNT(127);
554 /* Setting PeriphClk2Mux and PeriphMux to provide stable clock before PLLs are initialed */
555 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 1); /* Set PERIPH_CLK2 MUX to OSC */
556 CLOCK_SetMux(kCLOCK_PeriphMux, 1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
557 /* Set AHB_PODF. */
558 CLOCK_SetDiv(kCLOCK_AhbDiv, 0);
559 /* Disable IPG clock gate. */
560 CLOCK_DisableClock(kCLOCK_Adc1);
561 CLOCK_DisableClock(kCLOCK_Adc2);
562 CLOCK_DisableClock(kCLOCK_Xbar1);
563 CLOCK_DisableClock(kCLOCK_Xbar2);
564 /* Set IPG_PODF. */
565 CLOCK_SetDiv(kCLOCK_IpgDiv, 3);
566 /* Set ARM_PODF. */
567 CLOCK_SetDiv(kCLOCK_ArmDiv, 0);
568 /* Set PERIPH_CLK2_PODF. */
569 CLOCK_SetDiv(kCLOCK_PeriphClk2Div, 0);
570 /* Disable PERCLK clock gate. */
571 CLOCK_DisableClock(kCLOCK_Gpt1);
572 CLOCK_DisableClock(kCLOCK_Gpt1S);
573 CLOCK_DisableClock(kCLOCK_Gpt2);
574 CLOCK_DisableClock(kCLOCK_Gpt2S);
575 CLOCK_DisableClock(kCLOCK_Pit);
576 /* Set PERCLK_PODF. */
577 CLOCK_SetDiv(kCLOCK_PerclkDiv, 1);
578 /* Disable USDHC1 clock gate. */
579 CLOCK_DisableClock(kCLOCK_Usdhc1);
580 /* Set USDHC1_PODF. */
581 CLOCK_SetDiv(kCLOCK_Usdhc1Div, 2);
582 /* Set Usdhc1 clock source. */
583 CLOCK_SetMux(kCLOCK_Usdhc1Mux, 0);
584 /* Disable USDHC2 clock gate. */
585 CLOCK_DisableClock(kCLOCK_Usdhc2);
586 /* Set USDHC2_PODF. */
587 CLOCK_SetDiv(kCLOCK_Usdhc2Div, 2);
588 /* Set Usdhc2 clock source. */
589 CLOCK_SetMux(kCLOCK_Usdhc2Mux, 0);
590 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
591 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
592 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
593 #ifndef SKIP_SYSCLK_INIT
594 /* Disable Semc clock gate. */
595 CLOCK_DisableClock(kCLOCK_Semc);
596 /* Set SEMC_PODF. */
597 CLOCK_SetDiv(kCLOCK_SemcDiv, 7);
598 /* Set Semc alt clock source. */
599 CLOCK_SetMux(kCLOCK_SemcAltMux, 0);
600 /* Set Semc clock source. */
601 CLOCK_SetMux(kCLOCK_SemcMux, 0);
602 #endif
603 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
604 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
605 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
606 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
607 /* Disable Flexspi clock gate. */
608 CLOCK_DisableClock(kCLOCK_FlexSpi);
609 /* Set FLEXSPI_PODF. */
610 CLOCK_SetDiv(kCLOCK_FlexspiDiv, 3);
611 /* Set Flexspi clock source. */
612 CLOCK_SetMux(kCLOCK_FlexspiMux, 2);
613 #endif
614 /* Disable LPSPI clock gate. */
615 CLOCK_DisableClock(kCLOCK_Lpspi1);
616 CLOCK_DisableClock(kCLOCK_Lpspi2);
617 CLOCK_DisableClock(kCLOCK_Lpspi3);
618 CLOCK_DisableClock(kCLOCK_Lpspi4);
619 /* Set LPSPI_PODF. */
620 CLOCK_SetDiv(kCLOCK_LpspiDiv, 4);
621 /* Set Lpspi clock source. */
622 CLOCK_SetMux(kCLOCK_LpspiMux, 2);
623 /* Disable TRACE clock gate. */
624 CLOCK_DisableClock(kCLOCK_Trace);
625 /* Set TRACE_PODF. */
626 CLOCK_SetDiv(kCLOCK_TraceDiv, 3);
627 /* Set Trace clock source. */
628 CLOCK_SetMux(kCLOCK_TraceMux, 0);
629 /* Disable SAI1 clock gate. */
630 CLOCK_DisableClock(kCLOCK_Sai1);
631 /* Set SAI1_CLK_PRED. */
632 CLOCK_SetDiv(kCLOCK_Sai1PreDiv, 3);
633 /* Set SAI1_CLK_PODF. */
634 CLOCK_SetDiv(kCLOCK_Sai1Div, 1);
635 /* Set Sai1 clock source. */
636 CLOCK_SetMux(kCLOCK_Sai1Mux, 0);
637 /* Disable SAI2 clock gate. */
638 CLOCK_DisableClock(kCLOCK_Sai2);
639 /* Set SAI2_CLK_PRED. */
640 CLOCK_SetDiv(kCLOCK_Sai2PreDiv, 3);
641 /* Set SAI2_CLK_PODF. */
642 CLOCK_SetDiv(kCLOCK_Sai2Div, 1);
643 /* Set Sai2 clock source. */
644 CLOCK_SetMux(kCLOCK_Sai2Mux, 0);
645 /* Disable SAI3 clock gate. */
646 CLOCK_DisableClock(kCLOCK_Sai3);
647 /* Set SAI3_CLK_PRED. */
648 CLOCK_SetDiv(kCLOCK_Sai3PreDiv, 3);
649 /* Set SAI3_CLK_PODF. */
650 CLOCK_SetDiv(kCLOCK_Sai3Div, 1);
651 /* Set Sai3 clock source. */
652 CLOCK_SetMux(kCLOCK_Sai3Mux, 0);
653 /* Disable Lpi2c clock gate. */
654 CLOCK_DisableClock(kCLOCK_Lpi2c1);
655 CLOCK_DisableClock(kCLOCK_Lpi2c2);
656 CLOCK_DisableClock(kCLOCK_Lpi2c3);
657 /* Set LPI2C_CLK_PODF. */
658 CLOCK_SetDiv(kCLOCK_Lpi2cDiv, 0);
659 /* Set Lpi2c clock source. */
660 CLOCK_SetMux(kCLOCK_Lpi2cMux, 0);
661 /* Disable CAN clock gate. */
662 CLOCK_DisableClock(kCLOCK_Can1);
663 CLOCK_DisableClock(kCLOCK_Can2);
664 CLOCK_DisableClock(kCLOCK_Can1S);
665 CLOCK_DisableClock(kCLOCK_Can2S);
666 /* Set CAN_CLK_PODF. */
667 CLOCK_SetDiv(kCLOCK_CanDiv, 1);
668 /* Set Can clock source. */
669 CLOCK_SetMux(kCLOCK_CanMux, 2);
670 /* Disable UART clock gate. */
671 CLOCK_DisableClock(kCLOCK_Lpuart1);
672 CLOCK_DisableClock(kCLOCK_Lpuart2);
673 CLOCK_DisableClock(kCLOCK_Lpuart3);
674 CLOCK_DisableClock(kCLOCK_Lpuart4);
675 CLOCK_DisableClock(kCLOCK_Lpuart5);
676 CLOCK_DisableClock(kCLOCK_Lpuart6);
677 CLOCK_DisableClock(kCLOCK_Lpuart7);
678 CLOCK_DisableClock(kCLOCK_Lpuart8);
679 /* Set UART_CLK_PODF. */
680 CLOCK_SetDiv(kCLOCK_UartDiv, 0);
681 /* Set Uart clock source. */
682 CLOCK_SetMux(kCLOCK_UartMux, 0);
683 /* Disable SPDIF clock gate. */
684 CLOCK_DisableClock(kCLOCK_Spdif);
685 /* Set SPDIF0_CLK_PRED. */
686 CLOCK_SetDiv(kCLOCK_Spdif0PreDiv, 1);
687 /* Set SPDIF0_CLK_PODF. */
688 CLOCK_SetDiv(kCLOCK_Spdif0Div, 7);
689 /* Set Spdif clock source. */
690 CLOCK_SetMux(kCLOCK_SpdifMux, 3);
691 /* Disable Flexio1 clock gate. */
692 CLOCK_DisableClock(kCLOCK_Flexio1);
693 /* Set FLEXIO1_CLK_PRED. */
694 CLOCK_SetDiv(kCLOCK_Flexio1PreDiv, 1);
695 /* Set FLEXIO1_CLK_PODF. */
696 CLOCK_SetDiv(kCLOCK_Flexio1Div, 7);
697 /* Set Flexio1 clock source. */
698 CLOCK_SetMux(kCLOCK_Flexio1Mux, 3);
699 /* Set Pll3 sw clock source. */
700 CLOCK_SetMux(kCLOCK_Pll3SwMux, 0);
701 /* In SDK projects, SDRAM (configured by SEMC) will be initialized in either debug script or dcd.
702 * With this macro SKIP_SYSCLK_INIT, system pll (selected to be SEMC source clock in SDK projects) will be left unchanged.
703 * Note: If another clock source is selected for SEMC, user may want to avoid changing that clock as well.*/
704 #ifndef SKIP_SYSCLK_INIT
705 #if defined(XIP_BOOT_HEADER_DCD_ENABLE) && (XIP_BOOT_HEADER_DCD_ENABLE == 1)
706 #warning "SKIP_SYSCLK_INIT should be defined to keep system pll (selected to be SEMC source clock in SDK projects) unchanged."
707 #endif
708 /* Init System PLL. */
709 CLOCK_InitSysPll(&sysPllConfig_BOARD_BootClockRUN_400M);
710 /* Init System pfd0. */
711 CLOCK_InitSysPfd(kCLOCK_Pfd0, 27);
712 /* Init System pfd1. */
713 CLOCK_InitSysPfd(kCLOCK_Pfd1, 16);
714 /* Init System pfd2. */
715 CLOCK_InitSysPfd(kCLOCK_Pfd2, 18);
716 /* Init System pfd3. */
717 CLOCK_InitSysPfd(kCLOCK_Pfd3, 24);
718 #endif
719 /* In SDK projects, external flash (configured by FLEXSPI) will be initialized by dcd.
720 * With this macro XIP_EXTERNAL_FLASH, usb1 pll (selected to be FLEXSPI clock source in SDK projects) will be left unchanged.
721 * Note: If another clock source is selected for FLEXSPI, user may want to avoid changing that clock as well.*/
722 #if !(defined(XIP_EXTERNAL_FLASH) && (XIP_EXTERNAL_FLASH == 1))
723 /* Init Usb1 PLL. */
724 CLOCK_InitUsb1Pll(&usb1PllConfig_BOARD_BootClockRUN_400M);
725 /* Init Usb1 pfd0. */
726 CLOCK_InitUsb1Pfd(kCLOCK_Pfd0, 22);
727 /* Init Usb1 pfd1. */
728 CLOCK_InitUsb1Pfd(kCLOCK_Pfd1, 16);
729 /* Init Usb1 pfd2. */
730 CLOCK_InitUsb1Pfd(kCLOCK_Pfd2, 17);
731 /* Init Usb1 pfd3. */
732 CLOCK_InitUsb1Pfd(kCLOCK_Pfd3, 18);
733 /* Disable Usb1 PLL output for USBPHY1. */
734 CCM_ANALOG->PLL_USB1 &= ~CCM_ANALOG_PLL_USB1_EN_USB_CLKS_MASK;
735 #endif
736 /* DeInit Audio PLL. */
737 CLOCK_DeinitAudioPll();
738 /* Bypass Audio PLL. */
739 CLOCK_SetPllBypass(CCM_ANALOG, kCLOCK_PllAudio, 1);
740 /* Set divider for Audio PLL. */
741 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_LSB_MASK;
742 CCM_ANALOG->MISC2 &= ~CCM_ANALOG_MISC2_AUDIO_DIV_MSB_MASK;
743 /* Enable Audio PLL output. */
744 CCM_ANALOG->PLL_AUDIO |= CCM_ANALOG_PLL_AUDIO_ENABLE_MASK;
745 /* Init Enet PLL. */
746 CLOCK_InitEnetPll(&enetPllConfig_BOARD_BootClockRUN_400M);
747 /* Set preperiph clock source. */
748 CLOCK_SetMux(kCLOCK_PrePeriphMux, 2);
749 /* Set periph clock source. */
750 CLOCK_SetMux(kCLOCK_PeriphMux, 0);
751 /* Set periph clock2 clock source. */
752 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0);
753 /* Set per clock source. */
754 CLOCK_SetMux(kCLOCK_PerclkMux, 0);
755 /* Set clock out1 divider. */
756 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_DIV_MASK)) | CCM_CCOSR_CLKO1_DIV(0);
757 /* Set clock out1 source. */
758 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO1_SEL_MASK)) | CCM_CCOSR_CLKO1_SEL(1);
759 /* Set clock out2 divider. */
760 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_DIV_MASK)) | CCM_CCOSR_CLKO2_DIV(0);
761 /* Set clock out2 source. */
762 CCM->CCOSR = (CCM->CCOSR & (~CCM_CCOSR_CLKO2_SEL_MASK)) | CCM_CCOSR_CLKO2_SEL(3);
763 /* Set clock out1 drives clock out1. */
764 CCM->CCOSR &= ~CCM_CCOSR_CLK_OUT_SEL_MASK;
765 /* Disable clock out1. */
766 CCM->CCOSR &= ~CCM_CCOSR_CLKO1_EN_MASK;
767 /* Disable clock out2. */
768 CCM->CCOSR &= ~CCM_CCOSR_CLKO2_EN_MASK;
769 /* Set SAI1 MCLK1 clock source. */
770 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk1Sel, 0);
771 /* Set SAI1 MCLK2 clock source. */
772 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk2Sel, 0);
773 /* Set SAI1 MCLK3 clock source. */
774 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI1MClk3Sel, 0);
775 /* Set SAI2 MCLK3 clock source. */
776 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI2MClk3Sel, 0);
777 /* Set SAI3 MCLK3 clock source. */
778 IOMUXC_SetSaiMClkClockSource(IOMUXC_GPR, kIOMUXC_GPR_SAI3MClk3Sel, 0);
779 /* Set MQS configuration. */
780 IOMUXC_MQSConfig(IOMUXC_GPR,kIOMUXC_MqsPwmOverSampleRate32, 0);
781 /* Set ENET Ref clock source. */
782 #if defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK)
783 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK;
784 #elif defined(IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK)
785 /* Backward compatibility for original bitfield name */
786 IOMUXC_GPR->GPR1 &= ~IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK;
787 #else
788 #error "Neither IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK nor IOMUXC_GPR_GPR1_ENET1_TX_CLK_DIR_MASK is defined."
789 #endif /* defined(IOMUXC_GPR_GPR1_ENET_REF_CLK_DIR_MASK) */
790 /* Set GPT1 High frequency reference clock source. */
791 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT1_MASK;
792 /* Set GPT2 High frequency reference clock source. */
793 IOMUXC_GPR->GPR5 &= ~IOMUXC_GPR_GPR5_VREF_1M_CLK_GPT2_MASK;
794 /* Set SystemCoreClock variable. */
795 SystemCoreClock = BOARD_BOOTCLOCKRUN_400M_CORE_CLOCK;
796 }
797
798
