1 /* 2 * Copyright (c) 2013-2020 ARM Limited. All rights reserved. 3 * 4 * SPDX-License-Identifier: Apache-2.0 5 * 6 * Licensed under the Apache License, Version 2.0 (the License); you may 7 * not use this file except in compliance with the License. 8 * You may obtain a copy of the License at 9 * 10 * www.apache.org/licenses/LICENSE-2.0 11 * 12 * Unless required by applicable law or agreed to in writing, software 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. 15 * See the License for the specific language governing permissions and 16 * limitations under the License. 17 * 18 * $Date: 31. March 2020 19 * $Revision: V2.4 20 * 21 * Project: NAND Flash Driver definitions 22 */ 23 24 /* History: 25 * Version 2.4 26 * Removed volatile from ARM_NAND_STATUS 27 * Version 2.3 28 * Extended ARM_NAND_ECC_INFO structure 29 * Version 2.2 30 * ARM_NAND_STATUS made volatile 31 * Version 2.1 32 * Updated ARM_NAND_ECC_INFO structure and ARM_NAND_ECC_xxx definitions 33 * Version 2.0 34 * New simplified driver: 35 * complexity moved to upper layer (command agnostic) 36 * Added support for: 37 * NV-DDR & NV-DDR2 Interface (ONFI specification) 38 * VCC, VCCQ and VPP Power Supply Control 39 * WP (Write Protect) Control 40 * Version 1.11 41 * Changed prefix ARM_DRV -> ARM_DRIVER 42 * Version 1.10 43 * Namespace prefix ARM_ added 44 * Version 1.00 45 * Initial release 46 */ 47 48 #ifndef DRIVER_NAND_H_ 49 #define DRIVER_NAND_H_ 50 51 #ifdef __cplusplus 52 extern "C" 53 { 54 #endif 55 56 #include "Driver_Common.h" 57 58 #define ARM_NAND_API_VERSION ARM_DRIVER_VERSION_MAJOR_MINOR(2,4) /* API version */ 59 60 61 #define _ARM_Driver_NAND_(n) Driver_NAND##n 62 #define ARM_Driver_NAND_(n) _ARM_Driver_NAND_(n) 63 64 65 /****** NAND Device Power *****/ 66 #define ARM_NAND_POWER_VCC_Pos 0 67 #define ARM_NAND_POWER_VCC_Msk (0x07UL << ARM_NAND_POWER_VCC_Pos) 68 #define ARM_NAND_POWER_VCC_OFF (0x01UL << ARM_NAND_POWER_VCC_Pos) ///< VCC Power off 69 #define ARM_NAND_POWER_VCC_3V3 (0x02UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 3.3V 70 #define ARM_NAND_POWER_VCC_1V8 (0x03UL << ARM_NAND_POWER_VCC_Pos) ///< VCC = 1.8V 71 #define ARM_NAND_POWER_VCCQ_Pos 3 72 #define ARM_NAND_POWER_VCCQ_Msk (0x07UL << ARM_NAND_POWER_VCCQ_Pos) 73 #define ARM_NAND_POWER_VCCQ_OFF (0x01UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ I/O Power off 74 #define ARM_NAND_POWER_VCCQ_3V3 (0x02UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 3.3V 75 #define ARM_NAND_POWER_VCCQ_1V8 (0x03UL << ARM_NAND_POWER_VCCQ_Pos) ///< VCCQ = 1.8V 76 #define ARM_NAND_POWER_VPP_OFF (1UL << 6) ///< VPP off 77 #define ARM_NAND_POWER_VPP_ON (1UL << 7) ///< VPP on 78 79 80 /****** NAND Control Codes *****/ 81 #define ARM_NAND_BUS_MODE (0x01UL) ///< Set Bus Mode as specified with arg 82 #define ARM_NAND_BUS_DATA_WIDTH (0x02UL) ///< Set Bus Data Width as specified with arg 83 #define ARM_NAND_DRIVER_STRENGTH (0x03UL) ///< Set Driver Strength as specified with arg 84 #define ARM_NAND_DEVICE_READY_EVENT (0x04UL) ///< Generate \ref ARM_NAND_EVENT_DEVICE_READY; arg: 0=disabled (default), 1=enabled 85 #define ARM_NAND_DRIVER_READY_EVENT (0x05UL) ///< Generate \ref ARM_NAND_EVENT_DRIVER_READY; arg: 0=disabled (default), 1=enabled 86 87 /*----- NAND Bus Mode (ONFI - Open NAND Flash Interface) -----*/ 88 #define ARM_NAND_BUS_INTERFACE_Pos 4 89 #define ARM_NAND_BUS_INTERFACE_Msk (0x03UL << ARM_NAND_BUS_INTERFACE_Pos) 90 #define ARM_NAND_BUS_SDR (0x00UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: SDR (Single Data Rate) - Traditional interface (default) 91 #define ARM_NAND_BUS_DDR (0x01UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR (Double Data Rate) 92 #define ARM_NAND_BUS_DDR2 (0x02UL << ARM_NAND_BUS_INTERFACE_Pos) ///< Data Interface: NV-DDR2 (Double Data Rate) 93 #define ARM_NAND_BUS_TIMING_MODE_Pos 0 94 #define ARM_NAND_BUS_TIMING_MODE_Msk (0x0FUL << ARM_NAND_BUS_TIMING_MODE_Pos) 95 #define ARM_NAND_BUS_TIMING_MODE_0 (0x00UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 0 (default) 96 #define ARM_NAND_BUS_TIMING_MODE_1 (0x01UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 1 97 #define ARM_NAND_BUS_TIMING_MODE_2 (0x02UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 2 98 #define ARM_NAND_BUS_TIMING_MODE_3 (0x03UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 3 99 #define ARM_NAND_BUS_TIMING_MODE_4 (0x04UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 4 (SDR EDO capable) 100 #define ARM_NAND_BUS_TIMING_MODE_5 (0x05UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 5 (SDR EDO capable) 101 #define ARM_NAND_BUS_TIMING_MODE_6 (0x06UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 6 (NV-DDR2 only) 102 #define ARM_NAND_BUS_TIMING_MODE_7 (0x07UL << ARM_NAND_BUS_TIMING_MODE_Pos) ///< Timing Mode 7 (NV-DDR2 only) 103 #define ARM_NAND_BUS_DDR2_DO_WCYC_Pos 8 104 #define ARM_NAND_BUS_DDR2_DO_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) 105 #define ARM_NAND_BUS_DDR2_DO_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 0 (default) 106 #define ARM_NAND_BUS_DDR2_DO_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 1 107 #define ARM_NAND_BUS_DDR2_DO_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 2 108 #define ARM_NAND_BUS_DDR2_DO_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DO_WCYC_Pos) ///< DDR2 Data Output Warm-up cycles: 4 109 #define ARM_NAND_BUS_DDR2_DI_WCYC_Pos 12 110 #define ARM_NAND_BUS_DDR2_DI_WCYC_Msk (0x0FUL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) 111 #define ARM_NAND_BUS_DDR2_DI_WCYC_0 (0x00UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 0 (default) 112 #define ARM_NAND_BUS_DDR2_DI_WCYC_1 (0x01UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 1 113 #define ARM_NAND_BUS_DDR2_DI_WCYC_2 (0x02UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 2 114 #define ARM_NAND_BUS_DDR2_DI_WCYC_4 (0x03UL << ARM_NAND_BUS_DDR2_DI_WCYC_Pos) ///< DDR2 Data Input Warm-up cycles: 4 115 #define ARM_NAND_BUS_DDR2_VEN (1UL << 16) ///< DDR2 Enable external VREFQ as reference 116 #define ARM_NAND_BUS_DDR2_CMPD (1UL << 17) ///< DDR2 Enable complementary DQS (DQS_c) signal 117 #define ARM_NAND_BUS_DDR2_CMPR (1UL << 18) ///< DDR2 Enable complementary RE_n (RE_c) signal 118 119 /*----- NAND Data Bus Width -----*/ 120 #define ARM_NAND_BUS_DATA_WIDTH_8 (0x00UL) ///< Bus Data Width: 8 bit (default) 121 #define ARM_NAND_BUS_DATA_WIDTH_16 (0x01UL) ///< Bus Data Width: 16 bit 122 123 /*----- NAND Driver Strength (ONFI - Open NAND Flash Interface) -----*/ 124 #define ARM_NAND_DRIVER_STRENGTH_18 (0x00UL) ///< Driver Strength 2.0x = 18 Ohms 125 #define ARM_NAND_DRIVER_STRENGTH_25 (0x01UL) ///< Driver Strength 1.4x = 25 Ohms 126 #define ARM_NAND_DRIVER_STRENGTH_35 (0x02UL) ///< Driver Strength 1.0x = 35 Ohms (default) 127 #define ARM_NAND_DRIVER_STRENGTH_50 (0x03UL) ///< Driver Strength 0.7x = 50 Ohms 128 129 130 /****** NAND ECC for Read/Write Data Mode and Sequence Execution Code *****/ 131 #define ARM_NAND_ECC_INDEX_Pos 0 132 #define ARM_NAND_ECC_INDEX_Msk (0xFFUL << ARM_NAND_ECC_INDEX_Pos) 133 #define ARM_NAND_ECC(n) ((n) & ARM_NAND_ECC_INDEX_Msk) ///< Select ECC 134 #define ARM_NAND_ECC0 (1UL << 8) ///< Use ECC0 of selected ECC 135 #define ARM_NAND_ECC1 (1UL << 9) ///< Use ECC1 of selected ECC 136 137 /****** NAND Flag for Read/Write Data Mode and Sequence Execution Code *****/ 138 #define ARM_NAND_DRIVER_DONE_EVENT (1UL << 16) ///< Generate \ref ARM_NAND_EVENT_DRIVER_DONE 139 140 /****** NAND Sequence Execution Code *****/ 141 #define ARM_NAND_CODE_SEND_CMD1 (1UL << 17) ///< Send Command 1 142 #define ARM_NAND_CODE_SEND_ADDR_COL1 (1UL << 18) ///< Send Column Address 1 143 #define ARM_NAND_CODE_SEND_ADDR_COL2 (1UL << 19) ///< Send Column Address 2 144 #define ARM_NAND_CODE_SEND_ADDR_ROW1 (1UL << 20) ///< Send Row Address 1 145 #define ARM_NAND_CODE_SEND_ADDR_ROW2 (1UL << 21) ///< Send Row Address 2 146 #define ARM_NAND_CODE_SEND_ADDR_ROW3 (1UL << 22) ///< Send Row Address 3 147 #define ARM_NAND_CODE_INC_ADDR_ROW (1UL << 23) ///< Auto-increment Row Address 148 #define ARM_NAND_CODE_WRITE_DATA (1UL << 24) ///< Write Data 149 #define ARM_NAND_CODE_SEND_CMD2 (1UL << 25) ///< Send Command 2 150 #define ARM_NAND_CODE_WAIT_BUSY (1UL << 26) ///< Wait while R/Bn busy 151 #define ARM_NAND_CODE_READ_DATA (1UL << 27) ///< Read Data 152 #define ARM_NAND_CODE_SEND_CMD3 (1UL << 28) ///< Send Command 3 153 #define ARM_NAND_CODE_READ_STATUS (1UL << 29) ///< Read Status byte and check FAIL bit (bit 0) 154 155 /*----- NAND Sequence Execution Code: Command -----*/ 156 #define ARM_NAND_CODE_CMD1_Pos 0 157 #define ARM_NAND_CODE_CMD1_Msk (0xFFUL << ARM_NAND_CODE_CMD1_Pos) 158 #define ARM_NAND_CODE_CMD2_Pos 8 159 #define ARM_NAND_CODE_CMD2_Msk (0xFFUL << ARM_NAND_CODE_CMD2_Pos) 160 #define ARM_NAND_CODE_CMD3_Pos 16 161 #define ARM_NAND_CODE_CMD3_Msk (0xFFUL << ARM_NAND_CODE_CMD3_Pos) 162 163 /*----- NAND Sequence Execution Code: Column Address -----*/ 164 #define ARM_NAND_CODE_ADDR_COL1_Pos 0 165 #define ARM_NAND_CODE_ADDR_COL1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL1_Pos) 166 #define ARM_NAND_CODE_ADDR_COL2_Pos 8 167 #define ARM_NAND_CODE_ADDR_COL2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_COL2_Pos) 168 169 /*----- NAND Sequence Execution Code: Row Address -----*/ 170 #define ARM_NAND_CODE_ADDR_ROW1_Pos 0 171 #define ARM_NAND_CODE_ADDR_ROW1_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW1_Pos) 172 #define ARM_NAND_CODE_ADDR_ROW2_Pos 8 173 #define ARM_NAND_CODE_ADDR_ROW2_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW2_Pos) 174 #define ARM_NAND_CODE_ADDR_ROW3_Pos 16 175 #define ARM_NAND_CODE_ADDR_ROW3_Msk (0xFFUL << ARM_NAND_CODE_ADDR_ROW3_Pos) 176 177 178 /****** NAND specific error codes *****/ 179 #define ARM_NAND_ERROR_ECC (ARM_DRIVER_ERROR_SPECIFIC - 1) ///< ECC generation/correction failed 180 181 182 /** 183 \brief NAND ECC (Error Correction Code) Information 184 */ 185 typedef struct _ARM_NAND_ECC_INFO { 186 uint32_t type : 2; ///< Type: 1=ECC0 over Main, 2=ECC0 over Main+Spare, 3=ECC0 over Main and ECC1 over Spare 187 uint32_t page_layout : 1; ///< Page layout: 0=|Main0|Spare0|...|MainN-1|SpareN-1|, 1=|Main0|...|MainN-1|Spare0|...|SpareN-1| 188 uint32_t page_count : 3; ///< Number of virtual pages: N = 2 ^ page_count 189 uint32_t page_size : 4; ///< Virtual Page size (Main+Spare): 0=512+16, 1=1k+32, 2=2k+64, 3=4k+128, 4=8k+256, 8=512+28, 9=1k+56, 10=2k+112, 11=4k+224, 12=8k+448, 15=Not used (extended description) 190 uint32_t reserved : 14; ///< Reserved (must be zero) 191 uint32_t correctable_bits : 8; ///< Number of correctable bits (based on 512 byte codeword size) 192 uint16_t codeword_size [2]; ///< Number of bytes over which ECC is calculated 193 uint16_t ecc_size [2]; ///< ECC size in bytes (rounded up) 194 uint16_t ecc_offset [2]; ///< ECC offset in bytes (where ECC starts in Spare) 195 /* Extended description */ 196 uint16_t virtual_page_size [2]; ///< Virtual Page size in bytes (Main/Spare) 197 uint16_t codeword_offset [2]; ///< Codeword offset in bytes (where ECC protected data starts in Main/Spare) 198 uint16_t codeword_gap [2]; ///< Codeword gap in bytes till next protected data 199 uint16_t ecc_gap [2]; ///< ECC gap in bytes till next generated ECC 200 } ARM_NAND_ECC_INFO; 201 202 203 /** 204 \brief NAND Status 205 */ 206 typedef struct _ARM_NAND_STATUS { 207 uint32_t busy : 1; ///< Driver busy flag 208 uint32_t ecc_error : 1; ///< ECC error detected (cleared on next Read/WriteData or ExecuteSequence) 209 uint32_t reserved : 30; 210 } ARM_NAND_STATUS; 211 212 213 /****** NAND Event *****/ 214 #define ARM_NAND_EVENT_DEVICE_READY (1UL << 0) ///< Device Ready: R/Bn rising edge 215 #define ARM_NAND_EVENT_DRIVER_READY (1UL << 1) ///< Driver Ready 216 #define ARM_NAND_EVENT_DRIVER_DONE (1UL << 2) ///< Driver operation done 217 #define ARM_NAND_EVENT_ECC_ERROR (1UL << 3) ///< ECC could not correct data 218 219 220 // Function documentation 221 /** 222 \fn ARM_DRIVER_VERSION ARM_NAND_GetVersion (void) 223 \brief Get driver version. 224 \return \ref ARM_DRIVER_VERSION 225 */ 226 /** 227 \fn ARM_NAND_CAPABILITIES ARM_NAND_GetCapabilities (void) 228 \brief Get driver capabilities. 229 \return \ref ARM_NAND_CAPABILITIES 230 */ 231 /** 232 \fn int32_t ARM_NAND_Initialize (ARM_NAND_SignalEvent_t cb_event) 233 \brief Initialize the NAND Interface. 234 \param[in] cb_event Pointer to \ref ARM_NAND_SignalEvent 235 \return \ref execution_status 236 */ 237 /** 238 \fn int32_t ARM_NAND_Uninitialize (void) 239 \brief De-initialize the NAND Interface. 240 \return \ref execution_status 241 */ 242 /** 243 \fn int32_t ARM_NAND_PowerControl (ARM_POWER_STATE state) 244 \brief Control the NAND interface power. 245 \param[in] state Power state 246 \return \ref execution_status 247 */ 248 /** 249 \fn int32_t ARM_NAND_DevicePower (uint32_t voltage) 250 \brief Set device power supply voltage. 251 \param[in] voltage NAND Device supply voltage 252 \return \ref execution_status 253 */ 254 /** 255 \fn int32_t ARM_NAND_WriteProtect (uint32_t dev_num, bool enable) 256 \brief Control WPn (Write Protect). 257 \param[in] dev_num Device number 258 \param[in] enable 259 - \b false Write Protect off 260 - \b true Write Protect on 261 \return \ref execution_status 262 */ 263 /** 264 \fn int32_t ARM_NAND_ChipEnable (uint32_t dev_num, bool enable) 265 \brief Control CEn (Chip Enable). 266 \param[in] dev_num Device number 267 \param[in] enable 268 - \b false Chip Enable off 269 - \b true Chip Enable on 270 \return \ref execution_status 271 */ 272 /** 273 \fn int32_t ARM_NAND_GetDeviceBusy (uint32_t dev_num) 274 \brief Get Device Busy pin state. 275 \param[in] dev_num Device number 276 \return 1=busy, 0=not busy, or error 277 */ 278 /** 279 \fn int32_t ARM_NAND_SendCommand (uint32_t dev_num, uint8_t cmd) 280 \brief Send command to NAND device. 281 \param[in] dev_num Device number 282 \param[in] cmd Command 283 \return \ref execution_status 284 */ 285 /** 286 \fn int32_t ARM_NAND_SendAddress (uint32_t dev_num, uint8_t addr) 287 \brief Send address to NAND device. 288 \param[in] dev_num Device number 289 \param[in] addr Address 290 \return \ref execution_status 291 */ 292 /** 293 \fn int32_t ARM_NAND_ReadData (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode) 294 \brief Read data from NAND device. 295 \param[in] dev_num Device number 296 \param[out] data Pointer to buffer for data to read from NAND device 297 \param[in] cnt Number of data items to read 298 \param[in] mode Operation mode 299 \return number of data items read or \ref execution_status 300 */ 301 /** 302 \fn int32_t ARM_NAND_WriteData (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode) 303 \brief Write data to NAND device. 304 \param[in] dev_num Device number 305 \param[out] data Pointer to buffer with data to write to NAND device 306 \param[in] cnt Number of data items to write 307 \param[in] mode Operation mode 308 \return number of data items written or \ref execution_status 309 */ 310 /** 311 \fn int32_t ARM_NAND_ExecuteSequence (uint32_t dev_num, uint32_t code, uint32_t cmd, 312 uint32_t addr_col, uint32_t addr_row, 313 void *data, uint32_t data_cnt, 314 uint8_t *status, uint32_t *count) 315 \brief Execute sequence of operations. 316 \param[in] dev_num Device number 317 \param[in] code Sequence code 318 \param[in] cmd Command(s) 319 \param[in] addr_col Column address 320 \param[in] addr_row Row address 321 \param[in,out] data Pointer to data to be written or read 322 \param[in] data_cnt Number of data items in one iteration 323 \param[out] status Pointer to status read 324 \param[in,out] count Number of iterations 325 \return \ref execution_status 326 */ 327 /** 328 \fn int32_t ARM_NAND_AbortSequence (uint32_t dev_num) 329 \brief Abort sequence execution. 330 \param[in] dev_num Device number 331 \return \ref execution_status 332 */ 333 /** 334 \fn int32_t ARM_NAND_Control (uint32_t dev_num, uint32_t control, uint32_t arg) 335 \brief Control NAND Interface. 336 \param[in] dev_num Device number 337 \param[in] control Operation 338 \param[in] arg Argument of operation 339 \return \ref execution_status 340 */ 341 /** 342 \fn ARM_NAND_STATUS ARM_NAND_GetStatus (uint32_t dev_num) 343 \brief Get NAND status. 344 \param[in] dev_num Device number 345 \return NAND status \ref ARM_NAND_STATUS 346 */ 347 /** 348 \fn int32_t ARM_NAND_InquireECC (int32_t index, ARM_NAND_ECC_INFO *info) 349 \brief Inquire about available ECC. 350 \param[in] index Inquire ECC index 351 \param[out] info Pointer to ECC information \ref ARM_NAND_ECC_INFO retrieved 352 \return \ref execution_status 353 */ 354 355 /** 356 \fn void ARM_NAND_SignalEvent (uint32_t dev_num, uint32_t event) 357 \brief Signal NAND event. 358 \param[in] dev_num Device number 359 \param[in] event Event notification mask 360 \return none 361 */ 362 363 typedef void (*ARM_NAND_SignalEvent_t) (uint32_t dev_num, uint32_t event); ///< Pointer to \ref ARM_NAND_SignalEvent : Signal NAND Event. 364 365 366 /** 367 \brief NAND Driver Capabilities. 368 */ 369 typedef struct _ARM_NAND_CAPABILITIES { 370 uint32_t event_device_ready : 1; ///< Signal Device Ready event (R/Bn rising edge) 371 uint32_t reentrant_operation : 1; ///< Supports re-entrant operation (SendCommand/Address, Read/WriteData) 372 uint32_t sequence_operation : 1; ///< Supports Sequence operation (ExecuteSequence, AbortSequence) 373 uint32_t vcc : 1; ///< Supports VCC Power Supply Control 374 uint32_t vcc_1v8 : 1; ///< Supports 1.8 VCC Power Supply 375 uint32_t vccq : 1; ///< Supports VCCQ I/O Power Supply Control 376 uint32_t vccq_1v8 : 1; ///< Supports 1.8 VCCQ I/O Power Supply 377 uint32_t vpp : 1; ///< Supports VPP High Voltage Power Supply Control 378 uint32_t wp : 1; ///< Supports WPn (Write Protect) Control 379 uint32_t ce_lines : 4; ///< Number of CEn (Chip Enable) lines: ce_lines + 1 380 uint32_t ce_manual : 1; ///< Supports manual CEn (Chip Enable) Control 381 uint32_t rb_monitor : 1; ///< Supports R/Bn (Ready/Busy) Monitoring 382 uint32_t data_width_16 : 1; ///< Supports 16-bit data 383 uint32_t ddr : 1; ///< Supports NV-DDR Data Interface (ONFI) 384 uint32_t ddr2 : 1; ///< Supports NV-DDR2 Data Interface (ONFI) 385 uint32_t sdr_timing_mode : 3; ///< Fastest (highest) SDR Timing Mode supported (ONFI) 386 uint32_t ddr_timing_mode : 3; ///< Fastest (highest) NV_DDR Timing Mode supported (ONFI) 387 uint32_t ddr2_timing_mode : 3; ///< Fastest (highest) NV_DDR2 Timing Mode supported (ONFI) 388 uint32_t driver_strength_18 : 1; ///< Supports Driver Strength 2.0x = 18 Ohms 389 uint32_t driver_strength_25 : 1; ///< Supports Driver Strength 1.4x = 25 Ohms 390 uint32_t driver_strength_50 : 1; ///< Supports Driver Strength 0.7x = 50 Ohms 391 uint32_t reserved : 2; ///< Reserved (must be zero) 392 } ARM_NAND_CAPABILITIES; 393 394 395 /** 396 \brief Access structure of the NAND Driver. 397 */ 398 typedef struct _ARM_DRIVER_NAND { 399 ARM_DRIVER_VERSION (*GetVersion) (void); ///< Pointer to \ref ARM_NAND_GetVersion : Get driver version. 400 ARM_NAND_CAPABILITIES (*GetCapabilities)(void); ///< Pointer to \ref ARM_NAND_GetCapabilities : Get driver capabilities. 401 int32_t (*Initialize) (ARM_NAND_SignalEvent_t cb_event); ///< Pointer to \ref ARM_NAND_Initialize : Initialize NAND Interface. 402 int32_t (*Uninitialize) (void); ///< Pointer to \ref ARM_NAND_Uninitialize : De-initialize NAND Interface. 403 int32_t (*PowerControl) (ARM_POWER_STATE state); ///< Pointer to \ref ARM_NAND_PowerControl : Control NAND Interface Power. 404 int32_t (*DevicePower) (uint32_t voltage); ///< Pointer to \ref ARM_NAND_DevicePower : Set device power supply voltage. 405 int32_t (*WriteProtect) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_WriteProtect : Control WPn (Write Protect). 406 int32_t (*ChipEnable) (uint32_t dev_num, bool enable); ///< Pointer to \ref ARM_NAND_ChipEnable : Control CEn (Chip Enable). 407 int32_t (*GetDeviceBusy) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetDeviceBusy : Get Device Busy pin state. 408 int32_t (*SendCommand) (uint32_t dev_num, uint8_t cmd); ///< Pointer to \ref ARM_NAND_SendCommand : Send command to NAND device. 409 int32_t (*SendAddress) (uint32_t dev_num, uint8_t addr); ///< Pointer to \ref ARM_NAND_SendAddress : Send address to NAND device. 410 int32_t (*ReadData) (uint32_t dev_num, void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_ReadData : Read data from NAND device. 411 int32_t (*WriteData) (uint32_t dev_num, const void *data, uint32_t cnt, uint32_t mode); ///< Pointer to \ref ARM_NAND_WriteData : Write data to NAND device. 412 int32_t (*ExecuteSequence)(uint32_t dev_num, uint32_t code, uint32_t cmd, 413 uint32_t addr_col, uint32_t addr_row, 414 void *data, uint32_t data_cnt, 415 uint8_t *status, uint32_t *count); ///< Pointer to \ref ARM_NAND_ExecuteSequence : Execute sequence of operations. 416 int32_t (*AbortSequence) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_AbortSequence : Abort sequence execution. 417 int32_t (*Control) (uint32_t dev_num, uint32_t control, uint32_t arg); ///< Pointer to \ref ARM_NAND_Control : Control NAND Interface. 418 ARM_NAND_STATUS (*GetStatus) (uint32_t dev_num); ///< Pointer to \ref ARM_NAND_GetStatus : Get NAND status. 419 int32_t (*InquireECC) ( int32_t index, ARM_NAND_ECC_INFO *info); ///< Pointer to \ref ARM_NAND_InquireECC : Inquire about available ECC. 420 } const ARM_DRIVER_NAND; 421 422 #ifdef __cplusplus 423 } 424 #endif 425 426 #endif /* DRIVER_NAND_H_ */ 427
