1 /*
2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without modification,
6 * are permitted provided that the following conditions are met:
7 *
8 * o Redistributions of source code must retain the above copyright notice, this list
9 * of conditions and the following disclaimer.
10 *
11 * o Redistributions in binary form must reproduce the above copyright notice, this
12 * list of conditions and the following disclaimer in the documentation and/or
13 * other materials provided with the distribution.
14 *
15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
16 * contributors may be used to endorse or promote products derived from this
17 * software without specific prior written permission.
18 *
19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 */
30
31 #ifndef __CCM_IMX6SX_H__
32 #define __CCM_IMX6SX_H__
33
34 #include <stdint.h>
35 #include <stdbool.h>
36 #include <stddef.h>
37 #include <assert.h>
38 #include "device_imx.h"
39
40 /*!
41 * @addtogroup ccm_driver
42 * @{
43 */
44
45 /*******************************************************************************
46 * Definitions
47 ******************************************************************************/
48 #define CCM_TUPLE(reg, shift, mask) ((offsetof(CCM_Type, reg) & 0xFF) | ((shift) << 8) | (((mask >> shift) & 0xFFFF) << 16))
49 #define CCM_TUPLE_REG(base, tuple) (*((volatile uint32_t *)((uint32_t)base + ((tuple) & 0xFF))))
50 #define CCM_TUPLE_SHIFT(tuple) (((tuple) >> 8) & 0x1F)
51 #define CCM_TUPLE_MASK(tuple) ((uint32_t)((((tuple) >> 16) & 0xFFFF) << ((((tuple) >> 8) & 0x1F))))
52
53 /*!
54 * @brief Root control names for root clock setting.
55 *
56 * These constants define the root control names for root clock setting.\n
57 * - 0:7: REG offset to CCM_BASE in bytes.
58 * - 8:15: Root clock setting bit field shift.
59 * - 16:31: Root clock setting bit field width.
60 */
61 enum _ccm_root_clock_control
62 {
63 ccmRootPll1SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll1_sw_clk_sel_SHIFT, CCM_CCSR_pll1_sw_clk_sel_MASK), /*!< PLL1 SW Clock control name.*/
64 ccmRootStepSel = CCM_TUPLE(CCSR, CCM_CCSR_step_sel_SHIFT, CCM_CCSR_step_sel_MASK), /*!< Step SW Clock control name.*/
65 ccmRootPeriph2ClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk_sel_SHIFT, CCM_CBCDR_periph2_clk_sel_MASK), /*!< Peripheral2 Clock control name.*/
66 ccmRootPrePeriph2ClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph2_clk_sel_SHIFT, CCM_CBCMR_pre_periph2_clk_sel_MASK), /*!< Pre Peripheral2 Clock control name.*/
67 ccmRootPeriph2Clk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph2_clk2_sel_SHIFT, CCM_CBCMR_periph2_clk2_sel_MASK), /*!< Peripheral2 Clock2 Clock control name.*/
68 ccmRootPll3SwClkSel = CCM_TUPLE(CCSR, CCM_CCSR_pll3_sw_clk_sel_SHIFT, CCM_CCSR_pll3_sw_clk_sel_MASK), /*!< PLL3 SW Clock control name.*/
69 ccmRootOcramClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_clk_sel_SHIFT, CCM_CBCDR_ocram_clk_sel_MASK), /*!< OCRAM Clock control name.*/
70 ccmRootOcramAltClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_alt_clk_sel_SHIFT, CCM_CBCDR_ocram_alt_clk_sel_MASK), /*!< OCRAM ALT Clock control name.*/
71 ccmRootPeriphClkSel = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk_sel_SHIFT, CCM_CBCDR_periph_clk_sel_MASK), /*!< Peripheral Clock control name.*/
72 ccmRootPeriphClk2Sel = CCM_TUPLE(CBCMR, CCM_CBCMR_periph_clk2_sel_SHIFT, CCM_CBCMR_periph_clk2_sel_MASK), /*!< Peripheral Clock2 control name.*/
73 ccmRootPrePeriphClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pre_periph_clk_sel_SHIFT, CCM_CBCMR_pre_periph_clk_sel_MASK), /*!< Pre Peripheral Clock control name.*/
74 ccmRootPcieAxiClkSel = CCM_TUPLE(CBCMR, CCM_CBCMR_pcie_axi_clk_sel_SHIFT, CCM_CBCMR_pcie_axi_clk_sel_MASK), /*!< PCIE AXI Clock control name.*/
75 ccmRootPerclkClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_clk_sel_SHIFT, CCM_CSCMR1_perclk_clk_sel_MASK), /*!< Pre Clock control name.*/
76 ccmRootUsdhc1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc1_clk_sel_SHIFT, CCM_CSCMR1_usdhc1_clk_sel_MASK), /*!< USDHC1 Clock control name.*/
77 ccmRootUsdhc2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc2_clk_sel_SHIFT, CCM_CSCMR1_usdhc2_clk_sel_MASK), /*!< USDHC2 Clock control name.*/
78 ccmRootUsdhc3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc3_clk_sel_SHIFT, CCM_CSCMR1_usdhc3_clk_sel_MASK), /*!< USDHC3 Clock control name.*/
79 ccmRootUsdhc4ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_usdhc4_clk_sel_SHIFT, CCM_CSCMR1_usdhc4_clk_sel_MASK), /*!< USDHC4 Clock control name.*/
80 ccmRootAclkEimSlowSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_sel_SHIFT, CCM_CSCMR1_aclk_eim_slow_sel_MASK), /*!< ACLK EIM SLOW Clock control name.*/
81 ccmRootGpuAxiSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_sel_SHIFT, CCM_CBCMR_gpu_axi_sel_MASK), /*!< GPU AXI Clock control name.*/
82 ccmRootGpuCoreSel = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_sel_SHIFT, CCM_CBCMR_gpu_core_sel_MASK), /*!< GPU Core Clock control name.*/
83 ccmRootVidClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_sel_SHIFT, CCM_CSCMR2_vid_clk_sel_MASK), /*!< VID Clock control name.*/
84 ccmRootEsaiClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_esai_clk_sel_SHIFT, CCM_CSCMR2_esai_clk_sel_MASK), /*!< ESAI Clock control name.*/
85 ccmRootAudioClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_sel_SHIFT, CCM_CDCDR_audio_clk_sel_MASK), /*!< AUDIO Clock control name.*/
86 ccmRootSpdif0ClkSel = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_sel_SHIFT, CCM_CDCDR_spdif0_clk_sel_MASK), /*!< SPDIF0 Clock control name.*/
87 ccmRootSsi1ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi1_clk_sel_SHIFT, CCM_CSCMR1_ssi1_clk_sel_MASK), /*!< SSI1 Clock control name.*/
88 ccmRootSsi2ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi2_clk_sel_SHIFT, CCM_CSCMR1_ssi2_clk_sel_MASK), /*!< SSI2 Clock control name.*/
89 ccmRootSsi3ClkSel = CCM_TUPLE(CSCMR1, CCM_CSCMR1_ssi3_clk_sel_SHIFT, CCM_CSCMR1_ssi3_clk_sel_MASK), /*!< SSI3 Clock control name.*/
90 ccmRootLcdif2ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_clk_sel_MASK), /*!< LCDIF2 Clock control name.*/
91 ccmRootLcdif2PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif2_pre_clk_sel_MASK), /*!< LCDIF2 Pre Clock control name.*/
92 ccmRootLdbDi1ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di1_clk_sel_SHIFT, CCM_CS2CDR_ldb_di1_clk_sel_MASK), /*!< LDB DI1 Clock control name.*/
93 ccmRootLdbDi0ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ldb_di0_clk_sel_SHIFT, CCM_CS2CDR_ldb_di0_clk_sel_MASK), /*!< LDB DI0 Clock control name.*/
94 ccmRootLcdif1ClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_clk_sel_MASK), /*!< LCDIF1 Clock control name.*/
95 ccmRootLcdif1PreClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pre_clk_sel_SHIFT, CCM_CSCDR2_lcdif1_pre_clk_sel_MASK), /*!< LCDIF1 Pre Clock control name.*/
96 ccmRootM4ClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_clk_sel_SHIFT, CCM_CHSCCDR_m4_clk_sel_MASK), /*!< M4 Clock control name.*/
97 ccmRootM4PreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_pre_clk_sel_SHIFT, CCM_CHSCCDR_m4_pre_clk_sel_MASK), /*!< M4 Pre Clock control name.*/
98 ccmRootEnetClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_clk_sel_SHIFT, CCM_CHSCCDR_enet_clk_sel_MASK), /*!< Ethernet Clock control name.*/
99 ccmRootEnetPreClkSel = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_pre_clk_sel_SHIFT, CCM_CHSCCDR_enet_pre_clk_sel_MASK), /*!< Ethernet Pre Clock control name.*/
100 ccmRootQspi2ClkSel = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_sel_SHIFT, CCM_CS2CDR_qspi2_clk_sel_MASK), /*!< QSPI2 Clock control name.*/
101 ccmRootDisplayClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_clk_sel_SHIFT, CCM_CSCDR3_display_clk_sel_MASK), /*!< Display Clock control name.*/
102 ccmRootCsiClkSel = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_clk_sel_SHIFT, CCM_CSCDR3_csi_clk_sel_MASK), /*!< CSI Clock control name.*/
103 ccmRootCanClkSel = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_sel_SHIFT, CCM_CSCMR2_can_clk_sel_MASK), /*!< CAN Clock control name.*/
104 ccmRootEcspiClkSel = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_sel_SHIFT, CCM_CSCDR2_ecspi_clk_sel_MASK), /*!< ECSPI Clock control name.*/
105 ccmRootUartClkSel = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_sel_SHIFT, CCM_CSCDR1_uart_clk_sel_MASK) /*!< UART Clock control name.*/
106 };
107
108 /*! @brief Root clock select enumeration for pll1_sw_clk_sel. */
109 enum _ccm_rootmux_pll1_sw_clk_sel
110 {
111 ccmRootmuxPll1SwClkPll1MainClk = 0U, /*!< PLL1 SW Clock from PLL1 Main Clock.*/
112 ccmRootmuxPll1SwClkStepClk = 1U, /*!< PLL1 SW Clock from Step Clock.*/
113 };
114
115 /*! @brief Root clock select enumeration for step_sel. */
116 enum _ccm_rootmux_step_sel
117 {
118 ccmRootmuxStepOsc24m = 0U, /*!< Step Clock from OSC 24M.*/
119 ccmRootmuxStepPll2Pfd2 = 1U, /*!< Step Clock from PLL2 PFD2.*/
120 };
121
122 /*! @brief Root clock select enumeration for periph2_clk_sel. */
123 enum _ccm_rootmux_periph2_clk_sel
124 {
125 ccmRootmuxPeriph2ClkPrePeriph2Clk = 0U, /*!< Peripheral2 Clock from Pre Peripheral2 Clock.*/
126 ccmRootmuxPeriph2ClkPeriph2Clk2 = 1U, /*!< Peripheral2 Clock from Peripheral2.*/
127 };
128
129 /*! @brief Root clock select enumeration for pre_periph2_clk_sel. */
130 enum _ccm_rootmux_pre_periph2_clk_sel
131 {
132 ccmRootmuxPrePeriph2ClkPll2 = 0U, /*!< Pre Peripheral2 Clock from PLL2.*/
133 ccmRootmuxPrePeriph2ClkPll2Pfd2 = 1U, /*!< Pre Peripheral2 Clock from PLL2 PFD2.*/
134 ccmRootmuxPrePeriph2ClkPll2Pfd0 = 2U, /*!< Pre Peripheral2 Clock from PLL2 PFD0.*/
135 ccmRootmuxPrePeriph2ClkPll4 = 3U, /*!< Pre Peripheral2 Clock from PLL4.*/
136 };
137
138 /*! @brief Root clock select enumeration for periph2_clk2_sel. */
139 enum _ccm_rootmux_periph2_clk2_sel
140 {
141 ccmRootmuxPeriph2Clk2Pll3SwClk = 0U, /*!< Peripheral2 Clock from PLL3 SW Clock.*/
142 ccmRootmuxPeriph2Clk2Osc24m = 1U, /*!< Peripheral2 Clock from OSC 24M.*/
143 };
144
145 /*! @brief Root clock select enumeration for pll3_sw_clk_sel. */
146 enum _ccm_rootmux_pll3_sw_clk_sel
147 {
148 ccmRootmuxPll3SwClkPll3 = 0U, /*!< PLL3 SW Clock from PLL3.*/
149 ccmRootmuxPll3SwClkPll3BypassClk = 1U, /*!< PLL3 SW Clock from PLL3 Bypass Clock.*/
150 };
151
152 /*! @brief Root clock select enumeration for ocram_clk_sel. */
153 enum _ccm_rootmux_ocram_clk_sel
154 {
155 ccmRootmuxOcramClkPeriphClk = 0U, /*!< OCRAM Clock from Peripheral Clock.*/
156 ccmRootmuxOcramClkOcramAltClk = 1U, /*!< OCRAM Clock from OCRAM ALT Clock.*/
157 };
158
159 /*! @brief Root clock select enumeration for ocram_alt_clk_sel. */
160 enum _ccm_rootmux_ocram_alt_clk_sel
161 {
162 ccmRootmuxOcramAltClkPll2Pfd2 = 0U, /*!< OCRAM ALT Clock from PLL2 PFD2.*/
163 ccmRootmuxOcramAltClkPll3Pfd1 = 1U, /*!< OCRAM ALT Clock from PLL3 PFD1.*/
164 };
165
166 /*! @brief Root clock select enumeration for periph_clk_sel. */
167 enum _ccm_rootmux_periph_clk_sel
168 {
169 ccmRootmuxPeriphClkPrePeriphClkSel = 0U, /*!< Peripheral Clock from Pre Peripheral .*/
170 ccmRootmuxPeriphClkPeriphClk2Sel = 1U, /*!< Peripheral Clock from Peripheral2.*/
171 };
172
173 /*! @brief Root clock select enumeration for periph_clk2_sel. */
174 enum _ccm_rootmux_periph_clk2_sel
175 {
176 ccmRootmuxPeriphClk2Pll3SwClk = 0U, /*!< Peripheral Clock2 from from PLL3 SW Clock.*/
177 ccmRootmuxPeriphClk2OSC24m = 1U, /*!< Peripheral Clock2 from OSC 24M.*/
178 ccmRootmuxPeriphClk2Pll2 = 2U, /*!< Peripheral Clock2 from PLL2.*/
179 };
180
181 /*! @brief Root clock select enumeration for pre_periph_clk_sel. */
182 enum _ccm_rootmux_pre_periph_clk_sel
183 {
184 ccmRootmuxPrePeriphClkPll2 = 0U, /*!< Pre Peripheral Clock from PLL2.*/
185 ccmRootmuxPrePeriphClkPll2Pfd2 = 1U, /*!< Pre Peripheral Clock from PLL2 PFD2.*/
186 ccmRootmuxPrePeriphClkPll2Pfd0 = 2U, /*!< Pre Peripheral Clock from PLL2 PFD0.*/
187 ccmRootmuxPrePeriphClkPll2Pfd2div2 = 3U, /*!< Pre Peripheral Clock from PLL2 PFD2 divided by 2.*/
188 };
189
190 /*! @brief Root clock select enumeration for pcie_axi_clk_sel. */
191 enum _ccm_rootmux_pcie_axi_clk_sel
192 {
193 ccmRootmuxPcieAxiClkAxiClk = 0U, /*!< PCIE AXI Clock from AXI Clock.*/
194 ccmRootmuxPcieAxiClkAhbClk = 1U, /*!< PCIE AXI Clock from AHB Clock.*/
195 };
196
197 /*! @brief Root clock select enumeration for perclk_clk_sel. */
198 enum _ccm_rootmux_perclk_clk_sel
199 {
200 ccmRootmuxPerclkClkIpgClkRoot = 0U, /*!< Perclk from IPG Clock Root.*/
201 ccmRootmuxPerclkClkOsc24m = 1U, /*!< Perclk from OSC 24M.*/
202 };
203
204 /*! @brief Root clock select enumeration for usdhc1_clk_sel. */
205 enum _ccm_rootmux_usdhc1_clk_sel
206 {
207 ccmRootmuxUsdhc1ClkPll2Pfd2 = 0U, /*!< USDHC1 Clock from PLL2 PFD2.*/
208 ccmRootmuxUsdhc1ClkPll2Pfd0 = 1U, /*!< USDHC1 Clock from PLL2 PFD0.*/
209 };
210
211 /*! @brief Root clock select enumeration for usdhc2_clk_sel. */
212 enum _ccm_rootmux_usdhc2_clk_sel
213 {
214 ccmRootmuxUsdhc2ClkPll2Pfd2 = 0U, /*!< USDHC2 Clock from PLL2 PFD2.*/
215 ccmRootmuxUsdhc2ClkPll2Pfd0 = 1U, /*!< USDHC2 Clock from PLL2 PFD0.*/
216 };
217
218 /*! @brief Root clock select enumeration for usdhc3_clk_sel. */
219 enum _ccm_rootmux_usdhc3_clk_sel
220 {
221 ccmRootmuxUsdhc3ClkPll2Pfd2 = 0U, /*!< USDHC3 Clock from PLL2 PFD2.*/
222 ccmRootmuxUsdhc3ClkPll2Pfd0 = 1U, /*!< USDHC3 Clock from PLL2 PFD0.*/
223 };
224
225 /*! @brief Root clock select enumeration for usdhc4_clk_sel. */
226 enum _ccm_rootmux_usdhc4_clk_sel
227 {
228 ccmRootmuxUsdhc4ClkPll2Pfd2 = 0U, /*!< USDHC4 Clock from PLL2 PFD2.*/
229 ccmRootmuxUsdhc4ClkPll2Pfd0 = 1U, /*!< USDHC4 Clock from PLL2 PFD0.*/
230 };
231
232 /*! @brief Root clock select enumeration for aclk_eim_slow_sel. */
233 enum _ccm_rootmux_aclk_eim_slow_sel
234 {
235 ccmRootmuxAclkEimSlowAxiClk = 0U, /*!< Aclk EimSlow Clock from AXI Clock.*/
236 ccmRootmuxAclkEimSlowPll3SwClk = 1U, /*!< Aclk EimSlow Clock from PLL3 SW Clock.*/
237 ccmRootmuxAclkEimSlowPll2Pfd2 = 2U, /*!< Aclk EimSlow Clock from PLL2 PFD2.*/
238 ccmRootmuxAclkEimSlowPll3Pfd0 = 3U, /*!< Aclk EimSlow Clock from PLL3 PFD0.*/
239 };
240
241 /*! @brief Root clock select enumeration for gpu_axi_sel. */
242 enum _ccm_rootmux_gpu_axi_sel
243 {
244 ccmRootmuxGpuAxiPll2Pfd2 = 0U, /*!< GPU AXI Clock from PLL2 PFD2.*/
245 ccmRootmuxGpuAxiPll3Pfd0 = 1U, /*!< GPU AXI Clock from PLL3 PFD0.*/
246 ccmRootmuxGpuAxiPll2Pfd1 = 2U, /*!< GPU AXI Clock from PLL2 PFD1.*/
247 ccmRootmuxGpuAxiPll2 = 3U, /*!< GPU AXI Clock from PLL2.*/
248 };
249
250 /*! @brief Root clock select enumeration for gpu_core_sel. */
251 enum _ccm_rootmux_gpu_core_sel
252 {
253 ccmRootmuxGpuCorePll3Pfd1 = 0U, /*!< GPU Core Clock from PLL3 PFD1.*/
254 ccmRootmuxGpuCorePll3Pfd0 = 1U, /*!< GPU Core Clock from PLL3 PFD0.*/
255 ccmRootmuxGpuCorePll2 = 2U, /*!< GPU Core Clock from PLL2.*/
256 ccmRootmuxGpuCorePll2Pfd2 = 3U, /*!< GPU Core Clock from PLL2 PFD2.*/
257 };
258
259 /*! @brief Root clock select enumeration for vid_clk_sel. */
260 enum _ccm_rootmux_vid_clk_sel
261 {
262 ccmRootmuxVidClkPll3Pfd1 = 0U, /*!< VID Clock from PLL3 PFD1.*/
263 ccmRootmuxVidClkPll3 = 1U, /*!< VID Clock from PLL3.*/
264 ccmRootmuxVidClkPll3Pfd3 = 2U, /*!< VID Clock from PLL3 PFD3.*/
265 ccmRootmuxVidClkPll4 = 3U, /*!< VID Clock from PLL4.*/
266 ccmRootmuxVidClkPll5 = 4U, /*!< VID Clock from PLL5.*/
267 };
268
269 /*! @brief Root clock select enumeration for esai_clk_sel. */
270 enum _ccm_rootmux_esai_clk_sel
271 {
272 ccmRootmuxEsaiClkPll4 = 0U, /*!< ESAI Clock from PLL4.*/
273 ccmRootmuxEsaiClkPll3Pfd2 = 1U, /*!< ESAI Clock from PLL3 PFD2.*/
274 ccmRootmuxEsaiClkPll5 = 2U, /*!< ESAI Clock from PLL5.*/
275 ccmRootmuxEsaiClkPll3SwClk = 3U, /*!< ESAI Clock from PLL3 SW Clock.*/
276 };
277
278 /*! @brief Root clock select enumeration for audio_clk_sel. */
279 enum _ccm_rootmux_audio_clk_sel
280 {
281 ccmRootmuxAudioClkPll4 = 0U, /*!< Audio Clock from PLL4.*/
282 ccmRootmuxAudioClkPll3Pfd2 = 1U, /*!< Audio Clock from PLL3 PFD2.*/
283 ccmRootmuxAudioClkPll5 = 2U, /*!< Audio Clock from PLL5.*/
284 ccmRootmuxAudioClkPll3SwClk = 3U, /*!< Audio Clock from PLL3 SW Clock.*/
285 };
286
287 /*! @brief Root clock select enumeration for spdif0_clk_sel. */
288 enum _ccm_rootmux_spdif0_clk_sel
289 {
290 ccmRootmuxSpdif0ClkPll4 = 0U, /*!< SPDIF0 Clock from PLL4.*/
291 ccmRootmuxSpdif0ClkPll3Pfd2 = 1U, /*!< SPDIF0 Clock from PLL3 PFD2.*/
292 ccmRootmuxSpdif0ClkPll5 = 2U, /*!< SPDIF0 Clock from PLL5.*/
293 ccmRootmuxSpdif0ClkPll3SwClk = 3U, /*!< SPDIF0 Clock from PLL3 SW Clock.*/
294 };
295
296 /*! @brief Root clock select enumeration for ssi1_clk_sel. */
297 enum _ccm_rootmux_ssi1_clk_sel
298 {
299 ccmRootmuxSsi1ClkPll3Pfd2 = 0U, /*!< SSI1 Clock from PLL3 PFD2.*/
300 ccmRootmuxSsi1ClkPll5 = 1U, /*!< SSI1 Clock from PLL5.*/
301 ccmRootmuxSsi1ClkPll4 = 2U, /*!< SSI1 Clock from PLL4.*/
302 };
303
304 /*! @brief Root clock select enumeration for ssi2_clk_sel. */
305 enum _ccm_rootmux_ssi2_clk_sel
306 {
307 ccmRootmuxSsi2ClkPll3Pfd2 = 0U, /*!< SSI2 Clock from PLL3 PFD2.*/
308 ccmRootmuxSsi2ClkPll5 = 1U, /*!< SSI2 Clock from PLL5.*/
309 ccmRootmuxSsi2ClkPll4 = 2U, /*!< SSI2 Clock from PLL4.*/
310 };
311
312 /*! @brief Root clock select enumeration for ssi3_clk_sel. */
313 enum _ccm_rootmux_ssi3_clk_sel
314 {
315 ccmRootmuxSsi3ClkPll3Pfd2 = 0U, /*!< SSI3 Clock from PLL3 PFD2.*/
316 ccmRootmuxSsi3ClkPll5 = 1U, /*!< SSI3 Clock from PLL5.*/
317 ccmRootmuxSsi3ClkPll4 = 2U, /*!< SSI3 Clock from PLL4.*/
318 };
319
320 /*! @brief Root clock select enumeration for lcdif2_clk_sel. */
321 enum _ccm_rootmux_lcdif2_clk_sel
322 {
323 ccmRootmuxLcdif2ClkLcdif2PreClk = 0U, /*!< LCDIF2 Clock from LCDIF2 Pre Clock.*/
324 ccmRootmuxLcdif2ClkIppDi0Clk = 1U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/
325 ccmRootmuxLcdif2ClkIppDi1Clk = 2U, /*!< LCDIF2 Clock from IPP DI0 Clock.*/
326 ccmRootmuxLcdif2ClkLdbDi0Clk = 3U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/
327 ccmRootmuxLcdif2ClkLdbDi1Clk = 4U, /*!< LCDIF2 Clock from LDB DI0 Clock.*/
328 };
329
330 /*! @brief Root clock select enumeration for lcdif2_pre_clk_sel. */
331 enum _ccm_rootmux_lcdif2_pre_clk_sel
332 {
333 ccmRootmuxLcdif2ClkPrePll2 = 0U, /*!< LCDIF2 Pre Clock from PLL2.*/
334 ccmRootmuxLcdif2ClkPrePll3Pfd3 = 1U, /*!< LCDIF2 Pre Clock from PLL3 PFD3.*/
335 ccmRootmuxLcdif2ClkPrePll5 = 2U, /*!< LCDIF2 Pre Clock from PLL3 PFD5.*/
336 ccmRootmuxLcdif2ClkPrePll2Pfd0 = 3U, /*!< LCDIF2 Pre Clock from PLL2 PFD0.*/
337 ccmRootmuxLcdif2ClkPrePll2Pfd3 = 4U, /*!< LCDIF2 Pre Clock from PLL2 PFD3.*/
338 ccmRootmuxLcdif2ClkPrePll3Pfd1 = 5U, /*!< LCDIF2 Pre Clock from PLL3 PFD1.*/
339 };
340
341 /*! @brief Root clock select enumeration for ldb_di1_clk_sel. */
342 enum _ccm_rootmux_ldb_di1_clk_sel
343 {
344 ccmRootmuxLdbDi1ClkPll3SwClk = 0U, /*!< lDB DI1 Clock from PLL3 SW Clock.*/
345 ccmRootmuxLdbDi1ClkPll2Pfd0 = 1U, /*!< lDB DI1 Clock from PLL2 PFD0.*/
346 ccmRootmuxLdbDi1ClkPll2Pfd2 = 2U, /*!< lDB DI1 Clock from PLL2 PFD2.*/
347 ccmRootmuxLdbDi1ClkPll2 = 3U, /*!< lDB DI1 Clock from PLL2.*/
348 ccmRootmuxLdbDi1ClkPll3Pfd3 = 4U, /*!< lDB DI1 Clock from PLL3 PFD3.*/
349 ccmRootmuxLdbDi1ClkPll3Pfd2 = 5U, /*!< lDB DI1 Clock from PLL3 PFD2.*/
350 };
351
352 /*! @brief Root clock select enumeration for ldb_di0_clk_sel. */
353 enum _ccm_rootmux_ldb_di0_clk_sel
354 {
355 ccmRootmuxLdbDi0ClkPll5 = 0U, /*!< lDB DI0 Clock from PLL5.*/
356 ccmRootmuxLdbDi0ClkPll2Pfd0 = 1U, /*!< lDB DI0 Clock from PLL2 PFD0.*/
357 ccmRootmuxLdbDi0ClkPll2Pfd2 = 2U, /*!< lDB DI0 Clock from PLL2 PFD2.*/
358 ccmRootmuxLdbDi0ClkPll2Pfd3 = 3U, /*!< lDB DI0 Clock from PLL2 PFD3.*/
359 ccmRootmuxLdbDi0ClkPll3Pfd1 = 4U, /*!< lDB DI0 Clock from PLL3 PFD1.*/
360 ccmRootmuxLdbDi0ClkPll3Pfd3 = 5U, /*!< lDB DI0 Clock from PLL3 PFD3.*/
361 };
362
363 /*! @brief Root clock select enumeration for lcdif1_clk_sel. */
364 enum _ccm_rootmux_lcdif1_clk_sel
365 {
366 ccmRootmuxLcdif1ClkLcdif1PreClk = 0U, /*!< LCDIF1 clock from LCDIF1 Pre Clock.*/
367 ccmRootmuxLcdif1ClkIppDi0Clk = 1U, /*!< LCDIF1 clock from IPP DI0 Clock.*/
368 ccmRootmuxLcdif1ClkIppDi1Clk = 2U, /*!< LCDIF1 clock from IPP DI1 Clock.*/
369 ccmRootmuxLcdif1ClkLdbDi0Clk = 3U, /*!< LCDIF1 clock from LDB DI0 Clock.*/
370 ccmRootmuxLcdif1ClkLdbDi1Clk = 4U, /*!< LCDIF1 clock from LDB DI1 Clock.*/
371 };
372
373 /*! @brief Root clock select enumeration for lcdif1_pre_clk_sel. */
374 enum _ccm_rootmux_lcdif1_pre_clk_sel
375 {
376 ccmRootmuxLcdif1PreClkPll2 = 0U, /*!< LCDIF1 pre clock from PLL2.*/
377 ccmRootmuxLcdif1PreClkPll3Pfd3 = 1U, /*!< LCDIF1 pre clock from PLL3 PFD3.*/
378 ccmRootmuxLcdif1PreClkPll5 = 2U, /*!< LCDIF1 pre clock from PLL5.*/
379 ccmRootmuxLcdif1PreClkPll2Pfd0 = 3U, /*!< LCDIF1 pre clock from PLL2 PFD0.*/
380 ccmRootmuxLcdif1PreClkPll2Pfd1 = 4U, /*!< LCDIF1 pre clock from PLL2 PFD1.*/
381 ccmRootmuxLcdif1PreClkPll3Pfd1 = 5U, /*!< LCDIF1 pre clock from PLL3 PFD1.*/
382 };
383
384 /*! @brief Root clock select enumeration for m4_clk_sel. */
385 enum _ccm_rootmux_m4_clk_sel
386 {
387 ccmRootmuxM4ClkM4PreClk = 0U, /*!< M4 clock from M4 Pre Clock.*/
388 ccmRootmuxM4ClkPll3Pfd3 = 1U, /*!< M4 clock from PLL3 PFD3.*/
389 ccmRootmuxM4ClkIppDi0Clk = 2U, /*!< M4 clock from IPP DI0 Clock.*/
390 ccmRootmuxM4ClkIppDi1Clk = 3U, /*!< M4 clock from IPP DI1 Clock.*/
391 ccmRootmuxM4ClkLdbDi0Clk = 4U, /*!< M4 clock from LDB DI0 Clock.*/
392 ccmRootmuxM4ClkLdbDi1Clk = 5U, /*!< M4 clock from LDB DI1 Clock.*/
393 };
394
395 /*! @brief Root clock select enumeration for m4_pre_clk_sel. */
396 enum _ccm_rootmux_m4_pre_clk_sel
397 {
398 ccmRootmuxM4PreClkPll2 = 0U, /*!< M4 pre clock from PLL2.*/
399 ccmRootmuxM4PreClkPll3SwClk = 1U, /*!< M4 pre clock from PLL3 SW Clock.*/
400 ccmRootmuxM4PreClkOsc24m = 2U, /*!< M4 pre clock from OSC 24M.*/
401 ccmRootmuxM4PreClkPll2Pfd0 = 3U, /*!< M4 pre clock from PLL2 PFD0.*/
402 ccmRootmuxM4PreClkPll2Pfd2 = 4U, /*!< M4 pre clock from PLL2 PFD2.*/
403 ccmRootmuxM4PreClkPll3Pfd3 = 5U, /*!< M4 pre clock from PLL3 PFD3.*/
404 };
405
406 /*! @brief Root clock select enumeration for nent_clk_sel. */
407 enum _ccm_rootmux_enet_clk_sel
408 {
409 ccmRootmuxEnetClkEnetPreClk = 0U, /*!< Ethernet clock from Ethernet Pre Clock.*/
410 ccmRootmuxEnetClkIppDi0Clk = 1U, /*!< Ethernet clock from IPP DI0 Clock.*/
411 ccmRootmuxEnetClkIppDi1Clk = 2U, /*!< Ethernet clock from IPP DI1 Clock.*/
412 ccmRootmuxEnetClkLdbDi0Clk = 3U, /*!< Ethernet clock from LDB DI0 Clock.*/
413 ccmRootmuxEnetClkLdbDi1Clk = 4U, /*!< Ethernet clock from LDB DI1 Clock.*/
414 };
415
416 /*! @brief Root clock select enumeration for enet_pre_clk_sel. */
417 enum _ccm_rootmux_enet_pre_clk_sel
418 {
419 ccmRootmuxEnetPreClkPll2 = 0U, /*!< Ethernet Pre clock from PLL2.*/
420 ccmRootmuxEnetPreClkPll3SwClk = 1U, /*!< Ethernet Pre clock from PLL3 SW Clock.*/
421 ccmRootmuxEnetPreClkPll5 = 2U, /*!< Ethernet Pre clock from PLL5.*/
422 ccmRootmuxEnetPreClkPll2Pfd0 = 3U, /*!< Ethernet Pre clock from PLL2 PFD0.*/
423 ccmRootmuxEnetPreClkPll2Pfd2 = 4U, /*!< Ethernet Pre clock from PLL2 PFD2.*/
424 ccmRootmuxEnetPreClkPll3Pfd2 = 5U, /*!< Ethernet Pre clock from PLL3 PFD2.*/
425 };
426
427 /*! @brief Root clock select enumeration for qspi2_clk_sel. */
428 enum _ccm_rootmux_qspi2_clk_sel
429 {
430 ccmRootmuxQspi2ClkPll2Pfd0 = 0U, /*!< QSPI2 Clock from PLL2 PFD0.*/
431 ccmRootmuxQspi2ClkPll2 = 1U, /*!< QSPI2 Clock from PLL2.*/
432 ccmRootmuxQspi2ClkPll3SwClk = 2U, /*!< QSPI2 Clock from PLL3 SW Clock.*/
433 ccmRootmuxQspi2ClkPll2Pfd2 = 3U, /*!< QSPI2 Clock from PLL2 PFD2.*/
434 ccmRootmuxQspi2ClkPll3Pfd3 = 4U, /*!< QSPI2 Clock from PLL3 PFD3.*/
435 };
436
437 /*! @brief Root clock select enumeration for display_clk_sel. */
438 enum _ccm_rootmux_display_clk_sel
439 {
440 ccmRootmuxDisplayClkPll2 = 0U, /*!< Display Clock from PLL2.*/
441 ccmRootmuxDisplayClkPll2Pfd2 = 1U, /*!< Display Clock from PLL2 PFD2.*/
442 ccmRootmuxDisplayClkPll3SwClk = 2U, /*!< Display Clock from PLL3 SW Clock.*/
443 ccmRootmuxDisplayClkPll3Pfd1 = 3U, /*!< Display Clock from PLL3 PFD1.*/
444 };
445
446 /*! @brief Root clock select enumeration for csi_clk_sel. */
447 enum _ccm_rootmux_csi_clk_sel
448 {
449 ccmRootmuxCsiClkOSC24m = 0U, /*!< CSI Clock from OSC 24M.*/
450 ccmRootmuxCsiClkPll2Pfd2 = 1U, /*!< CSI Clock from PLL2 PFD2.*/
451 ccmRootmuxCsiClkPll3SwClkDiv2 = 2U, /*!< CSI Clock from PLL3 SW clock divided by 2.*/
452 ccmRootmuxCsiClkPll3Pfd1 = 3U, /*!< CSI Clock from PLL3 PFD1.*/
453 };
454
455 /*! @brief Root clock select enumeration for can_clk_sel. */
456 enum _ccm_rootmux_can_clk_sel
457 {
458 ccmRootmuxCanClkPll3SwClkDiv8 = 0U, /*!< CAN Clock from PLL3 SW clock divided by 8.*/
459 ccmRootmuxCanClkOsc24m = 1U, /*!< CAN Clock from OSC 24M.*/
460 ccmRootmuxCanClkPll3SwClkDiv6 = 2U, /*!< CAN Clock from PLL3 SW clock divided by 6.*/
461 ccmRootmuxCanClkDisableFlexcanClk = 3U, /*!< Disable FlexCAN clock.*/
462 };
463
464 /*! @brief Root clock select enumeration for ecspi_clk_sel. */
465 enum _ccm_rootmux_ecspi_clk_sel
466 {
467 ccmRootmuxEcspiClkPll3SwClkDiv8 = 0U, /*!< ecSPI Clock from PLL3 SW clock divided by 8.*/
468 ccmRootmuxEcspiClkOsc24m = 1U, /*!< ecSPI Clock from OSC 24M.*/
469 };
470
471 /*! @brief Root clock select enumeration for uart_clk_sel. */
472 enum _ccm_rootmux_uart_clk_sel
473 {
474 ccmRootmuxUartClkPll3SwClkDiv6 = 0U, /*!< UART Clock from PLL3 SW clock divided by 6.*/
475 ccmRootmuxUartClkOsc24m = 1U, /*!< UART Clock from OSC 24M.*/
476 };
477
478 /*!
479 * @brief Root control names for root divider setting.
480 *
481 * These constants define the root control names for root divider setting.\n
482 * - 0:7: REG offset to CCM_BASE in bytes.
483 * - 8:15: Root divider setting bit field shift.
484 * - 16:31: Root divider setting bit field width.
485 */
486 enum _ccm_root_div_control
487 {
488 ccmRootArmPodf = CCM_TUPLE(CACRR, CCM_CACRR_arm_podf_SHIFT, CCM_CACRR_arm_podf_MASK), /*!< ARM Clock post divider control names.*/
489 ccmRootFabricMmdcPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_fabric_mmdc_podf_SHIFT, CCM_CBCDR_fabric_mmdc_podf_MASK), /*!< Fabric MMDC Clock post divider control names.*/
490 ccmRootPeriph2Clk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph2_clk2_podf_SHIFT, CCM_CBCDR_periph2_clk2_podf_MASK), /*!< Peripheral2 Clock2 post divider control names.*/
491 ccmRootOcramPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ocram_podf_SHIFT, CCM_CBCDR_ocram_podf_MASK), /*!< OCRAM Clock post divider control names.*/
492 ccmRootAhbPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ahb_podf_SHIFT, CCM_CBCDR_ahb_podf_MASK), /*!< AHB Clock post divider control names.*/
493 ccmRootPeriphClk2Podf = CCM_TUPLE(CBCDR, CCM_CBCDR_periph_clk2_podf_SHIFT, CCM_CBCDR_periph_clk2_podf_MASK), /*!< Peripheral Clock2 post divider control names.*/
494 ccmRootPerclkPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_perclk_podf_SHIFT, CCM_CSCMR1_perclk_podf_MASK), /*!< Pre Clock post divider control names.*/
495 ccmRootIpgPodf = CCM_TUPLE(CBCDR, CCM_CBCDR_ipg_podf_SHIFT, CCM_CBCDR_ipg_podf_MASK), /*!< IPG Clock post divider control names.*/
496 ccmRootUsdhc1Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc1_podf_SHIFT, CCM_CSCDR1_usdhc1_podf_MASK), /*!< USDHC1 Clock post divider control names.*/
497 ccmRootUsdhc2Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc2_podf_SHIFT, CCM_CSCDR1_usdhc2_podf_MASK), /*!< USDHC2 Clock post divider control names.*/
498 ccmRootUsdhc3Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc3_podf_SHIFT, CCM_CSCDR1_usdhc3_podf_MASK), /*!< USDHC3 Clock post divider control names.*/
499 ccmRootUsdhc4Podf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_usdhc4_podf_SHIFT, CCM_CSCDR1_usdhc4_podf_MASK), /*!< USDHC4 Clock post divider control names.*/
500 ccmRootAclkEimSlowPodf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_aclk_eim_slow_podf_SHIFT, CCM_CSCMR1_aclk_eim_slow_podf_MASK), /*!< ACLK EIM SLOW Clock post divider control names.*/
501 ccmRootGpuAxiPodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_axi_podf_SHIFT, CCM_CBCMR_gpu_axi_podf_MASK), /*!< GPU AXI Clock post divider control names.*/
502 ccmRootGpuCorePodf = CCM_TUPLE(CBCMR, CCM_CBCMR_gpu_core_podf_SHIFT, CCM_CBCMR_gpu_core_podf_MASK), /*!< GPU Core Clock post divider control names.*/
503 ccmRootVidClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_vid_clk_podf_SHIFT, CCM_CSCMR2_vid_clk_podf_MASK), /*!< VID Clock post divider control names.*/
504 ccmRootEsaiClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_podf_SHIFT, CCM_CS1CDR_esai_clk_podf_MASK), /*!< ESAI Clock pre divider control names.*/
505 ccmRootEsaiClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_esai_clk_pred_SHIFT, CCM_CS1CDR_esai_clk_pred_MASK), /*!< ESAI Clock post divider control names.*/
506 ccmRootAudioClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_podf_SHIFT, CCM_CDCDR_audio_clk_podf_MASK), /*!< AUDIO Clock post divider control names.*/
507 ccmRootAudioClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_audio_clk_pred_SHIFT, CCM_CDCDR_audio_clk_pred_MASK), /*!< AUDIO Clock pre divider control names.*/
508 ccmRootSpdif0ClkPodf = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_podf_SHIFT, CCM_CDCDR_spdif0_clk_podf_MASK), /*!< SPDIF0 Clock post divider control names.*/
509 ccmRootSpdif0ClkPred = CCM_TUPLE(CDCDR, CCM_CDCDR_spdif0_clk_pred_SHIFT, CCM_CDCDR_spdif0_clk_pred_MASK), /*!< SPDIF0 Clock pre divider control names.*/
510 ccmRootSsi1ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_podf_SHIFT, CCM_CS1CDR_ssi1_clk_podf_MASK), /*!< SSI1 Clock post divider control names.*/
511 ccmRootSsi1ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi1_clk_pred_SHIFT, CCM_CS1CDR_ssi1_clk_pred_MASK), /*!< SSI1 Clock pre divider control names.*/
512 ccmRootSsi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_podf_SHIFT, CCM_CS2CDR_ssi2_clk_podf_MASK), /*!< SSI2 Clock post divider control names.*/
513 ccmRootSsi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_ssi2_clk_pred_SHIFT, CCM_CS2CDR_ssi2_clk_pred_MASK), /*!< SSI2 Clock pre divider control names.*/
514 ccmRootSsi3ClkPodf = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_podf_SHIFT, CCM_CS1CDR_ssi3_clk_podf_MASK), /*!< SSI3 Clock post divider control names.*/
515 ccmRootSsi3ClkPred = CCM_TUPLE(CS1CDR, CCM_CS1CDR_ssi3_clk_pred_SHIFT, CCM_CS1CDR_ssi3_clk_pred_MASK), /*!< SSI3 Clock pre divider control names.*/
516 ccmRootLcdif2Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_lcdif2_podf_SHIFT, CCM_CSCMR1_lcdif2_podf_MASK), /*!< LCDIF2 Clock post divider control names.*/
517 ccmRootLcdif2Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif2_pred_SHIFT, CCM_CSCDR2_lcdif2_pred_MASK), /*!< LCDIF2 Clock pre divider control names.*/
518 ccmRootLdbDi1Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di1_div_SHIFT, CCM_CSCMR2_ldb_di1_div_MASK), /*!< LDB DI1 Clock divider control names.*/
519 ccmRootLdbDi0Div = CCM_TUPLE(CSCMR2, CCM_CSCMR2_ldb_di0_div_SHIFT, CCM_CSCMR2_ldb_di0_div_MASK), /*!< LCDIDI0 Clock divider control names.*/
520 ccmRootLcdif1Podf = CCM_TUPLE(CBCMR, CCM_CBCMR_lcdif1_podf_SHIFT, CCM_CBCMR_lcdif1_podf_MASK), /*!< LCDIF1 Clock post divider control names.*/
521 ccmRootLcdif1Pred = CCM_TUPLE(CSCDR2, CCM_CSCDR2_lcdif1_pred_SHIFT, CCM_CSCDR2_lcdif1_pred_MASK), /*!< LCDIF1 Clock pre divider control names.*/
522 ccmRootM4Podf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_m4_podf_SHIFT, CCM_CHSCCDR_m4_podf_MASK), /*!< M4 Clock post divider control names.*/
523 ccmRootEnetPodf = CCM_TUPLE(CHSCCDR, CCM_CHSCCDR_enet_podf_SHIFT, CCM_CHSCCDR_enet_podf_MASK), /*!< Ethernet Clock post divider control names.*/
524 ccmRootQspi1Podf = CCM_TUPLE(CSCMR1, CCM_CSCMR1_qspi1_podf_SHIFT, CCM_CSCMR1_qspi1_podf_MASK), /*!< QSPI1 Clock post divider control names.*/
525 ccmRootQspi2ClkPodf = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_podf_SHIFT, CCM_CS2CDR_qspi2_clk_podf_MASK), /*!< QSPI2 Clock post divider control names.*/
526 ccmRootQspi2ClkPred = CCM_TUPLE(CS2CDR, CCM_CS2CDR_qspi2_clk_pred_SHIFT, CCM_CS2CDR_qspi2_clk_pred_MASK), /*!< QSPI2 Clock pre divider control names.*/
527 ccmRootDisplayPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_display_podf_SHIFT, CCM_CSCDR3_display_podf_MASK), /*!< Display Clock post divider control names.*/
528 ccmRootCsiPodf = CCM_TUPLE(CSCDR3, CCM_CSCDR3_csi_podf_SHIFT, CCM_CSCDR3_csi_podf_MASK), /*!< CSI Clock post divider control names.*/
529 ccmRootCanClkPodf = CCM_TUPLE(CSCMR2, CCM_CSCMR2_can_clk_podf_SHIFT, CCM_CSCMR2_can_clk_podf_MASK), /*!< CAN Clock post divider control names.*/
530 ccmRootEcspiClkPodf = CCM_TUPLE(CSCDR2, CCM_CSCDR2_ecspi_clk_podf_SHIFT, CCM_CSCDR2_ecspi_clk_podf_MASK), /*!< ECSPI Clock post divider control names.*/
531 ccmRootUartClkPodf = CCM_TUPLE(CSCDR1, CCM_CSCDR1_uart_clk_podf_SHIFT, CCM_CSCDR1_uart_clk_podf_MASK) /*!< UART Clock post divider control names.*/
532 };
533
534 /*!
535 * @brief CCM CCGR gate control for each module independently.
536 *
537 * These constants define the ccm ccgr clock gate for each module.\n
538 * - 0:7: REG offset to CCM_BASE in bytes.
539 * - 8:15: Root divider setting bit field shift.
540 * - 16:31: Root divider setting bit field width.
541 */
542 enum _ccm_ccgr_gate
543 {
544 ccmCcgrGateAipsTz1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG0_SHIFT, CCM_CCGR0_CG0_MASK), /*!< AipsTz1 Clock Gate.*/
545 ccmCcgrGateAipsTz2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG1_SHIFT, CCM_CCGR0_CG1_MASK), /*!< AipsTz2 Clock Gate.*/
546 ccmCcgrGateApbhdmaHclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG2_SHIFT, CCM_CCGR0_CG2_MASK), /*!< ApbhdmaH Clock Gate.*/
547 ccmCcgrGateAsrcClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG3_SHIFT, CCM_CCGR0_CG3_MASK), /*!< Asrc Clock Gate.*/
548 ccmCcgrGateCaamSecureMemClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG4_SHIFT, CCM_CCGR0_CG4_MASK), /*!< CaamSecureMem Clock Gate.*/
549 ccmCcgrGateCaamWrapperAclk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG5_SHIFT, CCM_CCGR0_CG5_MASK), /*!< CaamWrapperA Clock Gate.*/
550 ccmCcgrGateCaamWrapperIpg = CCM_TUPLE(CCGR0, CCM_CCGR0_CG6_SHIFT, CCM_CCGR0_CG6_MASK), /*!< CaamWrapperIpg Clock Gate.*/
551 ccmCcgrGateCan1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG7_SHIFT, CCM_CCGR0_CG7_MASK), /*!< Can1 Clock Gate.*/
552 ccmCcgrGateCan1SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG8_SHIFT, CCM_CCGR0_CG8_MASK), /*!< Can1 Serial Clock Gate.*/
553 ccmCcgrGateCan2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG9_SHIFT, CCM_CCGR0_CG9_MASK), /*!< Can2 Clock Gate.*/
554 ccmCcgrGateCan2SerialClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG10_SHIFT, CCM_CCGR0_CG10_MASK), /*!< Can2 Serial Clock Gate.*/
555 ccmCcgrGateArmDbgClk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG11_SHIFT, CCM_CCGR0_CG11_MASK), /*!< Arm Debug Clock Gate.*/
556 ccmCcgrGateDcic1Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG12_SHIFT, CCM_CCGR0_CG12_MASK), /*!< Dcic1 Clock Gate.*/
557 ccmCcgrGateDcic2Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG13_SHIFT, CCM_CCGR0_CG13_MASK), /*!< Dcic2 Clock Gate.*/
558 ccmCcgrGateAipsTz3Clk = CCM_TUPLE(CCGR0, CCM_CCGR0_CG15_SHIFT, CCM_CCGR0_CG15_MASK), /*!< AipsTz3 Clock Gate.*/
559 ccmCcgrGateEcspi1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG0_SHIFT, CCM_CCGR1_CG0_MASK), /*!< Ecspi1 Clock Gate.*/
560 ccmCcgrGateEcspi2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG1_SHIFT, CCM_CCGR1_CG1_MASK), /*!< Ecspi2 Clock Gate.*/
561 ccmCcgrGateEcspi3Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG2_SHIFT, CCM_CCGR1_CG2_MASK), /*!< Ecspi3 Clock Gate.*/
562 ccmCcgrGateEcspi4Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG3_SHIFT, CCM_CCGR1_CG3_MASK), /*!< Ecspi4 Clock Gate.*/
563 ccmCcgrGateEcspi5Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG4_SHIFT, CCM_CCGR1_CG4_MASK), /*!< Ecspi5 Clock Gate.*/
564 ccmCcgrGateEpit1Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG6_SHIFT, CCM_CCGR1_CG6_MASK), /*!< Epit1 Clock Gate.*/
565 ccmCcgrGateEpit2Clk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG7_SHIFT, CCM_CCGR1_CG7_MASK), /*!< Epit2 Clock Gate.*/
566 ccmCcgrGateEsaiClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG8_SHIFT, CCM_CCGR1_CG8_MASK), /*!< Esai Clock Gate.*/
567 ccmCcgrGateWakeupClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG9_SHIFT, CCM_CCGR1_CG9_MASK), /*!< Wakeup Clock Gate.*/
568 ccmCcgrGateGptClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG10_SHIFT, CCM_CCGR1_CG10_MASK), /*!< Gpt Clock Gate.*/
569 ccmCcgrGateGptSerialClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG11_SHIFT, CCM_CCGR1_CG11_MASK), /*!< Gpt Serial Clock Gate.*/
570 ccmCcgrGateGpuClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG13_SHIFT, CCM_CCGR1_CG13_MASK), /*!< Gpu Clock Gate.*/
571 ccmCcgrGateOcramSClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG14_SHIFT, CCM_CCGR1_CG14_MASK), /*!< OcramS Clock Gate.*/
572 ccmCcgrGateCanfdClk = CCM_TUPLE(CCGR1, CCM_CCGR1_CG15_SHIFT, CCM_CCGR1_CG15_MASK), /*!< Canfd Clock Gate.*/
573 ccmCcgrGateCsiClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG1_SHIFT, CCM_CCGR2_CG1_MASK), /*!< Csi Clock Gate.*/
574 ccmCcgrGateI2c1Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG3_SHIFT, CCM_CCGR2_CG3_MASK), /*!< I2c1 Serial Clock Gate.*/
575 ccmCcgrGateI2c2Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG4_SHIFT, CCM_CCGR2_CG4_MASK), /*!< I2c2 Serial Clock Gate.*/
576 ccmCcgrGateI2c3Serialclk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG5_SHIFT, CCM_CCGR2_CG5_MASK), /*!< I2c3 Serial Clock Gate.*/
577 ccmCcgrGateIimClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG6_SHIFT, CCM_CCGR2_CG6_MASK), /*!< Iim Clock Gate.*/
578 ccmCcgrGateIomuxIptClkIo = CCM_TUPLE(CCGR2, CCM_CCGR2_CG7_SHIFT, CCM_CCGR2_CG7_MASK), /*!< Iomux Ipt Clock Gate.*/
579 ccmCcgrGateIpmux1Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG8_SHIFT, CCM_CCGR2_CG8_MASK), /*!< Ipmux1 Clock Gate.*/
580 ccmCcgrGateIpmux2Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG9_SHIFT, CCM_CCGR2_CG9_MASK), /*!< Ipmux2 Clock Gate.*/
581 ccmCcgrGateIpmux3Clk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG10_SHIFT, CCM_CCGR2_CG10_MASK), /*!< Ipmux3 Clock Gate.*/
582 ccmCcgrGateIpsyncIp2apbtTasc1 = CCM_TUPLE(CCGR2, CCM_CCGR2_CG11_SHIFT, CCM_CCGR2_CG11_MASK), /*!< IpsyncIp2apbtTasc1 Clock Gate.*/
583 ccmCcgrGateLcdClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG14_SHIFT, CCM_CCGR2_CG14_MASK), /*!< Lcd Clock Gate.*/
584 ccmCcgrGatePxpClk = CCM_TUPLE(CCGR2, CCM_CCGR2_CG15_SHIFT, CCM_CCGR2_CG15_MASK), /*!< Pxp Clock Gate.*/
585 ccmCcgrGateM4Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG1_SHIFT, CCM_CCGR3_CG1_MASK), /*!< M4 Clock Gate.*/
586 ccmCcgrGateEnetClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG2_SHIFT, CCM_CCGR3_CG2_MASK), /*!< Enet Clock Gate.*/
587 ccmCcgrGateDispAxiClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG3_SHIFT, CCM_CCGR3_CG3_MASK), /*!< DispAxi Clock Gate.*/
588 ccmCcgrGateLcdif2PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG4_SHIFT, CCM_CCGR3_CG4_MASK), /*!< Lcdif2Pix Clock Gate.*/
589 ccmCcgrGateLcdif1PixClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG5_SHIFT, CCM_CCGR3_CG5_MASK), /*!< Lcdif1Pix Clock Gate.*/
590 ccmCcgrGateLdbDi0Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG6_SHIFT, CCM_CCGR3_CG6_MASK), /*!< LdbDi0 Clock Gate.*/
591 ccmCcgrGateQspi1Clk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG7_SHIFT, CCM_CCGR3_CG7_MASK), /*!< Qspi1 Clock Gate.*/
592 ccmCcgrGateMlbClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG9_SHIFT, CCM_CCGR3_CG9_MASK), /*!< Mlb Clock Gate.*/
593 ccmCcgrGateMmdcCoreAclkFastP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG10_SHIFT, CCM_CCGR3_CG10_MASK), /*!< Mmdc Core Aclk FastP0 Clock Gate.*/
594 ccmCcgrGateMmdcCoreIpgClkP0 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG12_SHIFT, CCM_CCGR3_CG12_MASK), /*!< Mmdc Core Ipg Clk P0 Clock Gate.*/
595 ccmCcgrGateMmdcCoreIpgClkP1 = CCM_TUPLE(CCGR3, CCM_CCGR3_CG13_SHIFT, CCM_CCGR3_CG13_MASK), /*!< Mmdc Core Ipg Clk P1 Clock Gate.*/
596 ccmCcgrGateOcramClk = CCM_TUPLE(CCGR3, CCM_CCGR3_CG14_SHIFT, CCM_CCGR3_CG14_MASK), /*!< Ocram Clock Gate.*/
597 ccmCcgrGatePcieRoot = CCM_TUPLE(CCGR4, CCM_CCGR4_CG0_SHIFT, CCM_CCGR4_CG0_MASK), /*!< Pcie Clock Gate.*/
598 ccmCcgrGateQspi2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG5_SHIFT, CCM_CCGR4_CG5_MASK), /*!< Qspi2 Clock Gate.*/
599 ccmCcgrGatePl301Mx6qper1Bch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG6_SHIFT, CCM_CCGR4_CG6_MASK), /*!< Pl301Mx6qper1Bch Clock Gate.*/
600 ccmCcgrGatePl301Mx6qper2Main = CCM_TUPLE(CCGR4, CCM_CCGR4_CG7_SHIFT, CCM_CCGR4_CG7_MASK), /*!< Pl301Mx6qper2Main Clock Gate.*/
601 ccmCcgrGatePwm1Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG8_SHIFT, CCM_CCGR4_CG8_MASK), /*!< Pwm1 Clock Gate.*/
602 ccmCcgrGatePwm2Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG9_SHIFT, CCM_CCGR4_CG9_MASK), /*!< Pwm2 Clock Gate.*/
603 ccmCcgrGatePwm3Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG10_SHIFT, CCM_CCGR4_CG10_MASK), /*!< Pwm3 Clock Gate.*/
604 ccmCcgrGatePwm4Clk = CCM_TUPLE(CCGR4, CCM_CCGR4_CG11_SHIFT, CCM_CCGR4_CG11_MASK), /*!< Pwm4 Clock Gate.*/
605 ccmCcgrGateRawnandUBchInptApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG12_SHIFT, CCM_CCGR4_CG12_MASK), /*!< RawnandUBchInptApb Clock Gate.*/
606 ccmCcgrGateRawnandUGpmiBch = CCM_TUPLE(CCGR4, CCM_CCGR4_CG13_SHIFT, CCM_CCGR4_CG13_MASK), /*!< RawnandUGpmiBch Clock Gate.*/
607 ccmCcgrGateRawnandUGpmiGpmiIo = CCM_TUPLE(CCGR4, CCM_CCGR4_CG14_SHIFT, CCM_CCGR4_CG14_MASK), /*!< RawnandUGpmiGpmiIo Clock Gate.*/
608 ccmCcgrGateRawnandUGpmiInpApb = CCM_TUPLE(CCGR4, CCM_CCGR4_CG15_SHIFT, CCM_CCGR4_CG15_MASK), /*!< RawnandUGpmiInpApb Clock Gate.*/
609 ccmCcgrGateRomClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG0_SHIFT, CCM_CCGR5_CG0_MASK), /*!< Rom Clock Gate.*/
610 ccmCcgrGateSdmaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG3_SHIFT, CCM_CCGR5_CG3_MASK), /*!< Sdma Clock Gate.*/
611 ccmCcgrGateSpbaClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG6_SHIFT, CCM_CCGR5_CG6_MASK), /*!< Spba Clock Gate.*/
612 ccmCcgrGateSpdifAudioClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG7_SHIFT, CCM_CCGR5_CG7_MASK), /*!< SpdifAudio Clock Gate.*/
613 ccmCcgrGateSsi1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG9_SHIFT, CCM_CCGR5_CG9_MASK), /*!< Ssi1 Clock Gate.*/
614 ccmCcgrGateSsi2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG10_SHIFT, CCM_CCGR5_CG10_MASK), /*!< Ssi2 Clock Gate.*/
615 ccmCcgrGateSsi3Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG11_SHIFT, CCM_CCGR5_CG11_MASK), /*!< Ssi3 Clock Gate.*/
616 ccmCcgrGateUartClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG12_SHIFT, CCM_CCGR5_CG12_MASK), /*!< Uart Clock Gate.*/
617 ccmCcgrGateUartSerialClk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG13_SHIFT, CCM_CCGR5_CG13_MASK), /*!< Uart Serial Clock Gate.*/
618 ccmCcgrGateSai1Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG14_SHIFT, CCM_CCGR5_CG14_MASK), /*!< Sai1 Clock Gate.*/
619 ccmCcgrGateSai2Clk = CCM_TUPLE(CCGR5, CCM_CCGR5_CG15_SHIFT, CCM_CCGR5_CG15_MASK), /*!< Sai2 Clock Gate.*/
620 ccmCcgrGateUsboh3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG0_SHIFT, CCM_CCGR6_CG0_MASK), /*!< Usboh3 Clock Gate.*/
621 ccmCcgrGateUsdhc1Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG1_SHIFT, CCM_CCGR6_CG1_MASK), /*!< Usdhc1 Clock Gate.*/
622 ccmCcgrGateUsdhc2Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG2_SHIFT, CCM_CCGR6_CG2_MASK), /*!< Usdhc2 Clock Gate.*/
623 ccmCcgrGateUsdhc3Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG3_SHIFT, CCM_CCGR6_CG3_MASK), /*!< Usdhc3 Clock Gate.*/
624 ccmCcgrGateUsdhc4Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG4_SHIFT, CCM_CCGR6_CG4_MASK), /*!< Usdhc4 Clock Gate.*/
625 ccmCcgrGateEimSlowClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG5_SHIFT, CCM_CCGR6_CG5_MASK), /*!< EimSlow Clock Gate.*/
626 ccmCcgrGatePwm8Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG8_SHIFT, CCM_CCGR6_CG8_MASK), /*!< Pwm8 Clock Gate.*/
627 ccmCcgrGateVadcClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG10_SHIFT, CCM_CCGR6_CG10_MASK), /*!< Vadc Clock Gate.*/
628 ccmCcgrGateGisClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG11_SHIFT, CCM_CCGR6_CG11_MASK), /*!< Gis Clock Gate.*/
629 ccmCcgrGateI2c4SerialClk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG12_SHIFT, CCM_CCGR6_CG12_MASK), /*!< I2c4 Serial Clock Gate.*/
630 ccmCcgrGatePwm5Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG13_SHIFT, CCM_CCGR6_CG13_MASK), /*!< Pwm5 Clock Gate.*/
631 ccmCcgrGatePwm6Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG14_SHIFT, CCM_CCGR6_CG14_MASK), /*!< Pwm6 Clock Gate.*/
632 ccmCcgrGatePwm7Clk = CCM_TUPLE(CCGR6, CCM_CCGR6_CG15_SHIFT, CCM_CCGR6_CG15_MASK), /*!< Pwm7 Clock Gate.*/
633 };
634
635 /*! @brief CCM gate control value. */
636 enum _ccm_gate_value
637 {
638 ccmClockNotNeeded = 0U, /*!< Clock always disabled.*/
639 ccmClockNeededRun = 1U, /*!< Clock enabled when CPU is running.*/
640 ccmClockNeededAll = 3U /*!< Clock always enabled.*/
641 };
642
643 /*! @brief CCM override clock enable signal from module. */
644 enum _ccm_overrided_enable_signal
645 {
646 ccmOverridedSignalFromGpt = 1U << 5, /*!< Override clock enable signal from GPT.*/
647 ccmOverridedSignalFromEpit = 1U << 6, /*!< Override clock enable signal from EPIT.*/
648 ccmOverridedSignalFromUsdhc = 1U << 7, /*!< Override clock enable signal from USDHC.*/
649 ccmOverridedSignalFromGpu = 1U << 10, /*!< Override clock enable signal from GPU.*/
650 ccmOverridedSignalFromCan2Cpi = 1U << 28, /*!< Override clock enable signal from CAN2.*/
651 ccmOverridedSignalFromCan1Cpi = 1U << 30 /*!< Override clock enable signal from CAN1.*/
652 };
653
654 /*******************************************************************************
655 * API
656 ******************************************************************************/
657
658 #if defined(__cplusplus)
659 extern "C" {
660 #endif
661
662 /*!
663 * @name CCM Root Clock Setting
664 * @{
665 */
666
667 /*!
668 * @brief Set clock root mux.
669 * User maybe need to set more than one mux node according to the clock tree
670 * description on the reference manual.
671 *
672 * @param base CCM base pointer.
673 * @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration).
674 * @param mux Root mux value (see @ref _ccm_rootmux_xxx enumeration).
675 */
CCM_SetRootMux(CCM_Type * base,uint32_t ccmRootClk,uint32_t mux)676 static inline void CCM_SetRootMux(CCM_Type * base, uint32_t ccmRootClk, uint32_t mux)
677 {
678 CCM_TUPLE_REG(base, ccmRootClk) = (CCM_TUPLE_REG(base, ccmRootClk) & (~CCM_TUPLE_MASK(ccmRootClk))) |
679 (((uint32_t)((mux) << CCM_TUPLE_SHIFT(ccmRootClk))) & CCM_TUPLE_MASK(ccmRootClk));
680 }
681
682 /*!
683 * @brief Get clock root mux.
684 * In order to get the clock source of root, user maybe need to get more than one
685 * node's mux value to obtain the final clock source of root.
686 *
687 * @param base CCM base pointer.
688 * @param ccmRootClk Root clock control (see @ref _ccm_root_clock_control enumeration).
689 * @return Root mux value (see @ref _ccm_rootmux_xxx enumeration).
690 */
CCM_GetRootMux(CCM_Type * base,uint32_t ccmRootClk)691 static inline uint32_t CCM_GetRootMux(CCM_Type * base, uint32_t ccmRootClk)
692 {
693 return (CCM_TUPLE_REG(base, ccmRootClk) & CCM_TUPLE_MASK(ccmRootClk)) >> CCM_TUPLE_SHIFT(ccmRootClk);
694 }
695
696 /*!
697 * @brief Set root clock divider.
698 * User should set the dividers carefully according to the clock tree on
699 * the reference manual. Take care of that the setting of one divider value
700 * may affect several clock root.
701 *
702 * @param base CCM base pointer.
703 * @param ccmRootDiv Root divider control (see @ref _ccm_root_div_control enumeration)
704 * @param div Divider value (divider = div + 1).
705 */
CCM_SetRootDivider(CCM_Type * base,uint32_t ccmRootDiv,uint32_t div)706 static inline void CCM_SetRootDivider(CCM_Type * base, uint32_t ccmRootDiv, uint32_t div)
707 {
708 CCM_TUPLE_REG(base, ccmRootDiv) = (CCM_TUPLE_REG(base, ccmRootDiv) & (~CCM_TUPLE_MASK(ccmRootDiv))) |
709 (((uint32_t)((div) << CCM_TUPLE_SHIFT(ccmRootDiv))) & CCM_TUPLE_MASK(ccmRootDiv));
710 }
711
712 /*!
713 * @brief Get root clock divider.
714 * In order to get divider value of clock root, user should get specific
715 * divider value according to the clock tree description on reference manual.
716 * Then calculate the root clock with those divider value.
717 *
718 * @param base CCM base pointer.
719 * @param ccmRootDiv Root control (see @ref _ccm_root_div_control enumeration).
720 * @param div Pointer to divider value store address.
721 * @return Root divider value.
722 */
CCM_GetRootDivider(CCM_Type * base,uint32_t ccmRootDiv)723 static inline uint32_t CCM_GetRootDivider(CCM_Type * base, uint32_t ccmRootDiv)
724 {
725 return (CCM_TUPLE_REG(base, ccmRootDiv) & CCM_TUPLE_MASK(ccmRootDiv)) >> CCM_TUPLE_SHIFT(ccmRootDiv);
726 }
727
728 /*!
729 * @brief Set handshake mask of MMDC module.
730 * During divider ratio mmdc_axi_podf change or sync mux periph2_clk_sel
731 * change (but not jtag) or SRC request during warm reset, mask handshake with mmdc module.
732 *
733 * @param base CCM base pointer.
734 * @param mask True: mask handshake with MMDC; False: allow handshake with MMDC.
735 */
736 void CCM_SetMmdcHandshakeMask(CCM_Type * base, bool mask);
737
738 /*@}*/
739
740 /*!
741 * @name CCM Gate Control
742 * @{
743 */
744
745 /*!
746 * @brief Set CCGR gate control for each module
747 * User should set specific gate for each module according to the description
748 * of the table of system clocks, gating and override in CCM chapter of
749 * reference manual. Take care of that one module may need to set more than
750 * one clock gate.
751 *
752 * @param base CCM base pointer.
753 * @param ccmGate Gate control for each module (see @ref _ccm_ccgr_gate enumeration).
754 * @param control Gate control value (see @ref _ccm_gate_value).
755 */
CCM_ControlGate(CCM_Type * base,uint32_t ccmGate,uint32_t control)756 static inline void CCM_ControlGate(CCM_Type * base, uint32_t ccmGate, uint32_t control)
757 {
758 CCM_TUPLE_REG(base, ccmGate) = (CCM_TUPLE_REG(base, ccmGate) & (~CCM_TUPLE_MASK(ccmGate))) |
759 (((uint32_t)((control) << CCM_TUPLE_SHIFT(ccmGate))) & CCM_TUPLE_MASK(ccmGate));
760 }
761
762 /*!
763 * @brief Set override or do not override clock enable signal from module.
764 * This is applicable only for modules whose clock enable signals are used.
765 *
766 * @param base CCM base pointer.
767 * @param signal Overrided enable signal from module (see @ref _ccm_overrided_enable_signal enumeration).
768 * @param control Override / Do not override clock enable signal from module.
769 * - true: override clock enable signal.
770 * - false: Do not override clock enable signal.
771 */
772 void CCM_SetClockEnableSignalOverrided(CCM_Type * base, uint32_t signal, bool control);
773
774 /*@}*/
775
776 #if defined(__cplusplus)
777 }
778 #endif
779
780 /*! @}*/
781
782 #endif /* __CCM_IMX6SX_H__ */
783 /*******************************************************************************
784 * EOF
785 ******************************************************************************/
786
