1 /* 2 * NOTE: File generated by lpc_cfg_utils.py 3 * from LPC55S36JHI48/signal_configuration.xml 4 * 5 * Copyright 2022 NXP 6 * SPDX-License-Identifier: Apache-2.0 7 */ 8 9 #ifndef _ZEPHYR_DTS_BINDING_LPC55S36JHI48_ 10 #define _ZEPHYR_DTS_BINDING_LPC55S36JHI48_ 11 12 #define IOCON_MUX(offset, type, mux) \ 13 (((offset & 0xFFF) << 20) | \ 14 (((type) & 0x3) << 18) | \ 15 (((mux) & 0xF) << 0)) 16 17 #define IOCON_TYPE_D 0x0 18 #define IOCON_TYPE_I 0x1 19 #define IOCON_TYPE_A 0x2 20 21 #define ADC0_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 22 #define ADC0_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 23 #define ADC0_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 24 #define ADC0_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 25 #define ADC1_TRIG0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 26 #define ADC1_TRIG1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 27 #define ADC1_TRIG2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 28 #define ADC1_TRIG3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 29 #define CTIMER0_MATCH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 3) /* PIO0_0 */ 30 #define DMA0_TRIG00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 31 #define DMA0_TRIG010_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 32 #define DMA0_TRIG011_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 33 #define DMA0_TRIG012_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 34 #define DMA0_TRIG013_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 35 #define DMA0_TRIG014_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 36 #define DMA0_TRIG015_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 37 #define DMA0_TRIG016_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 38 #define DMA0_TRIG017_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 39 #define DMA0_TRIG018_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 40 #define DMA0_TRIG019_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 41 #define DMA0_TRIG01_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 42 #define DMA0_TRIG020_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 43 #define DMA0_TRIG021_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 44 #define DMA0_TRIG022_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 45 #define DMA0_TRIG023_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 46 #define DMA0_TRIG024_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 47 #define DMA0_TRIG025_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 48 #define DMA0_TRIG026_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 49 #define DMA0_TRIG027_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 50 #define DMA0_TRIG028_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 51 #define DMA0_TRIG029_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 52 #define DMA0_TRIG02_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 53 #define DMA0_TRIG030_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 54 #define DMA0_TRIG031_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 55 #define DMA0_TRIG032_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 56 #define DMA0_TRIG033_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 57 #define DMA0_TRIG034_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 58 #define DMA0_TRIG035_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 59 #define DMA0_TRIG036_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 60 #define DMA0_TRIG037_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 61 #define DMA0_TRIG038_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 62 #define DMA0_TRIG039_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 63 #define DMA0_TRIG03_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 64 #define DMA0_TRIG040_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 65 #define DMA0_TRIG041_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 66 #define DMA0_TRIG042_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 67 #define DMA0_TRIG043_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 68 #define DMA0_TRIG044_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 69 #define DMA0_TRIG045_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 70 #define DMA0_TRIG046_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 71 #define DMA0_TRIG047_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 72 #define DMA0_TRIG048_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 73 #define DMA0_TRIG049_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 74 #define DMA0_TRIG04_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 75 #define DMA0_TRIG050_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 76 #define DMA0_TRIG051_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 77 #define DMA0_TRIG05_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 78 #define DMA0_TRIG06_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 79 #define DMA0_TRIG07_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 80 #define DMA0_TRIG08_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 81 #define DMA0_TRIG09_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 82 #define DMA1_TRIG10_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 83 #define DMA1_TRIG11_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 84 #define DMA1_TRIG12_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 85 #define DMA1_TRIG13_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 86 #define DMA1_TRIG14_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 87 #define DMA1_TRIG15_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 88 #define DMA1_TRIG16_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 89 #define DMA1_TRIG17_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 90 #define DMA1_TRIG18_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 91 #define DMA1_TRIG19_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 92 #define DMIC0_DATA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 5) /* PIO0_0 */ 93 #define ENC0_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 94 #define ENC0_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 95 #define ENC1_PHASEA_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 96 #define ENC1_PHASEB_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 97 #define EXTTRIG_IN8_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 98 #define FC3_SCK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 2) /* PIO0_0 */ 99 #define GPIO_PIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 100 #define PINT_PINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 101 #define PINT_PINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 102 #define PINT_PINT2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 103 #define PINT_PINT3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 104 #define PINT_PINT4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 105 #define PINT_PINT5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 106 #define PINT_PINT6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 107 #define PINT_PINT7_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 108 #define PIO0_0_PIO0_0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 109 #define PMC_ACMP_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 0) /* PIO0_0 */ 110 #define PWM0_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 111 #define PWM0_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 112 #define PWM0_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 113 #define PWM0_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 114 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 115 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 116 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 117 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 118 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 119 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 120 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 121 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 122 #define PWM1_B2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 11) /* PIO0_0 */ 123 #define PWM1_EXTA0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 124 #define PWM1_EXTA1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 125 #define PWM1_EXTA2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 126 #define PWM1_EXTA3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 127 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 128 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 129 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 130 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 131 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 132 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 133 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 134 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 13) /* PIO0_0 */ 135 #define SCT0_IN0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 136 #define SCT0_IN1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 137 #define SCT0_IN2_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 138 #define SCT0_IN3_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 139 #define SCT0_IN4_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 140 #define SCT0_IN5_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 141 #define SCT0_IN6_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 4) /* PIO0_0 */ 142 #define SECGPIO_SECPIO00_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ 143 #define SECPINT_SECPINT0_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ 144 #define SECPINT_SECPINT1_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 10) /* PIO0_0 */ 145 #define SWCLK_PIO0_0 IOCON_MUX(0, IOCON_TYPE_A, 9) /* PIO0_0 */ 146 #define ADC0_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 147 #define ADC0_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 148 #define ADC0_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 149 #define ADC0_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 150 #define ADC1_CH2B_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 151 #define ADC1_TRIG0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 152 #define ADC1_TRIG1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 153 #define ADC1_TRIG2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 154 #define ADC1_TRIG3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 155 #define AOI0_OUT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 12) /* PIO0_1 */ 156 #define CMP0_OUT_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 7) /* PIO0_1 */ 157 #define CTIMER0_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 158 #define CTIMER0_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 159 #define CTIMER0_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 160 #define CTIMER0_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 161 #define CTIMER1_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 162 #define CTIMER1_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 163 #define CTIMER1_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 164 #define CTIMER1_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 165 #define CTIMER2_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 166 #define CTIMER2_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 167 #define CTIMER2_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 168 #define CTIMER2_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 169 #define CTIMER3_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 170 #define CTIMER3_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 171 #define CTIMER3_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 172 #define CTIMER3_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 173 #define CTIMER4_CAPTURE0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 174 #define CTIMER4_CAPTURE1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 175 #define CTIMER4_CAPTURE2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 176 #define CTIMER4_CAPTURE3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 177 #define CT_INP0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 3) /* PIO0_1 */ 178 #define DMA0_TRIG00_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 179 #define DMA0_TRIG010_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 180 #define DMA0_TRIG011_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 181 #define DMA0_TRIG012_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 182 #define DMA0_TRIG013_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 183 #define DMA0_TRIG014_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 184 #define DMA0_TRIG015_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 185 #define DMA0_TRIG016_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 186 #define DMA0_TRIG017_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 187 #define DMA0_TRIG018_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 188 #define DMA0_TRIG019_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 189 #define DMA0_TRIG01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 190 #define DMA0_TRIG020_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 191 #define DMA0_TRIG021_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 192 #define DMA0_TRIG022_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 193 #define DMA0_TRIG023_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 194 #define DMA0_TRIG024_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 195 #define DMA0_TRIG025_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 196 #define DMA0_TRIG026_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 197 #define DMA0_TRIG027_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 198 #define DMA0_TRIG028_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 199 #define DMA0_TRIG029_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 200 #define DMA0_TRIG02_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 201 #define DMA0_TRIG030_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 202 #define DMA0_TRIG031_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 203 #define DMA0_TRIG032_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 204 #define DMA0_TRIG033_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 205 #define DMA0_TRIG034_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 206 #define DMA0_TRIG035_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 207 #define DMA0_TRIG036_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 208 #define DMA0_TRIG037_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 209 #define DMA0_TRIG038_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 210 #define DMA0_TRIG039_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 211 #define DMA0_TRIG03_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 212 #define DMA0_TRIG040_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 213 #define DMA0_TRIG041_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 214 #define DMA0_TRIG042_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 215 #define DMA0_TRIG043_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 216 #define DMA0_TRIG044_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 217 #define DMA0_TRIG045_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 218 #define DMA0_TRIG046_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 219 #define DMA0_TRIG047_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 220 #define DMA0_TRIG048_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 221 #define DMA0_TRIG049_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 222 #define DMA0_TRIG04_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 223 #define DMA0_TRIG050_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 224 #define DMA0_TRIG051_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 225 #define DMA0_TRIG05_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 226 #define DMA0_TRIG06_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 227 #define DMA0_TRIG07_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 228 #define DMA0_TRIG08_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 229 #define DMA0_TRIG09_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 230 #define DMA1_TRIG10_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 231 #define DMA1_TRIG11_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 232 #define DMA1_TRIG12_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 233 #define DMA1_TRIG13_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 234 #define DMA1_TRIG14_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 235 #define DMA1_TRIG15_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 236 #define DMA1_TRIG16_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 237 #define DMA1_TRIG17_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 238 #define DMA1_TRIG18_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 239 #define DMA1_TRIG19_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 240 #define DMIC0_CLK0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 5) /* PIO0_1 */ 241 #define FC3_CTS_SDA_SSEL0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 2) /* PIO0_1 */ 242 #define GPIO_PIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 243 #define PINT_PINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 244 #define PINT_PINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 245 #define PINT_PINT2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 246 #define PINT_PINT3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 247 #define PINT_PINT4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 248 #define PINT_PINT5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 249 #define PINT_PINT6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 250 #define PINT_PINT7_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 251 #define PIO0_1_PIO0_1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 0) /* PIO0_1 */ 252 #define SCT0_IN0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 253 #define SCT0_IN1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 254 #define SCT0_IN2_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 255 #define SCT0_IN3_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 256 #define SCT0_IN4_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 257 #define SCT0_IN5_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 258 #define SCT0_IN6_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 4) /* PIO0_1 */ 259 #define SECGPIO_SECPIO01_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ 260 #define SECPINT_SECPINT0_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ 261 #define SECPINT_SECPINT1_PIO0_1 IOCON_MUX(1, IOCON_TYPE_D, 10) /* PIO0_1 */ 262 #define ADC0_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 263 #define ADC0_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 264 #define ADC0_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 265 #define ADC0_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 266 #define ADC1_TRIG0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 267 #define ADC1_TRIG1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 268 #define ADC1_TRIG2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 269 #define ADC1_TRIG3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 270 #define AOI0_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ 271 #define AOI1_TRIGOUT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 12) /* PIO0_2 */ 272 #define CTIMER0_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 273 #define CTIMER0_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 274 #define CTIMER0_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 275 #define CTIMER0_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 276 #define CTIMER1_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 277 #define CTIMER1_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 278 #define CTIMER1_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 279 #define CTIMER1_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 280 #define CTIMER2_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 281 #define CTIMER2_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 282 #define CTIMER2_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 283 #define CTIMER2_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 284 #define CTIMER3_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 285 #define CTIMER3_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 286 #define CTIMER3_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 287 #define CTIMER3_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 288 #define CTIMER4_CAPTURE0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 289 #define CTIMER4_CAPTURE1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 290 #define CTIMER4_CAPTURE2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 291 #define CTIMER4_CAPTURE3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 292 #define CT_INP1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 2) /* PIO0_2 */ 293 #define DMA0_TRIG00_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 294 #define DMA0_TRIG010_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 295 #define DMA0_TRIG011_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 296 #define DMA0_TRIG012_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 297 #define DMA0_TRIG013_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 298 #define DMA0_TRIG014_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 299 #define DMA0_TRIG015_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 300 #define DMA0_TRIG016_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 301 #define DMA0_TRIG017_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 302 #define DMA0_TRIG018_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 303 #define DMA0_TRIG019_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 304 #define DMA0_TRIG01_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 305 #define DMA0_TRIG020_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 306 #define DMA0_TRIG021_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 307 #define DMA0_TRIG022_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 308 #define DMA0_TRIG023_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 309 #define DMA0_TRIG024_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 310 #define DMA0_TRIG025_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 311 #define DMA0_TRIG026_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 312 #define DMA0_TRIG027_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 313 #define DMA0_TRIG028_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 314 #define DMA0_TRIG029_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 315 #define DMA0_TRIG02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 316 #define DMA0_TRIG030_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 317 #define DMA0_TRIG031_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 318 #define DMA0_TRIG032_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 319 #define DMA0_TRIG033_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 320 #define DMA0_TRIG034_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 321 #define DMA0_TRIG035_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 322 #define DMA0_TRIG036_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 323 #define DMA0_TRIG037_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 324 #define DMA0_TRIG038_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 325 #define DMA0_TRIG039_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 326 #define DMA0_TRIG03_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 327 #define DMA0_TRIG040_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 328 #define DMA0_TRIG041_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 329 #define DMA0_TRIG042_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 330 #define DMA0_TRIG043_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 331 #define DMA0_TRIG044_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 332 #define DMA0_TRIG045_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 333 #define DMA0_TRIG046_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 334 #define DMA0_TRIG047_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 335 #define DMA0_TRIG048_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 336 #define DMA0_TRIG049_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 337 #define DMA0_TRIG04_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 338 #define DMA0_TRIG050_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 339 #define DMA0_TRIG051_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 340 #define DMA0_TRIG05_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 341 #define DMA0_TRIG06_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 342 #define DMA0_TRIG07_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 343 #define DMA0_TRIG08_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 344 #define DMA0_TRIG09_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 345 #define DMA1_TRIG10_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 346 #define DMA1_TRIG11_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 347 #define DMA1_TRIG12_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 348 #define DMA1_TRIG13_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 349 #define DMA1_TRIG14_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 350 #define DMA1_TRIG15_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 351 #define DMA1_TRIG16_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 352 #define DMA1_TRIG17_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 353 #define DMA1_TRIG18_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 354 #define DMA1_TRIG19_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 355 #define ENC0_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 356 #define ENC0_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 357 #define ENC1_PHASEA_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 358 #define ENC1_PHASEB_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 359 #define EXTTRIG_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 360 #define FC3_TXD_SCL_MISO_WS_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 1) /* PIO0_2 */ 361 #define FLEXSPI0_DATA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 5) /* PIO0_2 */ 362 #define GPIO_PIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 363 #define PINT_PINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 364 #define PINT_PINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 365 #define PINT_PINT2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 366 #define PINT_PINT3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 367 #define PINT_PINT4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 368 #define PINT_PINT5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 369 #define PINT_PINT6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 370 #define PINT_PINT7_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 371 #define PIO0_2_PIO0_2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 0) /* PIO0_2 */ 372 #define PWM0_A2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 11) /* PIO0_2 */ 373 #define PWM0_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 374 #define PWM0_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 375 #define PWM0_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 376 #define PWM0_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 377 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 378 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 379 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 380 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 381 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 382 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 383 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 384 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 385 #define PWM1_EXTA0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 386 #define PWM1_EXTA1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 387 #define PWM1_EXTA2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 388 #define PWM1_EXTA3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 389 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 390 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 391 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 392 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 393 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 394 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 395 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 396 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 13) /* PIO0_2 */ 397 #define SCT0_IN0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 398 #define SCT0_IN1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 399 #define SCT0_IN2_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 400 #define SCT0_IN3_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 401 #define SCT0_IN4_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 402 #define SCT0_IN5_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 403 #define SCT0_IN6_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 4) /* PIO0_2 */ 404 #define SCT0_OUT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 3) /* PIO0_2 */ 405 #define SECGPIO_SECPIO02_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ 406 #define SECPINT_SECPINT0_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ 407 #define SECPINT_SECPINT1_PIO0_2 IOCON_MUX(2, IOCON_TYPE_D, 10) /* PIO0_2 */ 408 #define ADC0_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 409 #define ADC0_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 410 #define ADC0_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 411 #define ADC0_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 412 #define ADC1_TRIG0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 413 #define ADC1_TRIG1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 414 #define ADC1_TRIG2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 415 #define ADC1_TRIG3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 416 #define CTIMER0_MATCH1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 2) /* PIO0_3 */ 417 #define DMA0_TRIG00_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 418 #define DMA0_TRIG010_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 419 #define DMA0_TRIG011_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 420 #define DMA0_TRIG012_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 421 #define DMA0_TRIG013_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 422 #define DMA0_TRIG014_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 423 #define DMA0_TRIG015_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 424 #define DMA0_TRIG016_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 425 #define DMA0_TRIG017_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 426 #define DMA0_TRIG018_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 427 #define DMA0_TRIG019_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 428 #define DMA0_TRIG01_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 429 #define DMA0_TRIG020_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 430 #define DMA0_TRIG021_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 431 #define DMA0_TRIG022_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 432 #define DMA0_TRIG023_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 433 #define DMA0_TRIG024_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 434 #define DMA0_TRIG025_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 435 #define DMA0_TRIG026_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 436 #define DMA0_TRIG027_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 437 #define DMA0_TRIG028_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 438 #define DMA0_TRIG029_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 439 #define DMA0_TRIG02_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 440 #define DMA0_TRIG030_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 441 #define DMA0_TRIG031_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 442 #define DMA0_TRIG032_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 443 #define DMA0_TRIG033_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 444 #define DMA0_TRIG034_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 445 #define DMA0_TRIG035_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 446 #define DMA0_TRIG036_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 447 #define DMA0_TRIG037_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 448 #define DMA0_TRIG038_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 449 #define DMA0_TRIG039_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 450 #define DMA0_TRIG03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 451 #define DMA0_TRIG040_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 452 #define DMA0_TRIG041_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 453 #define DMA0_TRIG042_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 454 #define DMA0_TRIG043_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 455 #define DMA0_TRIG044_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 456 #define DMA0_TRIG045_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 457 #define DMA0_TRIG046_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 458 #define DMA0_TRIG047_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 459 #define DMA0_TRIG048_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 460 #define DMA0_TRIG049_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 461 #define DMA0_TRIG04_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 462 #define DMA0_TRIG050_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 463 #define DMA0_TRIG051_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 464 #define DMA0_TRIG05_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 465 #define DMA0_TRIG06_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 466 #define DMA0_TRIG07_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 467 #define DMA0_TRIG08_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 468 #define DMA0_TRIG09_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 469 #define DMA1_TRIG10_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 470 #define DMA1_TRIG11_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 471 #define DMA1_TRIG12_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 472 #define DMA1_TRIG13_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 473 #define DMA1_TRIG14_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 474 #define DMA1_TRIG15_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 475 #define DMA1_TRIG16_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 476 #define DMA1_TRIG17_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 477 #define DMA1_TRIG18_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 478 #define DMA1_TRIG19_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 479 #define FC3_RXD_SDA_MOSI_DATA_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 1) /* PIO0_3 */ 480 #define FLEXSPI0_DATA2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 5) /* PIO0_3 */ 481 #define GPIO_PIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 482 #define PINT_PINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 483 #define PINT_PINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 484 #define PINT_PINT2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 485 #define PINT_PINT3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 486 #define PINT_PINT4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 487 #define PINT_PINT5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 488 #define PINT_PINT6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 489 #define PINT_PINT7_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 490 #define PIO0_3_PIO0_3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 0) /* PIO0_3 */ 491 #define PWM1_B0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 11) /* PIO0_3 */ 492 #define SCT0_IN0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 493 #define SCT0_IN1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 494 #define SCT0_IN2_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 495 #define SCT0_IN3_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 496 #define SCT0_IN4_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 497 #define SCT0_IN5_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 498 #define SCT0_IN6_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 4) /* PIO0_3 */ 499 #define SCT0_OUT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 3) /* PIO0_3 */ 500 #define SECGPIO_SECPIO03_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ 501 #define SECPINT_SECPINT0_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ 502 #define SECPINT_SECPINT1_PIO0_3 IOCON_MUX(3, IOCON_TYPE_D, 10) /* PIO0_3 */ 503 #define ADC0_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 504 #define ADC0_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 505 #define ADC0_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 506 #define ADC0_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 507 #define ADC1_TRIG0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 508 #define ADC1_TRIG1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 509 #define ADC1_TRIG2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 510 #define ADC1_TRIG3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 511 #define AOI0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 512 #define AOI0_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 513 #define AOI0_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 514 #define AOI0_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 515 #define AOI0_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 516 #define AOI0_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 517 #define AOI0_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 518 #define AOI0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 519 #define AOI0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 520 #define AOI0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 521 #define AOI0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 522 #define AOI0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 523 #define AOI0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 524 #define AOI0_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 525 #define AOI0_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 526 #define AOI0_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 527 #define AOI1_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 528 #define AOI1_IN10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 529 #define AOI1_IN11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 530 #define AOI1_IN12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 531 #define AOI1_IN13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 532 #define AOI1_IN14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 533 #define AOI1_IN15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 534 #define AOI1_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 535 #define AOI1_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 536 #define AOI1_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 537 #define AOI1_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 538 #define AOI1_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 539 #define AOI1_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 540 #define AOI1_IN7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 541 #define AOI1_IN8_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 542 #define AOI1_IN9_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 543 #define CAN0_RD_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 1) /* PIO0_4 */ 544 #define CTIMER0_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 545 #define CTIMER0_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 546 #define CTIMER0_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 547 #define CTIMER0_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 548 #define CTIMER1_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 549 #define CTIMER1_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 550 #define CTIMER1_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 551 #define CTIMER1_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 552 #define CTIMER2_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 553 #define CTIMER2_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 554 #define CTIMER2_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 555 #define CTIMER2_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 556 #define CTIMER3_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 557 #define CTIMER3_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 558 #define CTIMER3_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 559 #define CTIMER3_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 560 #define CTIMER4_CAPTURE0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 561 #define CTIMER4_CAPTURE1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 562 #define CTIMER4_CAPTURE2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 563 #define CTIMER4_CAPTURE3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 564 #define CT_INP12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 3) /* PIO0_4 */ 565 #define DMA0_TRIG00_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 566 #define DMA0_TRIG010_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 567 #define DMA0_TRIG011_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 568 #define DMA0_TRIG012_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 569 #define DMA0_TRIG013_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 570 #define DMA0_TRIG014_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 571 #define DMA0_TRIG015_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 572 #define DMA0_TRIG016_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 573 #define DMA0_TRIG017_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 574 #define DMA0_TRIG018_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 575 #define DMA0_TRIG019_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 576 #define DMA0_TRIG01_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 577 #define DMA0_TRIG020_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 578 #define DMA0_TRIG021_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 579 #define DMA0_TRIG022_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 580 #define DMA0_TRIG023_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 581 #define DMA0_TRIG024_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 582 #define DMA0_TRIG025_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 583 #define DMA0_TRIG026_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 584 #define DMA0_TRIG027_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 585 #define DMA0_TRIG028_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 586 #define DMA0_TRIG029_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 587 #define DMA0_TRIG02_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 588 #define DMA0_TRIG030_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 589 #define DMA0_TRIG031_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 590 #define DMA0_TRIG032_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 591 #define DMA0_TRIG033_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 592 #define DMA0_TRIG034_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 593 #define DMA0_TRIG035_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 594 #define DMA0_TRIG036_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 595 #define DMA0_TRIG037_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 596 #define DMA0_TRIG038_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 597 #define DMA0_TRIG039_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 598 #define DMA0_TRIG03_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 599 #define DMA0_TRIG040_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 600 #define DMA0_TRIG041_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 601 #define DMA0_TRIG042_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 602 #define DMA0_TRIG043_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 603 #define DMA0_TRIG044_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 604 #define DMA0_TRIG045_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 605 #define DMA0_TRIG046_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 606 #define DMA0_TRIG047_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 607 #define DMA0_TRIG048_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 608 #define DMA0_TRIG049_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 609 #define DMA0_TRIG04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 610 #define DMA0_TRIG050_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 611 #define DMA0_TRIG051_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 612 #define DMA0_TRIG05_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 613 #define DMA0_TRIG06_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 614 #define DMA0_TRIG07_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 615 #define DMA0_TRIG08_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 616 #define DMA0_TRIG09_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 617 #define DMA1_TRIG10_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 618 #define DMA1_TRIG11_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 619 #define DMA1_TRIG12_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 620 #define DMA1_TRIG13_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 621 #define DMA1_TRIG14_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 622 #define DMA1_TRIG15_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 623 #define DMA1_TRIG16_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 624 #define DMA1_TRIG17_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 625 #define DMA1_TRIG18_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 626 #define DMA1_TRIG19_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 627 #define ENC0_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 628 #define ENC0_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 629 #define ENC1_PHASEA_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 630 #define ENC1_PHASEB_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 631 #define EXTTRIG_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 632 #define FC3_CTS_SDA_SSEL0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 8) /* PIO0_4 */ 633 #define FC4_SCK_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 2) /* PIO0_4 */ 634 #define FC7_TXD_SCL_MISO_WS_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 9) /* PIO0_4 */ 635 #define FLEXSPI0_DATA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 5) /* PIO0_4 */ 636 #define GPIO_PIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 637 #define PINT_PINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 638 #define PINT_PINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 639 #define PINT_PINT2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 640 #define PINT_PINT3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 641 #define PINT_PINT4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 642 #define PINT_PINT5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 643 #define PINT_PINT6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 644 #define PINT_PINT7_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 645 #define PIO0_4_PIO0_4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 0) /* PIO0_4 */ 646 #define PWM0_B3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 11) /* PIO0_4 */ 647 #define PWM0_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 648 #define PWM0_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 649 #define PWM0_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 650 #define PWM0_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 651 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 652 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 653 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 654 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 655 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 656 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 657 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 658 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 659 #define PWM1_EXTA0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 660 #define PWM1_EXTA1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 661 #define PWM1_EXTA2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 662 #define PWM1_EXTA3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 663 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 664 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 665 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 666 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 667 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 668 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 669 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 670 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 13) /* PIO0_4 */ 671 #define SCT0_IN0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 672 #define SCT0_IN1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 673 #define SCT0_IN2_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 674 #define SCT0_IN3_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 675 #define SCT0_IN4_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 676 #define SCT0_IN5_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 677 #define SCT0_IN6_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 4) /* PIO0_4 */ 678 #define SECGPIO_SECPIO04_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ 679 #define SECPINT_SECPINT0_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ 680 #define SECPINT_SECPINT1_PIO0_4 IOCON_MUX(4, IOCON_TYPE_D, 10) /* PIO0_4 */ 681 #define ADC0_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 682 #define ADC0_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 683 #define ADC0_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 684 #define ADC0_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 685 #define ADC1_TRIG0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 686 #define ADC1_TRIG1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 687 #define ADC1_TRIG2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 688 #define ADC1_TRIG3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 689 #define CAN0_TD_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 1) /* PIO0_5 */ 690 #define CTIMER3_MATCH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 3) /* PIO0_5 */ 691 #define DMA0_TRIG00_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 692 #define DMA0_TRIG010_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 693 #define DMA0_TRIG011_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 694 #define DMA0_TRIG012_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 695 #define DMA0_TRIG013_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 696 #define DMA0_TRIG014_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 697 #define DMA0_TRIG015_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 698 #define DMA0_TRIG016_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 699 #define DMA0_TRIG017_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 700 #define DMA0_TRIG018_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 701 #define DMA0_TRIG019_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 702 #define DMA0_TRIG01_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 703 #define DMA0_TRIG020_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 704 #define DMA0_TRIG021_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 705 #define DMA0_TRIG022_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 706 #define DMA0_TRIG023_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 707 #define DMA0_TRIG024_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 708 #define DMA0_TRIG025_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 709 #define DMA0_TRIG026_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 710 #define DMA0_TRIG027_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 711 #define DMA0_TRIG028_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 712 #define DMA0_TRIG029_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 713 #define DMA0_TRIG02_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 714 #define DMA0_TRIG030_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 715 #define DMA0_TRIG031_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 716 #define DMA0_TRIG032_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 717 #define DMA0_TRIG033_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 718 #define DMA0_TRIG034_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 719 #define DMA0_TRIG035_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 720 #define DMA0_TRIG036_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 721 #define DMA0_TRIG037_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 722 #define DMA0_TRIG038_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 723 #define DMA0_TRIG039_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 724 #define DMA0_TRIG03_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 725 #define DMA0_TRIG040_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 726 #define DMA0_TRIG041_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 727 #define DMA0_TRIG042_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 728 #define DMA0_TRIG043_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 729 #define DMA0_TRIG044_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 730 #define DMA0_TRIG045_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 731 #define DMA0_TRIG046_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 732 #define DMA0_TRIG047_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 733 #define DMA0_TRIG048_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 734 #define DMA0_TRIG049_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 735 #define DMA0_TRIG04_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 736 #define DMA0_TRIG050_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 737 #define DMA0_TRIG051_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 738 #define DMA0_TRIG05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 739 #define DMA0_TRIG06_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 740 #define DMA0_TRIG07_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 741 #define DMA0_TRIG08_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 742 #define DMA0_TRIG09_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 743 #define DMA1_TRIG10_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 744 #define DMA1_TRIG11_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 745 #define DMA1_TRIG12_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 746 #define DMA1_TRIG13_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 747 #define DMA1_TRIG14_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 748 #define DMA1_TRIG15_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 749 #define DMA1_TRIG16_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 750 #define DMA1_TRIG17_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 751 #define DMA1_TRIG18_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 752 #define DMA1_TRIG19_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 753 #define ENC0_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 754 #define ENC0_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 755 #define ENC1_PHASEA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 756 #define ENC1_PHASEB_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 757 #define EXTTRIG_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 758 #define FC3_RTS_SCL_SSEL1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 8) /* PIO0_5 */ 759 #define FC4_RXD_SDA_MOSI_DATA_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 2) /* PIO0_5 */ 760 #define GPIO_PIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 761 #define MCLK_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 9) /* PIO0_5 */ 762 #define PINT_PINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 763 #define PINT_PINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 764 #define PINT_PINT2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 765 #define PINT_PINT3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 766 #define PINT_PINT4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 767 #define PINT_PINT5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 768 #define PINT_PINT6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 769 #define PINT_PINT7_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 770 #define PIO0_5_PIO0_5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 0) /* PIO0_5 */ 771 #define PWM0_A0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 11) /* PIO0_5 */ 772 #define PWM0_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 773 #define PWM0_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 774 #define PWM0_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 775 #define PWM0_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 776 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 777 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 778 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 779 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 780 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 781 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 782 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 783 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 784 #define PWM1_EXTA0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 785 #define PWM1_EXTA1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 786 #define PWM1_EXTA2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 787 #define PWM1_EXTA3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 788 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 789 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 790 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 791 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 792 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 793 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 794 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 795 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 13) /* PIO0_5 */ 796 #define SCT0_IN0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 797 #define SCT0_IN1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 798 #define SCT0_IN2_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 799 #define SCT0_IN3_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 800 #define SCT0_IN4_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 801 #define SCT0_IN5_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 802 #define SCT0_IN6_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 4) /* PIO0_5 */ 803 #define SECGPIO_SECPIO05_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ 804 #define SECPINT_SECPINT0_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ 805 #define SECPINT_SECPINT1_PIO0_5 IOCON_MUX(5, IOCON_TYPE_D, 10) /* PIO0_5 */ 806 #define ADC0_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 807 #define ADC0_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 808 #define ADC0_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 809 #define ADC0_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 810 #define ADC1_TRIG0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 811 #define ADC1_TRIG1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 812 #define ADC1_TRIG2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 813 #define ADC1_TRIG3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 814 #define AOI0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 815 #define AOI0_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 816 #define AOI0_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 817 #define AOI0_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 818 #define AOI0_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 819 #define AOI0_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 820 #define AOI0_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 821 #define AOI0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 822 #define AOI0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 823 #define AOI0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 824 #define AOI0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 825 #define AOI0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 826 #define AOI0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 827 #define AOI0_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 828 #define AOI0_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 829 #define AOI0_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 830 #define AOI1_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 831 #define AOI1_IN10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 832 #define AOI1_IN11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 833 #define AOI1_IN12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 834 #define AOI1_IN13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 835 #define AOI1_IN14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 836 #define AOI1_IN15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 837 #define AOI1_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 838 #define AOI1_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 839 #define AOI1_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 840 #define AOI1_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 841 #define AOI1_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 842 #define AOI1_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 843 #define AOI1_IN7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 844 #define AOI1_IN8_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 845 #define AOI1_IN9_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 846 #define CTIMER0_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 847 #define CTIMER0_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 848 #define CTIMER0_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 849 #define CTIMER0_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 850 #define CTIMER1_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 851 #define CTIMER1_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 852 #define CTIMER1_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 853 #define CTIMER1_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 854 #define CTIMER2_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 855 #define CTIMER2_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 856 #define CTIMER2_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 857 #define CTIMER2_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 858 #define CTIMER3_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 859 #define CTIMER3_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 860 #define CTIMER3_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 861 #define CTIMER3_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 862 #define CTIMER4_CAPTURE0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 863 #define CTIMER4_CAPTURE1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 864 #define CTIMER4_CAPTURE2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 865 #define CTIMER4_CAPTURE3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 866 #define CTIMER4_MATCH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 3) /* PIO0_6 */ 867 #define CT_INP13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 2) /* PIO0_6 */ 868 #define DMA0_TRIG00_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 869 #define DMA0_TRIG010_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 870 #define DMA0_TRIG011_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 871 #define DMA0_TRIG012_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 872 #define DMA0_TRIG013_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 873 #define DMA0_TRIG014_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 874 #define DMA0_TRIG015_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 875 #define DMA0_TRIG016_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 876 #define DMA0_TRIG017_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 877 #define DMA0_TRIG018_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 878 #define DMA0_TRIG019_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 879 #define DMA0_TRIG01_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 880 #define DMA0_TRIG020_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 881 #define DMA0_TRIG021_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 882 #define DMA0_TRIG022_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 883 #define DMA0_TRIG023_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 884 #define DMA0_TRIG024_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 885 #define DMA0_TRIG025_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 886 #define DMA0_TRIG026_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 887 #define DMA0_TRIG027_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 888 #define DMA0_TRIG028_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 889 #define DMA0_TRIG029_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 890 #define DMA0_TRIG02_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 891 #define DMA0_TRIG030_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 892 #define DMA0_TRIG031_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 893 #define DMA0_TRIG032_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 894 #define DMA0_TRIG033_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 895 #define DMA0_TRIG034_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 896 #define DMA0_TRIG035_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 897 #define DMA0_TRIG036_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 898 #define DMA0_TRIG037_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 899 #define DMA0_TRIG038_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 900 #define DMA0_TRIG039_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 901 #define DMA0_TRIG03_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 902 #define DMA0_TRIG040_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 903 #define DMA0_TRIG041_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 904 #define DMA0_TRIG042_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 905 #define DMA0_TRIG043_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 906 #define DMA0_TRIG044_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 907 #define DMA0_TRIG045_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 908 #define DMA0_TRIG046_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 909 #define DMA0_TRIG047_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 910 #define DMA0_TRIG048_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 911 #define DMA0_TRIG049_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 912 #define DMA0_TRIG04_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 913 #define DMA0_TRIG050_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 914 #define DMA0_TRIG051_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 915 #define DMA0_TRIG05_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 916 #define DMA0_TRIG06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 917 #define DMA0_TRIG07_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 918 #define DMA0_TRIG08_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 919 #define DMA0_TRIG09_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 920 #define DMA1_TRIG10_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 921 #define DMA1_TRIG11_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 922 #define DMA1_TRIG12_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 923 #define DMA1_TRIG13_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 924 #define DMA1_TRIG14_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 925 #define DMA1_TRIG15_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 926 #define DMA1_TRIG16_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 927 #define DMA1_TRIG17_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 928 #define DMA1_TRIG18_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 929 #define DMA1_TRIG19_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 930 #define ENC0_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 931 #define ENC0_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 932 #define ENC1_PHASEA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 933 #define ENC1_PHASEB_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 934 #define EXTTRIG_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 935 #define FC3_SCK_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 1) /* PIO0_6 */ 936 #define FC7_RXD_SDA_MOSI_DATA_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 9) /* PIO0_6 */ 937 #define FLEXSPI0_DATA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 5) /* PIO0_6 */ 938 #define GPIO_PIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 939 #define PINT_PINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 940 #define PINT_PINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 941 #define PINT_PINT2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 942 #define PINT_PINT3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 943 #define PINT_PINT4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 944 #define PINT_PINT5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 945 #define PINT_PINT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 946 #define PINT_PINT7_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 947 #define PIO0_6_PIO0_6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 0) /* PIO0_6 */ 948 #define PWM0_B0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 11) /* PIO0_6 */ 949 #define PWM0_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 950 #define PWM0_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 951 #define PWM0_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 952 #define PWM0_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 953 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 954 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 955 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 956 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 957 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 958 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 959 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 960 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 961 #define PWM1_EXTA0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 962 #define PWM1_EXTA1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 963 #define PWM1_EXTA2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 964 #define PWM1_EXTA3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 965 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 966 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 967 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 968 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 969 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 970 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 971 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 972 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 13) /* PIO0_6 */ 973 #define SCT0_IN0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 974 #define SCT0_IN1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 975 #define SCT0_IN2_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 976 #define SCT0_IN3_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 977 #define SCT0_IN4_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 978 #define SCT0_IN5_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 979 #define SCT0_IN6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 4) /* PIO0_6 */ 980 #define SCT0_OUT6_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 8) /* PIO0_6 */ 981 #define SECGPIO_SECPIO06_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ 982 #define SECPINT_SECPINT0_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ 983 #define SECPINT_SECPINT1_PIO0_6 IOCON_MUX(6, IOCON_TYPE_D, 10) /* PIO0_6 */ 984 #define ADC0_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 985 #define ADC0_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 986 #define ADC0_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 987 #define ADC0_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 988 #define ADC1_TRIG0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 989 #define ADC1_TRIG1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 990 #define ADC1_TRIG2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 991 #define ADC1_TRIG3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 992 #define AOI0_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ 993 #define AOI1_TRIGOUT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 12) /* PIO0_7 */ 994 #define DMA0_TRIG00_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 995 #define DMA0_TRIG010_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 996 #define DMA0_TRIG011_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 997 #define DMA0_TRIG012_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 998 #define DMA0_TRIG013_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 999 #define DMA0_TRIG014_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1000 #define DMA0_TRIG015_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1001 #define DMA0_TRIG016_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1002 #define DMA0_TRIG017_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1003 #define DMA0_TRIG018_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1004 #define DMA0_TRIG019_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1005 #define DMA0_TRIG01_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1006 #define DMA0_TRIG020_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1007 #define DMA0_TRIG021_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1008 #define DMA0_TRIG022_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1009 #define DMA0_TRIG023_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1010 #define DMA0_TRIG024_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1011 #define DMA0_TRIG025_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1012 #define DMA0_TRIG026_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1013 #define DMA0_TRIG027_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1014 #define DMA0_TRIG028_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1015 #define DMA0_TRIG029_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1016 #define DMA0_TRIG02_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1017 #define DMA0_TRIG030_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1018 #define DMA0_TRIG031_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1019 #define DMA0_TRIG032_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1020 #define DMA0_TRIG033_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1021 #define DMA0_TRIG034_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1022 #define DMA0_TRIG035_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1023 #define DMA0_TRIG036_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1024 #define DMA0_TRIG037_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1025 #define DMA0_TRIG038_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1026 #define DMA0_TRIG039_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1027 #define DMA0_TRIG03_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1028 #define DMA0_TRIG040_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1029 #define DMA0_TRIG041_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1030 #define DMA0_TRIG042_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1031 #define DMA0_TRIG043_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1032 #define DMA0_TRIG044_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1033 #define DMA0_TRIG045_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1034 #define DMA0_TRIG046_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1035 #define DMA0_TRIG047_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1036 #define DMA0_TRIG048_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1037 #define DMA0_TRIG049_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1038 #define DMA0_TRIG04_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1039 #define DMA0_TRIG050_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1040 #define DMA0_TRIG051_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1041 #define DMA0_TRIG05_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1042 #define DMA0_TRIG06_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1043 #define DMA0_TRIG07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1044 #define DMA0_TRIG08_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1045 #define DMA0_TRIG09_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1046 #define DMA1_TRIG10_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1047 #define DMA1_TRIG11_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1048 #define DMA1_TRIG12_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1049 #define DMA1_TRIG13_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1050 #define DMA1_TRIG14_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1051 #define DMA1_TRIG15_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1052 #define DMA1_TRIG16_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1053 #define DMA1_TRIG17_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1054 #define DMA1_TRIG18_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1055 #define DMA1_TRIG19_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1056 #define DMIC0_CLK0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 5) /* PIO0_7 */ 1057 #define FC1_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 4) /* PIO0_7 */ 1058 #define FC3_RTS_SCL_SSEL1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 1) /* PIO0_7 */ 1059 #define FC5_SCK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 3) /* PIO0_7 */ 1060 #define GPIO_PIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1061 #define HSCMP1_IN0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1062 #define HSCMP2_OUT_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 13) /* PIO0_7 */ 1063 #define MCLK_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 8) /* PIO0_7 */ 1064 #define PINT_PINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1065 #define PINT_PINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1066 #define PINT_PINT2_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1067 #define PINT_PINT3_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1068 #define PINT_PINT4_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1069 #define PINT_PINT5_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1070 #define PINT_PINT6_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1071 #define PINT_PINT7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1072 #define PIO0_7_PIO0_7_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 0) /* PIO0_7 */ 1073 #define PWM0_B0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 11) /* PIO0_7 */ 1074 #define QSPI_CS0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 9) /* PIO0_7 */ 1075 #define SECGPIO_SECPIO07_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ 1076 #define SECPINT_SECPINT0_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ 1077 #define SECPINT_SECPINT1_PIO0_7 IOCON_MUX(7, IOCON_TYPE_A, 10) /* PIO0_7 */ 1078 #define ADC0_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1079 #define ADC0_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1080 #define ADC0_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1081 #define ADC0_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1082 #define ADC1_TRIG0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1083 #define ADC1_TRIG1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1084 #define ADC1_TRIG2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1085 #define ADC1_TRIG3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1086 #define DMA0_TRIG00_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1087 #define DMA0_TRIG010_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1088 #define DMA0_TRIG011_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1089 #define DMA0_TRIG012_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1090 #define DMA0_TRIG013_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1091 #define DMA0_TRIG014_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1092 #define DMA0_TRIG015_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1093 #define DMA0_TRIG016_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1094 #define DMA0_TRIG017_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1095 #define DMA0_TRIG018_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1096 #define DMA0_TRIG019_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1097 #define DMA0_TRIG01_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1098 #define DMA0_TRIG020_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1099 #define DMA0_TRIG021_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1100 #define DMA0_TRIG022_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1101 #define DMA0_TRIG023_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1102 #define DMA0_TRIG024_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1103 #define DMA0_TRIG025_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1104 #define DMA0_TRIG026_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1105 #define DMA0_TRIG027_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1106 #define DMA0_TRIG028_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1107 #define DMA0_TRIG029_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1108 #define DMA0_TRIG02_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1109 #define DMA0_TRIG030_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1110 #define DMA0_TRIG031_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1111 #define DMA0_TRIG032_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1112 #define DMA0_TRIG033_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1113 #define DMA0_TRIG034_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1114 #define DMA0_TRIG035_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1115 #define DMA0_TRIG036_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1116 #define DMA0_TRIG037_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1117 #define DMA0_TRIG038_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1118 #define DMA0_TRIG039_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1119 #define DMA0_TRIG03_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1120 #define DMA0_TRIG040_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1121 #define DMA0_TRIG041_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1122 #define DMA0_TRIG042_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1123 #define DMA0_TRIG043_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1124 #define DMA0_TRIG044_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1125 #define DMA0_TRIG045_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1126 #define DMA0_TRIG046_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1127 #define DMA0_TRIG047_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1128 #define DMA0_TRIG048_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1129 #define DMA0_TRIG049_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1130 #define DMA0_TRIG04_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1131 #define DMA0_TRIG050_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1132 #define DMA0_TRIG051_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1133 #define DMA0_TRIG05_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1134 #define DMA0_TRIG06_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1135 #define DMA0_TRIG07_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1136 #define DMA0_TRIG08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1137 #define DMA0_TRIG09_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1138 #define DMA1_TRIG10_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1139 #define DMA1_TRIG11_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1140 #define DMA1_TRIG12_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1141 #define DMA1_TRIG13_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1142 #define DMA1_TRIG14_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1143 #define DMA1_TRIG15_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1144 #define DMA1_TRIG16_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1145 #define DMA1_TRIG17_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1146 #define DMA1_TRIG18_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1147 #define DMA1_TRIG19_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1148 #define DMIC0_DATA1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 5) /* PIO0_8 */ 1149 #define FC3_SSEL3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 1) /* PIO0_8 */ 1150 #define FC5_RXD_SDA_MOSI_DATA_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 3) /* PIO0_8 */ 1151 #define GPIO_PIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1152 #define OPAMP0_DP0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1153 #define PINT_PINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1154 #define PINT_PINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1155 #define PINT_PINT2_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1156 #define PINT_PINT3_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1157 #define PINT_PINT4_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1158 #define PINT_PINT5_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1159 #define PINT_PINT6_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1160 #define PINT_PINT7_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1161 #define PIO0_8_PIO0_8_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 0) /* PIO0_8 */ 1162 #define SECGPIO_SECPIO08_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ 1163 #define SECPINT_SECPINT0_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ 1164 #define SECPINT_SECPINT1_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 10) /* PIO0_8 */ 1165 #define SWO_PIO0_8 IOCON_MUX(8, IOCON_TYPE_D, 4) /* PIO0_8 */ 1166 #define ADC0_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1167 #define ADC0_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1168 #define ADC0_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1169 #define ADC0_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1170 #define ADC1_TRIG0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1171 #define ADC1_TRIG1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1172 #define ADC1_TRIG2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1173 #define ADC1_TRIG3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1174 #define AOI0_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ 1175 #define AOI1_TRIGOUT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 13) /* PIO0_9 */ 1176 #define DMA0_TRIG00_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1177 #define DMA0_TRIG010_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1178 #define DMA0_TRIG011_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1179 #define DMA0_TRIG012_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1180 #define DMA0_TRIG013_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1181 #define DMA0_TRIG014_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1182 #define DMA0_TRIG015_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1183 #define DMA0_TRIG016_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1184 #define DMA0_TRIG017_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1185 #define DMA0_TRIG018_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1186 #define DMA0_TRIG019_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1187 #define DMA0_TRIG01_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1188 #define DMA0_TRIG020_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1189 #define DMA0_TRIG021_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1190 #define DMA0_TRIG022_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1191 #define DMA0_TRIG023_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1192 #define DMA0_TRIG024_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1193 #define DMA0_TRIG025_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1194 #define DMA0_TRIG026_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1195 #define DMA0_TRIG027_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1196 #define DMA0_TRIG028_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1197 #define DMA0_TRIG029_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1198 #define DMA0_TRIG02_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1199 #define DMA0_TRIG030_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1200 #define DMA0_TRIG031_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1201 #define DMA0_TRIG032_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1202 #define DMA0_TRIG033_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1203 #define DMA0_TRIG034_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1204 #define DMA0_TRIG035_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1205 #define DMA0_TRIG036_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1206 #define DMA0_TRIG037_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1207 #define DMA0_TRIG038_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1208 #define DMA0_TRIG039_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1209 #define DMA0_TRIG03_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1210 #define DMA0_TRIG040_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1211 #define DMA0_TRIG041_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1212 #define DMA0_TRIG042_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1213 #define DMA0_TRIG043_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1214 #define DMA0_TRIG044_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1215 #define DMA0_TRIG045_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1216 #define DMA0_TRIG046_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1217 #define DMA0_TRIG047_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1218 #define DMA0_TRIG048_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1219 #define DMA0_TRIG049_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1220 #define DMA0_TRIG04_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1221 #define DMA0_TRIG050_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1222 #define DMA0_TRIG051_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1223 #define DMA0_TRIG05_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1224 #define DMA0_TRIG06_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1225 #define DMA0_TRIG07_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1226 #define DMA0_TRIG08_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1227 #define DMA0_TRIG09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1228 #define DMA1_TRIG10_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1229 #define DMA1_TRIG11_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1230 #define DMA1_TRIG12_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1231 #define DMA1_TRIG13_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1232 #define DMA1_TRIG14_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1233 #define DMA1_TRIG15_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1234 #define DMA1_TRIG16_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1235 #define DMA1_TRIG17_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1236 #define DMA1_TRIG18_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1237 #define DMA1_TRIG19_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1238 #define FC3_SSEL2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 1) /* PIO0_9 */ 1239 #define FC5_TXD_SCL_MISO_WS_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 3) /* PIO0_9 */ 1240 #define GPIO_PIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1241 #define I3C0_SCL_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 7) /* PIO0_9 */ 1242 #define PINT_PINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1243 #define PINT_PINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1244 #define PINT_PINT2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1245 #define PINT_PINT3_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1246 #define PINT_PINT4_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1247 #define PINT_PINT5_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1248 #define PINT_PINT6_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1249 #define PINT_PINT7_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1250 #define PIO0_9_PIO0_9_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1251 #define PMC_ACMP_IN2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 0) /* PIO0_9 */ 1252 #define PWM1_A2_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 11) /* PIO0_9 */ 1253 #define SECGPIO_SECPIO09_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ 1254 #define SECPINT_SECPINT0_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ 1255 #define SECPINT_SECPINT1_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 10) /* PIO0_9 */ 1256 #define SWDIO_PIO0_9 IOCON_MUX(9, IOCON_TYPE_A, 9) /* PIO0_9 */ 1257 #define ADC0_CH1A_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1258 #define ADC0_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1259 #define ADC0_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1260 #define ADC0_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1261 #define ADC0_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1262 #define ADC1_TRIG0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1263 #define ADC1_TRIG1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1264 #define ADC1_TRIG2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1265 #define ADC1_TRIG3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1266 #define CTIMER0_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1267 #define CTIMER0_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1268 #define CTIMER0_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1269 #define CTIMER0_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1270 #define CTIMER1_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1271 #define CTIMER1_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1272 #define CTIMER1_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1273 #define CTIMER1_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1274 #define CTIMER2_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1275 #define CTIMER2_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1276 #define CTIMER2_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1277 #define CTIMER2_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1278 #define CTIMER2_MATCH0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 3) /* PIO0_10 */ 1279 #define CTIMER3_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1280 #define CTIMER3_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1281 #define CTIMER3_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1282 #define CTIMER3_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1283 #define CTIMER4_CAPTURE0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1284 #define CTIMER4_CAPTURE1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1285 #define CTIMER4_CAPTURE2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1286 #define CTIMER4_CAPTURE3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1287 #define CT_INP10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 2) /* PIO0_10 */ 1288 #define DMA0_TRIG00_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1289 #define DMA0_TRIG010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1290 #define DMA0_TRIG011_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1291 #define DMA0_TRIG012_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1292 #define DMA0_TRIG013_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1293 #define DMA0_TRIG014_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1294 #define DMA0_TRIG015_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1295 #define DMA0_TRIG016_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1296 #define DMA0_TRIG017_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1297 #define DMA0_TRIG018_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1298 #define DMA0_TRIG019_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1299 #define DMA0_TRIG01_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1300 #define DMA0_TRIG020_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1301 #define DMA0_TRIG021_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1302 #define DMA0_TRIG022_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1303 #define DMA0_TRIG023_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1304 #define DMA0_TRIG024_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1305 #define DMA0_TRIG025_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1306 #define DMA0_TRIG026_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1307 #define DMA0_TRIG027_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1308 #define DMA0_TRIG028_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1309 #define DMA0_TRIG029_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1310 #define DMA0_TRIG02_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1311 #define DMA0_TRIG030_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1312 #define DMA0_TRIG031_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1313 #define DMA0_TRIG032_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1314 #define DMA0_TRIG033_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1315 #define DMA0_TRIG034_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1316 #define DMA0_TRIG035_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1317 #define DMA0_TRIG036_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1318 #define DMA0_TRIG037_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1319 #define DMA0_TRIG038_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1320 #define DMA0_TRIG039_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1321 #define DMA0_TRIG03_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1322 #define DMA0_TRIG040_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1323 #define DMA0_TRIG041_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1324 #define DMA0_TRIG042_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1325 #define DMA0_TRIG043_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1326 #define DMA0_TRIG044_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1327 #define DMA0_TRIG045_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1328 #define DMA0_TRIG046_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1329 #define DMA0_TRIG047_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1330 #define DMA0_TRIG048_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1331 #define DMA0_TRIG049_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1332 #define DMA0_TRIG04_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1333 #define DMA0_TRIG050_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1334 #define DMA0_TRIG051_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1335 #define DMA0_TRIG05_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1336 #define DMA0_TRIG06_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1337 #define DMA0_TRIG07_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1338 #define DMA0_TRIG08_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1339 #define DMA0_TRIG09_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1340 #define DMA1_TRIG10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1341 #define DMA1_TRIG11_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1342 #define DMA1_TRIG12_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1343 #define DMA1_TRIG13_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1344 #define DMA1_TRIG14_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1345 #define DMA1_TRIG15_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1346 #define DMA1_TRIG16_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1347 #define DMA1_TRIG17_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1348 #define DMA1_TRIG18_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1349 #define DMA1_TRIG19_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1350 #define FC1_TXD_SCL_MISO_WS_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 4) /* PIO0_10 */ 1351 #define FC6_SCK_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 1) /* PIO0_10 */ 1352 #define GPIO_PIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1353 #define PINT_PINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1354 #define PINT_PINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1355 #define PINT_PINT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1356 #define PINT_PINT3_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1357 #define PINT_PINT4_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1358 #define PINT_PINT5_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1359 #define PINT_PINT6_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1360 #define PINT_PINT7_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1361 #define PIO0_10_PIO0_10_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 0) /* PIO0_10 */ 1362 #define SCT0_OUT2_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 5) /* PIO0_10 */ 1363 #define SECGPIO_SECPIO010_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ 1364 #define SECPINT_SECPINT0_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ 1365 #define SECPINT_SECPINT1_PIO0_10 IOCON_MUX(10, IOCON_TYPE_D, 10) /* PIO0_10 */ 1366 #define ADC0_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1367 #define ADC0_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1368 #define ADC0_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1369 #define ADC0_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1370 #define ADC1_CH2A_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1371 #define ADC1_TRIG0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1372 #define ADC1_TRIG1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1373 #define ADC1_TRIG2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1374 #define ADC1_TRIG3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1375 #define AOI1_OUT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 12) /* PIO0_11 */ 1376 #define CTIMER2_MATCH2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 2) /* PIO0_11 */ 1377 #define DMA0_TRIG00_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1378 #define DMA0_TRIG010_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1379 #define DMA0_TRIG011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1380 #define DMA0_TRIG012_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1381 #define DMA0_TRIG013_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1382 #define DMA0_TRIG014_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1383 #define DMA0_TRIG015_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1384 #define DMA0_TRIG016_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1385 #define DMA0_TRIG017_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1386 #define DMA0_TRIG018_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1387 #define DMA0_TRIG019_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1388 #define DMA0_TRIG01_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1389 #define DMA0_TRIG020_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1390 #define DMA0_TRIG021_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1391 #define DMA0_TRIG022_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1392 #define DMA0_TRIG023_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1393 #define DMA0_TRIG024_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1394 #define DMA0_TRIG025_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1395 #define DMA0_TRIG026_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1396 #define DMA0_TRIG027_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1397 #define DMA0_TRIG028_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1398 #define DMA0_TRIG029_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1399 #define DMA0_TRIG02_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1400 #define DMA0_TRIG030_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1401 #define DMA0_TRIG031_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1402 #define DMA0_TRIG032_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1403 #define DMA0_TRIG033_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1404 #define DMA0_TRIG034_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1405 #define DMA0_TRIG035_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1406 #define DMA0_TRIG036_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1407 #define DMA0_TRIG037_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1408 #define DMA0_TRIG038_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1409 #define DMA0_TRIG039_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1410 #define DMA0_TRIG03_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1411 #define DMA0_TRIG040_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1412 #define DMA0_TRIG041_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1413 #define DMA0_TRIG042_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1414 #define DMA0_TRIG043_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1415 #define DMA0_TRIG044_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1416 #define DMA0_TRIG045_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1417 #define DMA0_TRIG046_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1418 #define DMA0_TRIG047_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1419 #define DMA0_TRIG048_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1420 #define DMA0_TRIG049_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1421 #define DMA0_TRIG04_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1422 #define DMA0_TRIG050_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1423 #define DMA0_TRIG051_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1424 #define DMA0_TRIG05_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1425 #define DMA0_TRIG06_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1426 #define DMA0_TRIG07_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1427 #define DMA0_TRIG08_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1428 #define DMA0_TRIG09_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1429 #define DMA1_TRIG10_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1430 #define DMA1_TRIG11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1431 #define DMA1_TRIG12_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1432 #define DMA1_TRIG13_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1433 #define DMA1_TRIG14_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1434 #define DMA1_TRIG15_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1435 #define DMA1_TRIG16_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1436 #define DMA1_TRIG17_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1437 #define DMA1_TRIG18_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1438 #define DMA1_TRIG19_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1439 #define FC6_RXD_SDA_MOSI_DATA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 1) /* PIO0_11 */ 1440 #define GPIO_PIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1441 #define PINT_PINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1442 #define PINT_PINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1443 #define PINT_PINT2_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1444 #define PINT_PINT3_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1445 #define PINT_PINT4_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1446 #define PINT_PINT5_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1447 #define PINT_PINT6_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1448 #define PINT_PINT7_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1449 #define PIO0_11_PIO0_11_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 0) /* PIO0_11 */ 1450 #define SECGPIO_SECPIO011_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ 1451 #define SECPINT_SECPINT0_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ 1452 #define SECPINT_SECPINT1_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 10) /* PIO0_11 */ 1453 #define SYSCON_FREQMEA_PIO0_11 IOCON_MUX(11, IOCON_TYPE_D, 3) /* PIO0_11 */ 1454 #define ADC0_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1455 #define ADC0_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1456 #define ADC0_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1457 #define ADC0_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1458 #define ADC1_TRIG0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1459 #define ADC1_TRIG1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1460 #define ADC1_TRIG2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1461 #define ADC1_TRIG3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1462 #define AOI0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1463 #define AOI0_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1464 #define AOI0_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1465 #define AOI0_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1466 #define AOI0_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1467 #define AOI0_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1468 #define AOI0_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1469 #define AOI0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1470 #define AOI0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1471 #define AOI0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1472 #define AOI0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1473 #define AOI0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1474 #define AOI0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1475 #define AOI0_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1476 #define AOI0_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1477 #define AOI0_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1478 #define AOI1_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1479 #define AOI1_IN10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1480 #define AOI1_IN11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1481 #define AOI1_IN12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1482 #define AOI1_IN13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1483 #define AOI1_IN14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1484 #define AOI1_IN15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1485 #define AOI1_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1486 #define AOI1_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1487 #define AOI1_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1488 #define AOI1_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1489 #define AOI1_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1490 #define AOI1_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1491 #define AOI1_IN7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1492 #define AOI1_IN8_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1493 #define AOI1_IN9_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1494 #define CTIMER0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1495 #define CTIMER0_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1496 #define CTIMER0_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1497 #define CTIMER0_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1498 #define CTIMER1_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1499 #define CTIMER1_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1500 #define CTIMER1_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1501 #define CTIMER1_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1502 #define CTIMER2_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1503 #define CTIMER2_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1504 #define CTIMER2_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1505 #define CTIMER2_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1506 #define CTIMER3_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1507 #define CTIMER3_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1508 #define CTIMER3_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1509 #define CTIMER3_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1510 #define CTIMER4_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1511 #define CTIMER4_CAPTURE1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1512 #define CTIMER4_CAPTURE2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1513 #define CTIMER4_CAPTURE3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1514 #define CT_INP0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 3) /* PIO0_13 */ 1515 #define DMA0_TRIG00_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1516 #define DMA0_TRIG010_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1517 #define DMA0_TRIG011_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1518 #define DMA0_TRIG012_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1519 #define DMA0_TRIG013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1520 #define DMA0_TRIG014_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1521 #define DMA0_TRIG015_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1522 #define DMA0_TRIG016_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1523 #define DMA0_TRIG017_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1524 #define DMA0_TRIG018_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1525 #define DMA0_TRIG019_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1526 #define DMA0_TRIG01_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1527 #define DMA0_TRIG020_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1528 #define DMA0_TRIG021_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1529 #define DMA0_TRIG022_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1530 #define DMA0_TRIG023_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1531 #define DMA0_TRIG024_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1532 #define DMA0_TRIG025_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1533 #define DMA0_TRIG026_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1534 #define DMA0_TRIG027_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1535 #define DMA0_TRIG028_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1536 #define DMA0_TRIG029_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1537 #define DMA0_TRIG02_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1538 #define DMA0_TRIG030_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1539 #define DMA0_TRIG031_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1540 #define DMA0_TRIG032_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1541 #define DMA0_TRIG033_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1542 #define DMA0_TRIG034_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1543 #define DMA0_TRIG035_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1544 #define DMA0_TRIG036_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1545 #define DMA0_TRIG037_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1546 #define DMA0_TRIG038_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1547 #define DMA0_TRIG039_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1548 #define DMA0_TRIG03_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1549 #define DMA0_TRIG040_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1550 #define DMA0_TRIG041_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1551 #define DMA0_TRIG042_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1552 #define DMA0_TRIG043_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1553 #define DMA0_TRIG044_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1554 #define DMA0_TRIG045_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1555 #define DMA0_TRIG046_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1556 #define DMA0_TRIG047_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1557 #define DMA0_TRIG048_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1558 #define DMA0_TRIG049_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1559 #define DMA0_TRIG04_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1560 #define DMA0_TRIG050_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1561 #define DMA0_TRIG051_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1562 #define DMA0_TRIG05_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1563 #define DMA0_TRIG06_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1564 #define DMA0_TRIG07_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1565 #define DMA0_TRIG08_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1566 #define DMA0_TRIG09_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1567 #define DMA1_TRIG10_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1568 #define DMA1_TRIG11_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1569 #define DMA1_TRIG12_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1570 #define DMA1_TRIG13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1571 #define DMA1_TRIG14_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1572 #define DMA1_TRIG15_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1573 #define DMA1_TRIG16_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1574 #define DMA1_TRIG17_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1575 #define DMA1_TRIG18_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1576 #define DMA1_TRIG19_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1577 #define ENC0_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1578 #define ENC0_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1579 #define ENC1_PHASEA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1580 #define ENC1_PHASEB_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1581 #define EXTTRIG_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1582 #define FC1_CTS_SDA_SSEL0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 1) /* PIO0_13 */ 1583 #define FC1_RXD_SDA_MOSI_DATA_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 5) /* PIO0_13 */ 1584 #define GPIO_PIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1585 #define PINT_PINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1586 #define PINT_PINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1587 #define PINT_PINT2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1588 #define PINT_PINT3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1589 #define PINT_PINT4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1590 #define PINT_PINT5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1591 #define PINT_PINT6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1592 #define PINT_PINT7_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1593 #define PIO0_13_PIO0_13_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 0) /* PIO0_13 */ 1594 #define PWM0_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1595 #define PWM0_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1596 #define PWM0_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1597 #define PWM0_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1598 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1599 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1600 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1601 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1602 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1603 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1604 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1605 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1606 #define PWM1_EXTA0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1607 #define PWM1_EXTA1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1608 #define PWM1_EXTA2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1609 #define PWM1_EXTA3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1610 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1611 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1612 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1613 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1614 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1615 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1616 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1617 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 13) /* PIO0_13 */ 1618 #define SCT0_IN0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1619 #define SCT0_IN1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1620 #define SCT0_IN2_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1621 #define SCT0_IN3_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1622 #define SCT0_IN4_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1623 #define SCT0_IN5_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1624 #define SCT0_IN6_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 4) /* PIO0_13 */ 1625 #define SECGPIO_SECPIO013_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ 1626 #define SECPINT_SECPINT0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ 1627 #define SECPINT_SECPINT1_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 10) /* PIO0_13 */ 1628 #define UTICK0_CAPTURE0_PIO0_13 IOCON_MUX(13, IOCON_TYPE_I, 2) /* PIO0_13 */ 1629 #define ADC0_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1630 #define ADC0_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1631 #define ADC0_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1632 #define ADC0_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1633 #define ADC1_TRIG0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1634 #define ADC1_TRIG1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1635 #define ADC1_TRIG2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1636 #define ADC1_TRIG3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1637 #define AOI0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1638 #define AOI0_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1639 #define AOI0_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1640 #define AOI0_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1641 #define AOI0_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1642 #define AOI0_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1643 #define AOI0_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1644 #define AOI0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1645 #define AOI0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1646 #define AOI0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1647 #define AOI0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1648 #define AOI0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1649 #define AOI0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1650 #define AOI0_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1651 #define AOI0_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1652 #define AOI0_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1653 #define AOI1_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1654 #define AOI1_IN10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1655 #define AOI1_IN11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1656 #define AOI1_IN12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1657 #define AOI1_IN13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1658 #define AOI1_IN14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1659 #define AOI1_IN15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1660 #define AOI1_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1661 #define AOI1_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1662 #define AOI1_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1663 #define AOI1_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1664 #define AOI1_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1665 #define AOI1_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1666 #define AOI1_IN7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1667 #define AOI1_IN8_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1668 #define AOI1_IN9_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1669 #define CTIMER0_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1670 #define CTIMER0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1671 #define CTIMER0_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1672 #define CTIMER0_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1673 #define CTIMER1_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1674 #define CTIMER1_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1675 #define CTIMER1_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1676 #define CTIMER1_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1677 #define CTIMER2_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1678 #define CTIMER2_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1679 #define CTIMER2_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1680 #define CTIMER2_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1681 #define CTIMER3_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1682 #define CTIMER3_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1683 #define CTIMER3_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1684 #define CTIMER3_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1685 #define CTIMER4_CAPTURE0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1686 #define CTIMER4_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1687 #define CTIMER4_CAPTURE2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1688 #define CTIMER4_CAPTURE3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1689 #define CT_INP1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 3) /* PIO0_14 */ 1690 #define DMA0_TRIG00_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1691 #define DMA0_TRIG010_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1692 #define DMA0_TRIG011_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1693 #define DMA0_TRIG012_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1694 #define DMA0_TRIG013_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1695 #define DMA0_TRIG014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1696 #define DMA0_TRIG015_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1697 #define DMA0_TRIG016_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1698 #define DMA0_TRIG017_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1699 #define DMA0_TRIG018_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1700 #define DMA0_TRIG019_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1701 #define DMA0_TRIG01_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1702 #define DMA0_TRIG020_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1703 #define DMA0_TRIG021_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1704 #define DMA0_TRIG022_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1705 #define DMA0_TRIG023_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1706 #define DMA0_TRIG024_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1707 #define DMA0_TRIG025_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1708 #define DMA0_TRIG026_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1709 #define DMA0_TRIG027_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1710 #define DMA0_TRIG028_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1711 #define DMA0_TRIG029_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1712 #define DMA0_TRIG02_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1713 #define DMA0_TRIG030_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1714 #define DMA0_TRIG031_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1715 #define DMA0_TRIG032_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1716 #define DMA0_TRIG033_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1717 #define DMA0_TRIG034_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1718 #define DMA0_TRIG035_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1719 #define DMA0_TRIG036_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1720 #define DMA0_TRIG037_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1721 #define DMA0_TRIG038_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1722 #define DMA0_TRIG039_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1723 #define DMA0_TRIG03_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1724 #define DMA0_TRIG040_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1725 #define DMA0_TRIG041_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1726 #define DMA0_TRIG042_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1727 #define DMA0_TRIG043_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1728 #define DMA0_TRIG044_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1729 #define DMA0_TRIG045_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1730 #define DMA0_TRIG046_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1731 #define DMA0_TRIG047_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1732 #define DMA0_TRIG048_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1733 #define DMA0_TRIG049_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1734 #define DMA0_TRIG04_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1735 #define DMA0_TRIG050_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1736 #define DMA0_TRIG051_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1737 #define DMA0_TRIG05_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1738 #define DMA0_TRIG06_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1739 #define DMA0_TRIG07_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1740 #define DMA0_TRIG08_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1741 #define DMA0_TRIG09_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1742 #define DMA1_TRIG10_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1743 #define DMA1_TRIG11_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1744 #define DMA1_TRIG12_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1745 #define DMA1_TRIG13_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1746 #define DMA1_TRIG14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1747 #define DMA1_TRIG15_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1748 #define DMA1_TRIG16_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1749 #define DMA1_TRIG17_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1750 #define DMA1_TRIG18_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1751 #define DMA1_TRIG19_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1752 #define ENC0_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1753 #define ENC0_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1754 #define ENC1_PHASEA_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1755 #define ENC1_PHASEB_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1756 #define EXTTRIG_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1757 #define FC1_RTS_SCL_SSEL1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 1) /* PIO0_14 */ 1758 #define FC1_TXD_SCL_MISO_WS_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 6) /* PIO0_14 */ 1759 #define GPIO_PIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1760 #define PINT_PINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1761 #define PINT_PINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1762 #define PINT_PINT2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1763 #define PINT_PINT3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1764 #define PINT_PINT4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1765 #define PINT_PINT5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1766 #define PINT_PINT6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1767 #define PINT_PINT7_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1768 #define PIO0_14_PIO0_14_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 0) /* PIO0_14 */ 1769 #define PWM0_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1770 #define PWM0_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1771 #define PWM0_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1772 #define PWM0_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1773 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1774 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1775 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1776 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1777 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1778 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1779 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1780 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1781 #define PWM1_EXTA0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1782 #define PWM1_EXTA1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1783 #define PWM1_EXTA2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1784 #define PWM1_EXTA3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1785 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1786 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1787 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1788 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1789 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1790 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1791 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1792 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 13) /* PIO0_14 */ 1793 #define SCT0_IN0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1794 #define SCT0_IN1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1795 #define SCT0_IN2_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1796 #define SCT0_IN3_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1797 #define SCT0_IN4_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1798 #define SCT0_IN5_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1799 #define SCT0_IN6_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 4) /* PIO0_14 */ 1800 #define SECGPIO_SECPIO014_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ 1801 #define SECPINT_SECPINT0_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ 1802 #define SECPINT_SECPINT1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 10) /* PIO0_14 */ 1803 #define UTICK0_CAPTURE1_PIO0_14 IOCON_MUX(14, IOCON_TYPE_I, 2) /* PIO0_14 */ 1804 #define ADC0_CH3A_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1805 #define ADC0_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1806 #define ADC0_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1807 #define ADC0_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1808 #define ADC0_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1809 #define ADC1_TRIG0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1810 #define ADC1_TRIG1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1811 #define ADC1_TRIG2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1812 #define ADC1_TRIG3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1813 #define CTIMER0_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1814 #define CTIMER0_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1815 #define CTIMER0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1816 #define CTIMER0_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1817 #define CTIMER1_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1818 #define CTIMER1_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1819 #define CTIMER1_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1820 #define CTIMER1_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1821 #define CTIMER2_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1822 #define CTIMER2_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1823 #define CTIMER2_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1824 #define CTIMER2_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1825 #define CTIMER3_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1826 #define CTIMER3_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1827 #define CTIMER3_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1828 #define CTIMER3_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1829 #define CTIMER4_CAPTURE0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1830 #define CTIMER4_CAPTURE1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1831 #define CTIMER4_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1832 #define CTIMER4_CAPTURE3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1833 #define CT_INP16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 3) /* PIO0_15 */ 1834 #define DMA0_TRIG00_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1835 #define DMA0_TRIG010_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1836 #define DMA0_TRIG011_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1837 #define DMA0_TRIG012_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1838 #define DMA0_TRIG013_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1839 #define DMA0_TRIG014_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1840 #define DMA0_TRIG015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1841 #define DMA0_TRIG016_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1842 #define DMA0_TRIG017_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1843 #define DMA0_TRIG018_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1844 #define DMA0_TRIG019_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1845 #define DMA0_TRIG01_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1846 #define DMA0_TRIG020_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1847 #define DMA0_TRIG021_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1848 #define DMA0_TRIG022_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1849 #define DMA0_TRIG023_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1850 #define DMA0_TRIG024_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1851 #define DMA0_TRIG025_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1852 #define DMA0_TRIG026_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1853 #define DMA0_TRIG027_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1854 #define DMA0_TRIG028_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1855 #define DMA0_TRIG029_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1856 #define DMA0_TRIG02_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1857 #define DMA0_TRIG030_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1858 #define DMA0_TRIG031_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1859 #define DMA0_TRIG032_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1860 #define DMA0_TRIG033_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1861 #define DMA0_TRIG034_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1862 #define DMA0_TRIG035_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1863 #define DMA0_TRIG036_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1864 #define DMA0_TRIG037_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1865 #define DMA0_TRIG038_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1866 #define DMA0_TRIG039_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1867 #define DMA0_TRIG03_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1868 #define DMA0_TRIG040_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1869 #define DMA0_TRIG041_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1870 #define DMA0_TRIG042_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1871 #define DMA0_TRIG043_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1872 #define DMA0_TRIG044_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1873 #define DMA0_TRIG045_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1874 #define DMA0_TRIG046_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1875 #define DMA0_TRIG047_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1876 #define DMA0_TRIG048_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1877 #define DMA0_TRIG049_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1878 #define DMA0_TRIG04_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1879 #define DMA0_TRIG050_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1880 #define DMA0_TRIG051_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1881 #define DMA0_TRIG05_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1882 #define DMA0_TRIG06_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1883 #define DMA0_TRIG07_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1884 #define DMA0_TRIG08_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1885 #define DMA0_TRIG09_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1886 #define DMA1_TRIG10_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1887 #define DMA1_TRIG11_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1888 #define DMA1_TRIG12_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1889 #define DMA1_TRIG13_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1890 #define DMA1_TRIG14_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1891 #define DMA1_TRIG15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1892 #define DMA1_TRIG16_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1893 #define DMA1_TRIG17_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1894 #define DMA1_TRIG18_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1895 #define DMA1_TRIG19_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1896 #define FC6_CTS_SDA_SSEL0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 1) /* PIO0_15 */ 1897 #define GPIO_PIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1898 #define PINT_PINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1899 #define PINT_PINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1900 #define PINT_PINT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1901 #define PINT_PINT3_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1902 #define PINT_PINT4_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1903 #define PINT_PINT5_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1904 #define PINT_PINT6_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1905 #define PINT_PINT7_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1906 #define PIO0_15_PIO0_15_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 0) /* PIO0_15 */ 1907 #define SCT0_OUT2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 4) /* PIO0_15 */ 1908 #define SECGPIO_SECPIO015_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ 1909 #define SECPINT_SECPINT0_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ 1910 #define SECPINT_SECPINT1_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 10) /* PIO0_15 */ 1911 #define UTICK0_CAPTURE2_PIO0_15 IOCON_MUX(15, IOCON_TYPE_D, 2) /* PIO0_15 */ 1912 #define ADC0_CH3B_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1913 #define ADC0_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1914 #define ADC0_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1915 #define ADC0_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1916 #define ADC0_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1917 #define ADC1_TRIG0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1918 #define ADC1_TRIG1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1919 #define ADC1_TRIG2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1920 #define ADC1_TRIG3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1921 #define AOI0_OUT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 12) /* PIO0_16 */ 1922 #define CLKOUT_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 2) /* PIO0_16 */ 1923 #define CTIMER0_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1924 #define CTIMER0_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1925 #define CTIMER0_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1926 #define CTIMER0_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1927 #define CTIMER1_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1928 #define CTIMER1_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1929 #define CTIMER1_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1930 #define CTIMER1_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1931 #define CTIMER2_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1932 #define CTIMER2_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1933 #define CTIMER2_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1934 #define CTIMER2_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1935 #define CTIMER3_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1936 #define CTIMER3_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1937 #define CTIMER3_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1938 #define CTIMER3_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1939 #define CTIMER4_CAPTURE0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1940 #define CTIMER4_CAPTURE1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1941 #define CTIMER4_CAPTURE2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1942 #define CTIMER4_CAPTURE3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1943 #define CT_INP4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 3) /* PIO0_16 */ 1944 #define DMA0_TRIG00_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1945 #define DMA0_TRIG010_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1946 #define DMA0_TRIG011_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1947 #define DMA0_TRIG012_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1948 #define DMA0_TRIG013_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1949 #define DMA0_TRIG014_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1950 #define DMA0_TRIG015_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1951 #define DMA0_TRIG016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1952 #define DMA0_TRIG017_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1953 #define DMA0_TRIG018_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1954 #define DMA0_TRIG019_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1955 #define DMA0_TRIG01_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1956 #define DMA0_TRIG020_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1957 #define DMA0_TRIG021_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1958 #define DMA0_TRIG022_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1959 #define DMA0_TRIG023_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1960 #define DMA0_TRIG024_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1961 #define DMA0_TRIG025_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1962 #define DMA0_TRIG026_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1963 #define DMA0_TRIG027_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1964 #define DMA0_TRIG028_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1965 #define DMA0_TRIG029_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1966 #define DMA0_TRIG02_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1967 #define DMA0_TRIG030_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1968 #define DMA0_TRIG031_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1969 #define DMA0_TRIG032_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1970 #define DMA0_TRIG033_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1971 #define DMA0_TRIG034_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1972 #define DMA0_TRIG035_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1973 #define DMA0_TRIG036_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1974 #define DMA0_TRIG037_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1975 #define DMA0_TRIG038_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1976 #define DMA0_TRIG039_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1977 #define DMA0_TRIG03_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1978 #define DMA0_TRIG040_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1979 #define DMA0_TRIG041_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1980 #define DMA0_TRIG042_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1981 #define DMA0_TRIG043_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1982 #define DMA0_TRIG044_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1983 #define DMA0_TRIG045_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1984 #define DMA0_TRIG046_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1985 #define DMA0_TRIG047_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1986 #define DMA0_TRIG048_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1987 #define DMA0_TRIG049_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1988 #define DMA0_TRIG04_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1989 #define DMA0_TRIG050_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1990 #define DMA0_TRIG051_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1991 #define DMA0_TRIG05_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1992 #define DMA0_TRIG06_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1993 #define DMA0_TRIG07_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1994 #define DMA0_TRIG08_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1995 #define DMA0_TRIG09_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1996 #define DMA1_TRIG10_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1997 #define DMA1_TRIG11_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1998 #define DMA1_TRIG12_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 1999 #define DMA1_TRIG13_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2000 #define DMA1_TRIG14_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2001 #define DMA1_TRIG15_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2002 #define DMA1_TRIG16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2003 #define DMA1_TRIG17_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2004 #define DMA1_TRIG18_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2005 #define DMA1_TRIG19_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2006 #define FC4_TXD_SCL_MISO_WS_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 1) /* PIO0_16 */ 2007 #define GPIO_PIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2008 #define PINT_PINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2009 #define PINT_PINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2010 #define PINT_PINT2_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2011 #define PINT_PINT3_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2012 #define PINT_PINT4_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2013 #define PINT_PINT5_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2014 #define PINT_PINT6_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2015 #define PINT_PINT7_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2016 #define PIO0_16_PIO0_16_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 0) /* PIO0_16 */ 2017 #define SECGPIO_SECPIO016_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ 2018 #define SECPINT_SECPINT0_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ 2019 #define SECPINT_SECPINT1_PIO0_16 IOCON_MUX(16, IOCON_TYPE_D, 10) /* PIO0_16 */ 2020 #define ADC0_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2021 #define ADC0_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2022 #define ADC0_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2023 #define ADC0_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2024 #define ADC1_TRIG0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2025 #define ADC1_TRIG1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2026 #define ADC1_TRIG2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2027 #define ADC1_TRIG3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2028 #define AOI0_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ 2029 #define AOI1_TRIGOUT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 12) /* PIO0_17 */ 2030 #define DMA0_TRIG00_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2031 #define DMA0_TRIG010_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2032 #define DMA0_TRIG011_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2033 #define DMA0_TRIG012_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2034 #define DMA0_TRIG013_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2035 #define DMA0_TRIG014_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2036 #define DMA0_TRIG015_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2037 #define DMA0_TRIG016_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2038 #define DMA0_TRIG017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2039 #define DMA0_TRIG018_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2040 #define DMA0_TRIG019_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2041 #define DMA0_TRIG01_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2042 #define DMA0_TRIG020_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2043 #define DMA0_TRIG021_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2044 #define DMA0_TRIG022_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2045 #define DMA0_TRIG023_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2046 #define DMA0_TRIG024_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2047 #define DMA0_TRIG025_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2048 #define DMA0_TRIG026_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2049 #define DMA0_TRIG027_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2050 #define DMA0_TRIG028_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2051 #define DMA0_TRIG029_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2052 #define DMA0_TRIG02_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2053 #define DMA0_TRIG030_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2054 #define DMA0_TRIG031_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2055 #define DMA0_TRIG032_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2056 #define DMA0_TRIG033_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2057 #define DMA0_TRIG034_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2058 #define DMA0_TRIG035_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2059 #define DMA0_TRIG036_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2060 #define DMA0_TRIG037_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2061 #define DMA0_TRIG038_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2062 #define DMA0_TRIG039_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2063 #define DMA0_TRIG03_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2064 #define DMA0_TRIG040_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2065 #define DMA0_TRIG041_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2066 #define DMA0_TRIG042_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2067 #define DMA0_TRIG043_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2068 #define DMA0_TRIG044_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2069 #define DMA0_TRIG045_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2070 #define DMA0_TRIG046_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2071 #define DMA0_TRIG047_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2072 #define DMA0_TRIG048_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2073 #define DMA0_TRIG049_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2074 #define DMA0_TRIG04_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2075 #define DMA0_TRIG050_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2076 #define DMA0_TRIG051_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2077 #define DMA0_TRIG05_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2078 #define DMA0_TRIG06_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2079 #define DMA0_TRIG07_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2080 #define DMA0_TRIG08_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2081 #define DMA0_TRIG09_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2082 #define DMA1_TRIG10_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2083 #define DMA1_TRIG11_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2084 #define DMA1_TRIG12_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2085 #define DMA1_TRIG13_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2086 #define DMA1_TRIG14_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2087 #define DMA1_TRIG15_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2088 #define DMA1_TRIG16_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2089 #define DMA1_TRIG17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2090 #define DMA1_TRIG18_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2091 #define DMA1_TRIG19_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2092 #define FC4_SSEL2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 1) /* PIO0_17 */ 2093 #define FC5_RXD_SDA_MOSI_DATA_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 8) /* PIO0_17 */ 2094 #define GPIO_PIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2095 #define HSCMP1_OUT_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 13) /* PIO0_17 */ 2096 #define HSCMP2_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2097 #define PINT_PINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2098 #define PINT_PINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2099 #define PINT_PINT2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2100 #define PINT_PINT3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2101 #define PINT_PINT4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2102 #define PINT_PINT5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2103 #define PINT_PINT6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2104 #define PINT_PINT7_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2105 #define PIO0_17_PIO0_17_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 0) /* PIO0_17 */ 2106 #define QSPI_SCLK_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 9) /* PIO0_17 */ 2107 #define SCT0_IN0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2108 #define SCT0_IN1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2109 #define SCT0_IN2_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2110 #define SCT0_IN3_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2111 #define SCT0_IN4_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2112 #define SCT0_IN5_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2113 #define SCT0_IN6_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 3) /* PIO0_17 */ 2114 #define SCT0_OUT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 4) /* PIO0_17 */ 2115 #define SECGPIO_SECPIO017_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ 2116 #define SECPINT_SECPINT0_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ 2117 #define SECPINT_SECPINT1_PIO0_17 IOCON_MUX(17, IOCON_TYPE_A, 10) /* PIO0_17 */ 2118 #define ADC0_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2119 #define ADC0_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2120 #define ADC0_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2121 #define ADC0_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2122 #define ADC1_TRIG0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2123 #define ADC1_TRIG1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2124 #define ADC1_TRIG2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2125 #define ADC1_TRIG3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2126 #define AOI0_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ 2127 #define AOI1_TRIGOUT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 13) /* PIO0_18 */ 2128 #define CTIMER1_MATCH0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 3) /* PIO0_18 */ 2129 #define DMA0_TRIG00_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2130 #define DMA0_TRIG010_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2131 #define DMA0_TRIG011_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2132 #define DMA0_TRIG012_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2133 #define DMA0_TRIG013_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2134 #define DMA0_TRIG014_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2135 #define DMA0_TRIG015_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2136 #define DMA0_TRIG016_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2137 #define DMA0_TRIG017_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2138 #define DMA0_TRIG018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2139 #define DMA0_TRIG019_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2140 #define DMA0_TRIG01_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2141 #define DMA0_TRIG020_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2142 #define DMA0_TRIG021_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2143 #define DMA0_TRIG022_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2144 #define DMA0_TRIG023_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2145 #define DMA0_TRIG024_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2146 #define DMA0_TRIG025_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2147 #define DMA0_TRIG026_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2148 #define DMA0_TRIG027_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2149 #define DMA0_TRIG028_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2150 #define DMA0_TRIG029_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2151 #define DMA0_TRIG02_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2152 #define DMA0_TRIG030_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2153 #define DMA0_TRIG031_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2154 #define DMA0_TRIG032_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2155 #define DMA0_TRIG033_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2156 #define DMA0_TRIG034_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2157 #define DMA0_TRIG035_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2158 #define DMA0_TRIG036_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2159 #define DMA0_TRIG037_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2160 #define DMA0_TRIG038_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2161 #define DMA0_TRIG039_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2162 #define DMA0_TRIG03_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2163 #define DMA0_TRIG040_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2164 #define DMA0_TRIG041_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2165 #define DMA0_TRIG042_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2166 #define DMA0_TRIG043_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2167 #define DMA0_TRIG044_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2168 #define DMA0_TRIG045_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2169 #define DMA0_TRIG046_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2170 #define DMA0_TRIG047_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2171 #define DMA0_TRIG048_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2172 #define DMA0_TRIG049_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2173 #define DMA0_TRIG04_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2174 #define DMA0_TRIG050_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2175 #define DMA0_TRIG051_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2176 #define DMA0_TRIG05_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2177 #define DMA0_TRIG06_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2178 #define DMA0_TRIG07_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2179 #define DMA0_TRIG08_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2180 #define DMA0_TRIG09_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2181 #define DMA1_TRIG10_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2182 #define DMA1_TRIG11_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2183 #define DMA1_TRIG12_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2184 #define DMA1_TRIG13_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2185 #define DMA1_TRIG14_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2186 #define DMA1_TRIG15_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2187 #define DMA1_TRIG16_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2188 #define DMA1_TRIG17_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2189 #define DMA1_TRIG18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2190 #define DMA1_TRIG19_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2191 #define FC4_CTS_SDA_SSEL0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 1) /* PIO0_18 */ 2192 #define FC5_RXD_SDA_MOSI_DATA_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 5) /* PIO0_18 */ 2193 #define GPIO_PIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2194 #define PINT_PINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2195 #define PINT_PINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2196 #define PINT_PINT2_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2197 #define PINT_PINT3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2198 #define PINT_PINT4_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2199 #define PINT_PINT5_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2200 #define PINT_PINT6_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2201 #define PINT_PINT7_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2202 #define PIO0_18_PIO0_18_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2203 #define PMC_ACMP_IN3_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 0) /* PIO0_18 */ 2204 #define PWM1_A0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 11) /* PIO0_18 */ 2205 #define QSPI_DIN1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 12) /* PIO0_18 */ 2206 #define SCT0_OUT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 4) /* PIO0_18 */ 2207 #define SECGPIO_SECPIO018_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ 2208 #define SECPINT_SECPINT0_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ 2209 #define SECPINT_SECPINT1_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 10) /* PIO0_18 */ 2210 #define SWO_PIO0_18 IOCON_MUX(18, IOCON_TYPE_A, 8) /* PIO0_18 */ 2211 #define ADC0_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2212 #define ADC0_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2213 #define ADC0_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2214 #define ADC0_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2215 #define ADC1_TRIG0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2216 #define ADC1_TRIG1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2217 #define ADC1_TRIG2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2218 #define ADC1_TRIG3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2219 #define AOI0_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2220 #define AOI0_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2221 #define AOI0_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2222 #define AOI0_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2223 #define AOI0_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2224 #define AOI0_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2225 #define AOI0_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2226 #define AOI0_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2227 #define AOI0_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2228 #define AOI0_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2229 #define AOI0_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2230 #define AOI0_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2231 #define AOI0_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2232 #define AOI0_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2233 #define AOI0_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2234 #define AOI0_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2235 #define AOI0_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ 2236 #define AOI1_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2237 #define AOI1_IN10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2238 #define AOI1_IN11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2239 #define AOI1_IN12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2240 #define AOI1_IN13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2241 #define AOI1_IN14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2242 #define AOI1_IN15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2243 #define AOI1_IN1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2244 #define AOI1_IN2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2245 #define AOI1_IN3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2246 #define AOI1_IN4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2247 #define AOI1_IN5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2248 #define AOI1_IN6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2249 #define AOI1_IN7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2250 #define AOI1_IN8_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2251 #define AOI1_IN9_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2252 #define AOI1_TRIGOUT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 12) /* PIO0_19 */ 2253 #define CTIMER0_MATCH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 3) /* PIO0_19 */ 2254 #define DMA0_TRIG00_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2255 #define DMA0_TRIG010_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2256 #define DMA0_TRIG011_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2257 #define DMA0_TRIG012_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2258 #define DMA0_TRIG013_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2259 #define DMA0_TRIG014_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2260 #define DMA0_TRIG015_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2261 #define DMA0_TRIG016_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2262 #define DMA0_TRIG017_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2263 #define DMA0_TRIG018_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2264 #define DMA0_TRIG019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2265 #define DMA0_TRIG01_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2266 #define DMA0_TRIG020_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2267 #define DMA0_TRIG021_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2268 #define DMA0_TRIG022_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2269 #define DMA0_TRIG023_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2270 #define DMA0_TRIG024_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2271 #define DMA0_TRIG025_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2272 #define DMA0_TRIG026_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2273 #define DMA0_TRIG027_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2274 #define DMA0_TRIG028_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2275 #define DMA0_TRIG029_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2276 #define DMA0_TRIG02_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2277 #define DMA0_TRIG030_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2278 #define DMA0_TRIG031_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2279 #define DMA0_TRIG032_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2280 #define DMA0_TRIG033_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2281 #define DMA0_TRIG034_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2282 #define DMA0_TRIG035_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2283 #define DMA0_TRIG036_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2284 #define DMA0_TRIG037_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2285 #define DMA0_TRIG038_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2286 #define DMA0_TRIG039_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2287 #define DMA0_TRIG03_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2288 #define DMA0_TRIG040_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2289 #define DMA0_TRIG041_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2290 #define DMA0_TRIG042_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2291 #define DMA0_TRIG043_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2292 #define DMA0_TRIG044_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2293 #define DMA0_TRIG045_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2294 #define DMA0_TRIG046_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2295 #define DMA0_TRIG047_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2296 #define DMA0_TRIG048_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2297 #define DMA0_TRIG049_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2298 #define DMA0_TRIG04_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2299 #define DMA0_TRIG050_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2300 #define DMA0_TRIG051_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2301 #define DMA0_TRIG05_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2302 #define DMA0_TRIG06_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2303 #define DMA0_TRIG07_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2304 #define DMA0_TRIG08_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2305 #define DMA0_TRIG09_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2306 #define DMA1_TRIG10_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2307 #define DMA1_TRIG11_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2308 #define DMA1_TRIG12_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2309 #define DMA1_TRIG13_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2310 #define DMA1_TRIG14_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2311 #define DMA1_TRIG15_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2312 #define DMA1_TRIG16_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2313 #define DMA1_TRIG17_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2314 #define DMA1_TRIG18_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2315 #define DMA1_TRIG19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2316 #define ENC0_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2317 #define ENC0_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2318 #define ENC1_PHASEA_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2319 #define ENC1_PHASEB_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2320 #define EXTTRIG_IN0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2321 #define FC4_RTS_SCL_SSEL1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 1) /* PIO0_19 */ 2322 #define FC7_SCK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 9) /* PIO0_19 */ 2323 #define FC7_TXD_SCL_MISO_WS_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 7) /* PIO0_19 */ 2324 #define FLEXSPI0_SCLK_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 5) /* PIO0_19 */ 2325 #define GPIO_PIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2326 #define PINT_PINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2327 #define PINT_PINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2328 #define PINT_PINT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2329 #define PINT_PINT3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2330 #define PINT_PINT4_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2331 #define PINT_PINT5_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2332 #define PINT_PINT6_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2333 #define PINT_PINT7_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2334 #define PIO0_19_PIO0_19_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 0) /* PIO0_19 */ 2335 #define PWM0_B1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 11) /* PIO0_19 */ 2336 #define PWM0_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2337 #define PWM0_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2338 #define PWM0_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2339 #define PWM0_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2340 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2341 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2342 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2343 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2344 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2345 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2346 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2347 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2348 #define PWM1_EXTA0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2349 #define PWM1_EXTA1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2350 #define PWM1_EXTA2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2351 #define PWM1_EXTA3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2352 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2353 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2354 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2355 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2356 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2357 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2358 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2359 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 13) /* PIO0_19 */ 2360 #define SCT0_OUT2_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 4) /* PIO0_19 */ 2361 #define SECGPIO_SECPIO019_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ 2362 #define SECPINT_SECPINT0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ 2363 #define SECPINT_SECPINT1_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 10) /* PIO0_19 */ 2364 #define UTICK0_CAPTURE0_PIO0_19 IOCON_MUX(19, IOCON_TYPE_D, 2) /* PIO0_19 */ 2365 #define ADC0_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2366 #define ADC0_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2367 #define ADC0_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2368 #define ADC0_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2369 #define ADC1_TRIG0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2370 #define ADC1_TRIG1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2371 #define ADC1_TRIG2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2372 #define ADC1_TRIG3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2373 #define CTIMER0_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2374 #define CTIMER0_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2375 #define CTIMER0_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2376 #define CTIMER0_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2377 #define CTIMER1_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2378 #define CTIMER1_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2379 #define CTIMER1_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2380 #define CTIMER1_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2381 #define CTIMER1_MATCH1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 2) /* PIO0_20 */ 2382 #define CTIMER2_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2383 #define CTIMER2_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2384 #define CTIMER2_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2385 #define CTIMER2_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2386 #define CTIMER3_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2387 #define CTIMER3_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2388 #define CTIMER3_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2389 #define CTIMER3_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2390 #define CTIMER4_CAPTURE0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2391 #define CTIMER4_CAPTURE1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2392 #define CTIMER4_CAPTURE2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2393 #define CTIMER4_CAPTURE3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2394 #define CT_INP15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 3) /* PIO0_20 */ 2395 #define DMA0_TRIG00_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2396 #define DMA0_TRIG010_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2397 #define DMA0_TRIG011_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2398 #define DMA0_TRIG012_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2399 #define DMA0_TRIG013_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2400 #define DMA0_TRIG014_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2401 #define DMA0_TRIG015_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2402 #define DMA0_TRIG016_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2403 #define DMA0_TRIG017_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2404 #define DMA0_TRIG018_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2405 #define DMA0_TRIG019_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2406 #define DMA0_TRIG01_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2407 #define DMA0_TRIG020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2408 #define DMA0_TRIG021_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2409 #define DMA0_TRIG022_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2410 #define DMA0_TRIG023_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2411 #define DMA0_TRIG024_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2412 #define DMA0_TRIG025_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2413 #define DMA0_TRIG026_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2414 #define DMA0_TRIG027_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2415 #define DMA0_TRIG028_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2416 #define DMA0_TRIG029_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2417 #define DMA0_TRIG02_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2418 #define DMA0_TRIG030_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2419 #define DMA0_TRIG031_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2420 #define DMA0_TRIG032_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2421 #define DMA0_TRIG033_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2422 #define DMA0_TRIG034_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2423 #define DMA0_TRIG035_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2424 #define DMA0_TRIG036_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2425 #define DMA0_TRIG037_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2426 #define DMA0_TRIG038_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2427 #define DMA0_TRIG039_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2428 #define DMA0_TRIG03_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2429 #define DMA0_TRIG040_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2430 #define DMA0_TRIG041_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2431 #define DMA0_TRIG042_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2432 #define DMA0_TRIG043_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2433 #define DMA0_TRIG044_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2434 #define DMA0_TRIG045_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2435 #define DMA0_TRIG046_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2436 #define DMA0_TRIG047_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2437 #define DMA0_TRIG048_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2438 #define DMA0_TRIG049_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2439 #define DMA0_TRIG04_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2440 #define DMA0_TRIG050_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2441 #define DMA0_TRIG051_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2442 #define DMA0_TRIG05_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2443 #define DMA0_TRIG06_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2444 #define DMA0_TRIG07_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2445 #define DMA0_TRIG08_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2446 #define DMA0_TRIG09_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2447 #define DMA1_TRIG10_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2448 #define DMA1_TRIG11_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2449 #define DMA1_TRIG12_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2450 #define DMA1_TRIG13_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2451 #define DMA1_TRIG14_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2452 #define DMA1_TRIG15_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2453 #define DMA1_TRIG16_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2454 #define DMA1_TRIG17_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2455 #define DMA1_TRIG18_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2456 #define DMA1_TRIG19_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2457 #define FC3_CTS_SDA_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 1) /* PIO0_20 */ 2458 #define FC4_TXD_SCL_MISO_WS_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 11) /* PIO0_20 */ 2459 #define FC7_RXD_SDA_MOSI_DATA_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 7) /* PIO0_20 */ 2460 #define GPIO_PIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2461 #define HS_SPI_SSEL0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 8) /* PIO0_20 */ 2462 #define PINT_PINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2463 #define PINT_PINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2464 #define PINT_PINT2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2465 #define PINT_PINT3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2466 #define PINT_PINT4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2467 #define PINT_PINT5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2468 #define PINT_PINT6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2469 #define PINT_PINT7_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2470 #define PIO0_20_PIO0_20_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 0) /* PIO0_20 */ 2471 #define PWM1_X2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 13) /* PIO0_20 */ 2472 #define SCT0_IN0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2473 #define SCT0_IN1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2474 #define SCT0_IN2_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2475 #define SCT0_IN3_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2476 #define SCT0_IN4_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2477 #define SCT0_IN5_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2478 #define SCT0_IN6_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 4) /* PIO0_20 */ 2479 #define SECGPIO_SECPIO020_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ 2480 #define SECPINT_SECPINT0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ 2481 #define SECPINT_SECPINT1_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 10) /* PIO0_20 */ 2482 #define SPI_CS0_PIO0_20 IOCON_MUX(20, IOCON_TYPE_D, 12) /* PIO0_20 */ 2483 #define ADC0_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2484 #define ADC0_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2485 #define ADC0_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2486 #define ADC0_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2487 #define ADC1_TRIG0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2488 #define ADC1_TRIG1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2489 #define ADC1_TRIG2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2490 #define ADC1_TRIG3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2491 #define AOI0_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ 2492 #define AOI1_TRIGOUT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 12) /* PIO0_21 */ 2493 #define CTIMER3_MATCH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 3) /* PIO0_21 */ 2494 #define DMA0_TRIG00_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2495 #define DMA0_TRIG010_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2496 #define DMA0_TRIG011_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2497 #define DMA0_TRIG012_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2498 #define DMA0_TRIG013_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2499 #define DMA0_TRIG014_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2500 #define DMA0_TRIG015_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2501 #define DMA0_TRIG016_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2502 #define DMA0_TRIG017_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2503 #define DMA0_TRIG018_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2504 #define DMA0_TRIG019_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2505 #define DMA0_TRIG01_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2506 #define DMA0_TRIG020_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2507 #define DMA0_TRIG021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2508 #define DMA0_TRIG022_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2509 #define DMA0_TRIG023_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2510 #define DMA0_TRIG024_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2511 #define DMA0_TRIG025_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2512 #define DMA0_TRIG026_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2513 #define DMA0_TRIG027_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2514 #define DMA0_TRIG028_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2515 #define DMA0_TRIG029_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2516 #define DMA0_TRIG02_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2517 #define DMA0_TRIG030_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2518 #define DMA0_TRIG031_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2519 #define DMA0_TRIG032_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2520 #define DMA0_TRIG033_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2521 #define DMA0_TRIG034_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2522 #define DMA0_TRIG035_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2523 #define DMA0_TRIG036_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2524 #define DMA0_TRIG037_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2525 #define DMA0_TRIG038_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2526 #define DMA0_TRIG039_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2527 #define DMA0_TRIG03_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2528 #define DMA0_TRIG040_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2529 #define DMA0_TRIG041_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2530 #define DMA0_TRIG042_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2531 #define DMA0_TRIG043_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2532 #define DMA0_TRIG044_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2533 #define DMA0_TRIG045_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2534 #define DMA0_TRIG046_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2535 #define DMA0_TRIG047_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2536 #define DMA0_TRIG048_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2537 #define DMA0_TRIG049_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2538 #define DMA0_TRIG04_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2539 #define DMA0_TRIG050_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2540 #define DMA0_TRIG051_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2541 #define DMA0_TRIG05_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2542 #define DMA0_TRIG06_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2543 #define DMA0_TRIG07_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2544 #define DMA0_TRIG08_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2545 #define DMA0_TRIG09_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2546 #define DMA1_TRIG10_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2547 #define DMA1_TRIG11_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2548 #define DMA1_TRIG12_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2549 #define DMA1_TRIG13_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2550 #define DMA1_TRIG14_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2551 #define DMA1_TRIG15_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2552 #define DMA1_TRIG16_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2553 #define DMA1_TRIG17_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2554 #define DMA1_TRIG18_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2555 #define DMA1_TRIG19_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2556 #define ENC0_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2557 #define ENC0_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2558 #define ENC1_PHASEA_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2559 #define ENC1_PHASEB_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2560 #define EXTTRIG_IN7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2561 #define FC3_RTS_SCL_SSEL1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 1) /* PIO0_21 */ 2562 #define FC7_CTS_SDA_SSEL0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 9) /* PIO0_21 */ 2563 #define FC7_SCK_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 7) /* PIO0_21 */ 2564 #define FLEXSPI0_SS0_N_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 6) /* PIO0_21 */ 2565 #define GPIO_PIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2566 #define HS_SPI_SSEL3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 8) /* PIO0_21 */ 2567 #define PINT_PINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2568 #define PINT_PINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2569 #define PINT_PINT2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2570 #define PINT_PINT3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2571 #define PINT_PINT4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2572 #define PINT_PINT5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2573 #define PINT_PINT6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2574 #define PINT_PINT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2575 #define PIO0_21_PIO0_21_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 0) /* PIO0_21 */ 2576 #define PWM0_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2577 #define PWM0_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2578 #define PWM0_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2579 #define PWM0_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2580 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2581 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2582 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2583 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2584 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2585 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2586 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2587 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2588 #define PWM1_B1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 11) /* PIO0_21 */ 2589 #define PWM1_EXTA0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2590 #define PWM1_EXTA1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2591 #define PWM1_EXTA2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2592 #define PWM1_EXTA3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2593 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2594 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2595 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2596 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2597 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2598 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2599 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2600 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 13) /* PIO0_21 */ 2601 #define SCT0_IN0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2602 #define SCT0_IN1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2603 #define SCT0_IN2_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2604 #define SCT0_IN3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2605 #define SCT0_IN4_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2606 #define SCT0_IN5_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2607 #define SCT0_IN6_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 4) /* PIO0_21 */ 2608 #define SCT0_OUT7_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 5) /* PIO0_21 */ 2609 #define SECGPIO_SECPIO021_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ 2610 #define SECPINT_SECPINT0_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ 2611 #define SECPINT_SECPINT1_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 10) /* PIO0_21 */ 2612 #define UTICK0_CAPTURE3_PIO0_21 IOCON_MUX(21, IOCON_TYPE_D, 2) /* PIO0_21 */ 2613 #define ADC0_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2614 #define ADC0_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2615 #define ADC0_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2616 #define ADC0_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2617 #define ADC1_TRIG0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2618 #define ADC1_TRIG1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2619 #define ADC1_TRIG2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2620 #define ADC1_TRIG3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2621 #define CTIMER0_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2622 #define CTIMER0_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2623 #define CTIMER0_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2624 #define CTIMER0_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2625 #define CTIMER1_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2626 #define CTIMER1_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2627 #define CTIMER1_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2628 #define CTIMER1_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2629 #define CTIMER2_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2630 #define CTIMER2_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2631 #define CTIMER2_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2632 #define CTIMER2_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2633 #define CTIMER3_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2634 #define CTIMER3_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2635 #define CTIMER3_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2636 #define CTIMER3_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2637 #define CTIMER4_CAPTURE0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2638 #define CTIMER4_CAPTURE1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2639 #define CTIMER4_CAPTURE2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2640 #define CTIMER4_CAPTURE3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2641 #define CT_INP8_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 3) /* PIO0_24 */ 2642 #define DMA0_TRIG00_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2643 #define DMA0_TRIG010_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2644 #define DMA0_TRIG011_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2645 #define DMA0_TRIG012_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2646 #define DMA0_TRIG013_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2647 #define DMA0_TRIG014_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2648 #define DMA0_TRIG015_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2649 #define DMA0_TRIG016_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2650 #define DMA0_TRIG017_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2651 #define DMA0_TRIG018_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2652 #define DMA0_TRIG019_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2653 #define DMA0_TRIG01_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2654 #define DMA0_TRIG020_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2655 #define DMA0_TRIG021_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2656 #define DMA0_TRIG022_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2657 #define DMA0_TRIG023_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2658 #define DMA0_TRIG024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2659 #define DMA0_TRIG025_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2660 #define DMA0_TRIG026_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2661 #define DMA0_TRIG027_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2662 #define DMA0_TRIG028_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2663 #define DMA0_TRIG029_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2664 #define DMA0_TRIG02_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2665 #define DMA0_TRIG030_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2666 #define DMA0_TRIG031_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2667 #define DMA0_TRIG032_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2668 #define DMA0_TRIG033_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2669 #define DMA0_TRIG034_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2670 #define DMA0_TRIG035_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2671 #define DMA0_TRIG036_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2672 #define DMA0_TRIG037_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2673 #define DMA0_TRIG038_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2674 #define DMA0_TRIG039_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2675 #define DMA0_TRIG03_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2676 #define DMA0_TRIG040_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2677 #define DMA0_TRIG041_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2678 #define DMA0_TRIG042_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2679 #define DMA0_TRIG043_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2680 #define DMA0_TRIG044_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2681 #define DMA0_TRIG045_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2682 #define DMA0_TRIG046_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2683 #define DMA0_TRIG047_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2684 #define DMA0_TRIG048_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2685 #define DMA0_TRIG049_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2686 #define DMA0_TRIG04_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2687 #define DMA0_TRIG050_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2688 #define DMA0_TRIG051_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2689 #define DMA0_TRIG05_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2690 #define DMA0_TRIG06_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2691 #define DMA0_TRIG07_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2692 #define DMA0_TRIG08_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2693 #define DMA0_TRIG09_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2694 #define DMA1_TRIG10_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2695 #define DMA1_TRIG11_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2696 #define DMA1_TRIG12_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2697 #define DMA1_TRIG13_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2698 #define DMA1_TRIG14_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2699 #define DMA1_TRIG15_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2700 #define DMA1_TRIG16_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2701 #define DMA1_TRIG17_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2702 #define DMA1_TRIG18_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2703 #define DMA1_TRIG19_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2704 #define FC0_RXD_SDA_MOSI_DATA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 1) /* PIO0_24 */ 2705 #define GPIO_PIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2706 #define HSCMP0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2707 #define I3C0_SDA_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 5) /* PIO0_24 */ 2708 #define PINT_PINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2709 #define PINT_PINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2710 #define PINT_PINT2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2711 #define PINT_PINT3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2712 #define PINT_PINT4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2713 #define PINT_PINT5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2714 #define PINT_PINT6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2715 #define PINT_PINT7_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2716 #define PIO0_24_PIO0_24_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 0) /* PIO0_24 */ 2717 #define PWM0_A1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 11) /* PIO0_24 */ 2718 #define PWM0_X0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 13) /* PIO0_24 */ 2719 #define SCT0_IN0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2720 #define SCT0_IN1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2721 #define SCT0_IN2_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2722 #define SCT0_IN3_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2723 #define SCT0_IN4_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2724 #define SCT0_IN5_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2725 #define SCT0_IN6_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 4) /* PIO0_24 */ 2726 #define SECGPIO_SECPIO024_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ 2727 #define SECPINT_SECPINT0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ 2728 #define SECPINT_SECPINT1_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 10) /* PIO0_24 */ 2729 #define SPI_CS0_DIS_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 12) /* PIO0_24 */ 2730 #define SWD_TRACEDATA0_PIO0_24 IOCON_MUX(24, IOCON_TYPE_A, 6) /* PIO0_24 */ 2731 #define ADC0_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2732 #define ADC0_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2733 #define ADC0_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2734 #define ADC0_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2735 #define ADC1_TRIG0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2736 #define ADC1_TRIG1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2737 #define ADC1_TRIG2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2738 #define ADC1_TRIG3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2739 #define CLKOUT_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 2) /* PIO0_26 */ 2740 #define CTIMER0_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2741 #define CTIMER0_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2742 #define CTIMER0_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2743 #define CTIMER0_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2744 #define CTIMER1_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2745 #define CTIMER1_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2746 #define CTIMER1_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2747 #define CTIMER1_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2748 #define CTIMER2_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2749 #define CTIMER2_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2750 #define CTIMER2_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2751 #define CTIMER2_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2752 #define CTIMER3_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2753 #define CTIMER3_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2754 #define CTIMER3_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2755 #define CTIMER3_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2756 #define CTIMER4_CAPTURE0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2757 #define CTIMER4_CAPTURE1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2758 #define CTIMER4_CAPTURE2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2759 #define CTIMER4_CAPTURE3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2760 #define CT_INP14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 3) /* PIO0_26 */ 2761 #define DMA0_TRIG00_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2762 #define DMA0_TRIG010_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2763 #define DMA0_TRIG011_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2764 #define DMA0_TRIG012_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2765 #define DMA0_TRIG013_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2766 #define DMA0_TRIG014_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2767 #define DMA0_TRIG015_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2768 #define DMA0_TRIG016_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2769 #define DMA0_TRIG017_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2770 #define DMA0_TRIG018_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2771 #define DMA0_TRIG019_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2772 #define DMA0_TRIG01_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2773 #define DMA0_TRIG020_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2774 #define DMA0_TRIG021_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2775 #define DMA0_TRIG022_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2776 #define DMA0_TRIG023_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2777 #define DMA0_TRIG024_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2778 #define DMA0_TRIG025_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2779 #define DMA0_TRIG026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2780 #define DMA0_TRIG027_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2781 #define DMA0_TRIG028_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2782 #define DMA0_TRIG029_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2783 #define DMA0_TRIG02_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2784 #define DMA0_TRIG030_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2785 #define DMA0_TRIG031_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2786 #define DMA0_TRIG032_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2787 #define DMA0_TRIG033_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2788 #define DMA0_TRIG034_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2789 #define DMA0_TRIG035_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2790 #define DMA0_TRIG036_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2791 #define DMA0_TRIG037_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2792 #define DMA0_TRIG038_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2793 #define DMA0_TRIG039_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2794 #define DMA0_TRIG03_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2795 #define DMA0_TRIG040_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2796 #define DMA0_TRIG041_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2797 #define DMA0_TRIG042_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2798 #define DMA0_TRIG043_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2799 #define DMA0_TRIG044_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2800 #define DMA0_TRIG045_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2801 #define DMA0_TRIG046_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2802 #define DMA0_TRIG047_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2803 #define DMA0_TRIG048_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2804 #define DMA0_TRIG049_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2805 #define DMA0_TRIG04_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2806 #define DMA0_TRIG050_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2807 #define DMA0_TRIG051_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2808 #define DMA0_TRIG05_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2809 #define DMA0_TRIG06_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2810 #define DMA0_TRIG07_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2811 #define DMA0_TRIG08_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2812 #define DMA0_TRIG09_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2813 #define DMA1_TRIG10_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2814 #define DMA1_TRIG11_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2815 #define DMA1_TRIG12_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2816 #define DMA1_TRIG13_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2817 #define DMA1_TRIG14_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2818 #define DMA1_TRIG15_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2819 #define DMA1_TRIG16_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2820 #define DMA1_TRIG17_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2821 #define DMA1_TRIG18_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2822 #define DMA1_TRIG19_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2823 #define DMIC0_CLK0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 5) /* PIO0_26 */ 2824 #define FC0_SCK_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 8) /* PIO0_26 */ 2825 #define FC2_RXD_SDA_MOSI_DATA_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 1) /* PIO0_26 */ 2826 #define GPIO_PIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2827 #define HS_SPI_MOSI_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 9) /* PIO0_26 */ 2828 #define PINT_PINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2829 #define PINT_PINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2830 #define PINT_PINT2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2831 #define PINT_PINT3_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2832 #define PINT_PINT4_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2833 #define PINT_PINT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2834 #define PINT_PINT6_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2835 #define PINT_PINT7_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2836 #define PIO0_26_PIO0_26_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2837 #define PWM0_B1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 11) /* PIO0_26 */ 2838 #define RTC_TAMPER2_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 0) /* PIO0_26 */ 2839 #define SCT0_OUT5_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 4) /* PIO0_26 */ 2840 #define SECGPIO_SECPIO026_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ 2841 #define SECPINT_SECPINT0_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ 2842 #define SECPINT_SECPINT1_PIO0_26 IOCON_MUX(26, IOCON_TYPE_D, 10) /* PIO0_26 */ 2843 #define ADC0_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2844 #define ADC0_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2845 #define ADC0_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2846 #define ADC0_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2847 #define ADC1_TRIG0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2848 #define ADC1_TRIG1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2849 #define ADC1_TRIG2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2850 #define ADC1_TRIG3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2851 #define CTIMER3_MATCH2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 3) /* PIO0_27 */ 2852 #define DMA0_TRIG00_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2853 #define DMA0_TRIG010_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2854 #define DMA0_TRIG011_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2855 #define DMA0_TRIG012_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2856 #define DMA0_TRIG013_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2857 #define DMA0_TRIG014_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2858 #define DMA0_TRIG015_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2859 #define DMA0_TRIG016_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2860 #define DMA0_TRIG017_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2861 #define DMA0_TRIG018_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2862 #define DMA0_TRIG019_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2863 #define DMA0_TRIG01_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2864 #define DMA0_TRIG020_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2865 #define DMA0_TRIG021_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2866 #define DMA0_TRIG022_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2867 #define DMA0_TRIG023_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2868 #define DMA0_TRIG024_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2869 #define DMA0_TRIG025_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2870 #define DMA0_TRIG026_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2871 #define DMA0_TRIG027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2872 #define DMA0_TRIG028_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2873 #define DMA0_TRIG029_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2874 #define DMA0_TRIG02_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2875 #define DMA0_TRIG030_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2876 #define DMA0_TRIG031_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2877 #define DMA0_TRIG032_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2878 #define DMA0_TRIG033_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2879 #define DMA0_TRIG034_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2880 #define DMA0_TRIG035_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2881 #define DMA0_TRIG036_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2882 #define DMA0_TRIG037_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2883 #define DMA0_TRIG038_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2884 #define DMA0_TRIG039_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2885 #define DMA0_TRIG03_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2886 #define DMA0_TRIG040_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2887 #define DMA0_TRIG041_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2888 #define DMA0_TRIG042_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2889 #define DMA0_TRIG043_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2890 #define DMA0_TRIG044_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2891 #define DMA0_TRIG045_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2892 #define DMA0_TRIG046_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2893 #define DMA0_TRIG047_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2894 #define DMA0_TRIG048_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2895 #define DMA0_TRIG049_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2896 #define DMA0_TRIG04_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2897 #define DMA0_TRIG050_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2898 #define DMA0_TRIG051_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2899 #define DMA0_TRIG05_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2900 #define DMA0_TRIG06_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2901 #define DMA0_TRIG07_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2902 #define DMA0_TRIG08_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2903 #define DMA0_TRIG09_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2904 #define DMA1_TRIG10_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2905 #define DMA1_TRIG11_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2906 #define DMA1_TRIG12_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2907 #define DMA1_TRIG13_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2908 #define DMA1_TRIG14_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2909 #define DMA1_TRIG15_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2910 #define DMA1_TRIG16_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2911 #define DMA1_TRIG17_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2912 #define DMA1_TRIG18_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2913 #define DMA1_TRIG19_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2914 #define DMIC0_DATA0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 5) /* PIO0_27 */ 2915 #define FC2_TXD_SCL_MISO_WS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 1) /* PIO0_27 */ 2916 #define FC7_RXD_SDA_MOSI_DATA_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 7) /* PIO0_27 */ 2917 #define GPIO_PIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2918 #define OPAMP1_DP0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2919 #define PINT_PINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2920 #define PINT_PINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2921 #define PINT_PINT2_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2922 #define PINT_PINT3_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2923 #define PINT_PINT4_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2924 #define PINT_PINT5_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2925 #define PINT_PINT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2926 #define PINT_PINT7_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2927 #define PIO0_27_PIO0_27_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 0) /* PIO0_27 */ 2928 #define SCT0_OUT6_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 4) /* PIO0_27 */ 2929 #define SECGPIO_SECPIO027_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ 2930 #define SECPINT_SECPINT0_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ 2931 #define SECPINT_SECPINT1_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 10) /* PIO0_27 */ 2932 #define SPI_CS1_DIS_PIO0_27 IOCON_MUX(27, IOCON_TYPE_D, 12) /* PIO0_27 */ 2933 #define ADC0_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2934 #define ADC0_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2935 #define ADC0_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2936 #define ADC0_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2937 #define ADC1_TRIG0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2938 #define ADC1_TRIG1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2939 #define ADC1_TRIG2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2940 #define ADC1_TRIG3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2941 #define AOI0_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2942 #define AOI0_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2943 #define AOI0_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2944 #define AOI0_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2945 #define AOI0_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2946 #define AOI0_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2947 #define AOI0_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2948 #define AOI0_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2949 #define AOI0_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2950 #define AOI0_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2951 #define AOI0_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2952 #define AOI0_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2953 #define AOI0_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2954 #define AOI0_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2955 #define AOI0_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2956 #define AOI0_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2957 #define AOI1_IN0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2958 #define AOI1_IN10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2959 #define AOI1_IN11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2960 #define AOI1_IN12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2961 #define AOI1_IN13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2962 #define AOI1_IN14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2963 #define AOI1_IN15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2964 #define AOI1_IN1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2965 #define AOI1_IN2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2966 #define AOI1_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2967 #define AOI1_IN4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2968 #define AOI1_IN5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2969 #define AOI1_IN6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2970 #define AOI1_IN7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2971 #define AOI1_IN8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2972 #define AOI1_IN9_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 2973 #define CMP0_OUT_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 7) /* PIO0_29 */ 2974 #define CTIMER2_MATCH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 3) /* PIO0_29 */ 2975 #define DMA0_TRIG00_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2976 #define DMA0_TRIG010_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2977 #define DMA0_TRIG011_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2978 #define DMA0_TRIG012_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2979 #define DMA0_TRIG013_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2980 #define DMA0_TRIG014_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2981 #define DMA0_TRIG015_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2982 #define DMA0_TRIG016_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2983 #define DMA0_TRIG017_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2984 #define DMA0_TRIG018_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2985 #define DMA0_TRIG019_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2986 #define DMA0_TRIG01_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2987 #define DMA0_TRIG020_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2988 #define DMA0_TRIG021_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2989 #define DMA0_TRIG022_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2990 #define DMA0_TRIG023_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2991 #define DMA0_TRIG024_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2992 #define DMA0_TRIG025_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2993 #define DMA0_TRIG026_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2994 #define DMA0_TRIG027_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2995 #define DMA0_TRIG028_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2996 #define DMA0_TRIG029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2997 #define DMA0_TRIG02_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2998 #define DMA0_TRIG030_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 2999 #define DMA0_TRIG031_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3000 #define DMA0_TRIG032_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3001 #define DMA0_TRIG033_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3002 #define DMA0_TRIG034_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3003 #define DMA0_TRIG035_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3004 #define DMA0_TRIG036_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3005 #define DMA0_TRIG037_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3006 #define DMA0_TRIG038_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3007 #define DMA0_TRIG039_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3008 #define DMA0_TRIG03_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3009 #define DMA0_TRIG040_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3010 #define DMA0_TRIG041_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3011 #define DMA0_TRIG042_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3012 #define DMA0_TRIG043_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3013 #define DMA0_TRIG044_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3014 #define DMA0_TRIG045_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3015 #define DMA0_TRIG046_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3016 #define DMA0_TRIG047_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3017 #define DMA0_TRIG048_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3018 #define DMA0_TRIG049_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3019 #define DMA0_TRIG04_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3020 #define DMA0_TRIG050_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3021 #define DMA0_TRIG051_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3022 #define DMA0_TRIG05_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3023 #define DMA0_TRIG06_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3024 #define DMA0_TRIG07_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3025 #define DMA0_TRIG08_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3026 #define DMA0_TRIG09_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3027 #define DMA1_TRIG10_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3028 #define DMA1_TRIG11_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3029 #define DMA1_TRIG12_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3030 #define DMA1_TRIG13_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3031 #define DMA1_TRIG14_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3032 #define DMA1_TRIG15_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3033 #define DMA1_TRIG16_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3034 #define DMA1_TRIG17_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3035 #define DMA1_TRIG18_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3036 #define DMA1_TRIG19_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3037 #define ENC0_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3038 #define ENC0_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3039 #define ENC1_PHASEA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3040 #define ENC1_PHASEB_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3041 #define EXTTRIG_IN3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3042 #define FC0_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 1) /* PIO0_29 */ 3043 #define FC6_RXD_SDA_MOSI_DATA_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 6) /* PIO0_29 */ 3044 #define GPIO_PIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3045 #define PINT_PINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3046 #define PINT_PINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3047 #define PINT_PINT2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3048 #define PINT_PINT3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3049 #define PINT_PINT4_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3050 #define PINT_PINT5_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3051 #define PINT_PINT6_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3052 #define PINT_PINT7_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3053 #define PIO0_29_PIO0_29_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 0) /* PIO0_29 */ 3054 #define PWM0_A1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 11) /* PIO0_29 */ 3055 #define PWM0_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3056 #define PWM0_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3057 #define PWM0_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3058 #define PWM0_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3059 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3060 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3061 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3062 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3063 #define PWM0_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3064 #define PWM0_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3065 #define PWM0_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3066 #define PWM0_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3067 #define PWM1_EXTA0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3068 #define PWM1_EXTA1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3069 #define PWM1_EXTA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3070 #define PWM1_EXTA3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3071 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3072 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3073 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3074 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3075 #define PWM1_PWM_FAULT_TRG_CH0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3076 #define PWM1_PWM_FAULT_TRG_CH1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3077 #define PWM1_PWM_FAULT_TRG_CH2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3078 #define PWM1_PWM_FAULT_TRG_CH3_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 13) /* PIO0_29 */ 3079 #define SCT0_OUT8_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 4) /* PIO0_29 */ 3080 #define SECGPIO_SECPIO029_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ 3081 #define SECPINT_SECPINT0_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ 3082 #define SECPINT_SECPINT1_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 10) /* PIO0_29 */ 3083 #define SPI_DIN_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 12) /* PIO0_29 */ 3084 #define SWD_TRACEDATA2_PIO0_29 IOCON_MUX(29, IOCON_TYPE_D, 5) /* PIO0_29 */ 3085 #define ADC0_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3086 #define ADC0_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3087 #define ADC0_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3088 #define ADC0_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3089 #define ADC1_TRIG0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3090 #define ADC1_TRIG1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3091 #define ADC1_TRIG2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3092 #define ADC1_TRIG3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3093 #define AOI1_OUT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 12) /* PIO0_30 */ 3094 #define CAN0_TD_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 6) /* PIO0_30 */ 3095 #define CTIMER0_MATCH0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 3) /* PIO0_30 */ 3096 #define DMA0_TRIG00_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3097 #define DMA0_TRIG010_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3098 #define DMA0_TRIG011_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3099 #define DMA0_TRIG012_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3100 #define DMA0_TRIG013_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3101 #define DMA0_TRIG014_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3102 #define DMA0_TRIG015_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3103 #define DMA0_TRIG016_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3104 #define DMA0_TRIG017_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3105 #define DMA0_TRIG018_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3106 #define DMA0_TRIG019_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3107 #define DMA0_TRIG01_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3108 #define DMA0_TRIG020_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3109 #define DMA0_TRIG021_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3110 #define DMA0_TRIG022_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3111 #define DMA0_TRIG023_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3112 #define DMA0_TRIG024_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3113 #define DMA0_TRIG025_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3114 #define DMA0_TRIG026_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3115 #define DMA0_TRIG027_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3116 #define DMA0_TRIG028_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3117 #define DMA0_TRIG029_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3118 #define DMA0_TRIG02_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3119 #define DMA0_TRIG030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3120 #define DMA0_TRIG031_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3121 #define DMA0_TRIG032_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3122 #define DMA0_TRIG033_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3123 #define DMA0_TRIG034_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3124 #define DMA0_TRIG035_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3125 #define DMA0_TRIG036_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3126 #define DMA0_TRIG037_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3127 #define DMA0_TRIG038_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3128 #define DMA0_TRIG039_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3129 #define DMA0_TRIG03_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3130 #define DMA0_TRIG040_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3131 #define DMA0_TRIG041_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3132 #define DMA0_TRIG042_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3133 #define DMA0_TRIG043_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3134 #define DMA0_TRIG044_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3135 #define DMA0_TRIG045_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3136 #define DMA0_TRIG046_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3137 #define DMA0_TRIG047_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3138 #define DMA0_TRIG048_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3139 #define DMA0_TRIG049_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3140 #define DMA0_TRIG04_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3141 #define DMA0_TRIG050_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3142 #define DMA0_TRIG051_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3143 #define DMA0_TRIG05_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3144 #define DMA0_TRIG06_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3145 #define DMA0_TRIG07_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3146 #define DMA0_TRIG08_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3147 #define DMA0_TRIG09_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3148 #define DMA1_TRIG10_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3149 #define DMA1_TRIG11_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3150 #define DMA1_TRIG12_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3151 #define DMA1_TRIG13_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3152 #define DMA1_TRIG14_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3153 #define DMA1_TRIG15_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3154 #define DMA1_TRIG16_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3155 #define DMA1_TRIG17_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3156 #define DMA1_TRIG18_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3157 #define DMA1_TRIG19_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3158 #define FC0_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 1) /* PIO0_30 */ 3159 #define FC6_TXD_SCL_MISO_WS_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 9) /* PIO0_30 */ 3160 #define GPIO_PIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3161 #define PINT_PINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3162 #define PINT_PINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3163 #define PINT_PINT2_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3164 #define PINT_PINT3_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3165 #define PINT_PINT4_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3166 #define PINT_PINT5_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3167 #define PINT_PINT6_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3168 #define PINT_PINT7_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3169 #define PIO0_30_PIO0_30_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 0) /* PIO0_30 */ 3170 #define PWM1_A1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 11) /* PIO0_30 */ 3171 #define SCT0_OUT9_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 4) /* PIO0_30 */ 3172 #define SECGPIO_SECPIO030_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ 3173 #define SECPINT_SECPINT0_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ 3174 #define SECPINT_SECPINT1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 10) /* PIO0_30 */ 3175 #define SWD_TRACEDATA1_PIO0_30 IOCON_MUX(30, IOCON_TYPE_D, 5) /* PIO0_30 */ 3176 #define ADC0_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3177 #define ADC0_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3178 #define ADC0_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3179 #define ADC0_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3180 #define ADC1_CH0B_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3181 #define ADC1_TRIG0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3182 #define ADC1_TRIG1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3183 #define ADC1_TRIG2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3184 #define ADC1_TRIG3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3185 #define AOI1_OUT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 12) /* PIO1_0 */ 3186 #define CTIMER0_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3187 #define CTIMER0_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3188 #define CTIMER0_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3189 #define CTIMER0_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3190 #define CTIMER1_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3191 #define CTIMER1_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3192 #define CTIMER1_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3193 #define CTIMER1_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3194 #define CTIMER2_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3195 #define CTIMER2_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3196 #define CTIMER2_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3197 #define CTIMER2_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3198 #define CTIMER3_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3199 #define CTIMER3_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3200 #define CTIMER3_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3201 #define CTIMER3_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3202 #define CTIMER4_CAPTURE0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3203 #define CTIMER4_CAPTURE1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3204 #define CTIMER4_CAPTURE2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3205 #define CTIMER4_CAPTURE3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3206 #define CT_INP2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 3) /* PIO1_0 */ 3207 #define DMA0_TRIG00_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3208 #define DMA0_TRIG010_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3209 #define DMA0_TRIG011_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3210 #define DMA0_TRIG012_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3211 #define DMA0_TRIG013_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3212 #define DMA0_TRIG014_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3213 #define DMA0_TRIG015_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3214 #define DMA0_TRIG016_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3215 #define DMA0_TRIG017_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3216 #define DMA0_TRIG018_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3217 #define DMA0_TRIG019_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3218 #define DMA0_TRIG01_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3219 #define DMA0_TRIG020_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3220 #define DMA0_TRIG021_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3221 #define DMA0_TRIG022_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3222 #define DMA0_TRIG023_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3223 #define DMA0_TRIG024_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3224 #define DMA0_TRIG025_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3225 #define DMA0_TRIG026_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3226 #define DMA0_TRIG027_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3227 #define DMA0_TRIG028_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3228 #define DMA0_TRIG029_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3229 #define DMA0_TRIG02_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3230 #define DMA0_TRIG030_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3231 #define DMA0_TRIG031_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3232 #define DMA0_TRIG032_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3233 #define DMA0_TRIG033_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3234 #define DMA0_TRIG034_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3235 #define DMA0_TRIG035_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3236 #define DMA0_TRIG036_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3237 #define DMA0_TRIG037_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3238 #define DMA0_TRIG038_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3239 #define DMA0_TRIG039_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3240 #define DMA0_TRIG03_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3241 #define DMA0_TRIG040_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3242 #define DMA0_TRIG041_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3243 #define DMA0_TRIG042_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3244 #define DMA0_TRIG043_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3245 #define DMA0_TRIG044_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3246 #define DMA0_TRIG045_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3247 #define DMA0_TRIG046_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3248 #define DMA0_TRIG047_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3249 #define DMA0_TRIG048_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3250 #define DMA0_TRIG049_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3251 #define DMA0_TRIG04_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3252 #define DMA0_TRIG050_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3253 #define DMA0_TRIG051_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3254 #define DMA0_TRIG05_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3255 #define DMA0_TRIG06_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3256 #define DMA0_TRIG07_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3257 #define DMA0_TRIG08_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3258 #define DMA0_TRIG09_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3259 #define DMA1_TRIG10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3260 #define DMA1_TRIG11_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3261 #define DMA1_TRIG12_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3262 #define DMA1_TRIG13_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3263 #define DMA1_TRIG14_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3264 #define DMA1_TRIG15_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3265 #define DMA1_TRIG16_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3266 #define DMA1_TRIG17_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3267 #define DMA1_TRIG18_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3268 #define DMA1_TRIG19_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3269 #define FC0_RTS_SCL_SSEL1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 1) /* PIO1_0 */ 3270 #define GPIO_PIO10_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3271 #define PINT_PINT0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3272 #define PINT_PINT1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3273 #define PINT_PINT2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3274 #define PINT_PINT3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3275 #define PINT_PINT4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3276 #define PINT_PINT5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3277 #define PINT_PINT6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3278 #define PINT_PINT7_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3279 #define PIO1_0_PIO1_0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 0) /* PIO1_0 */ 3280 #define SCT0_IN0_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3281 #define SCT0_IN1_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3282 #define SCT0_IN2_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3283 #define SCT0_IN3_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3284 #define SCT0_IN4_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3285 #define SCT0_IN5_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3286 #define SCT0_IN6_PIO1_0 IOCON_MUX(32, IOCON_TYPE_D, 4) /* PIO1_0 */ 3287 #define ADC0_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3288 #define ADC0_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3289 #define ADC0_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3290 #define ADC0_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3291 #define ADC1_TRIG0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3292 #define ADC1_TRIG1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3293 #define ADC1_TRIG2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3294 #define ADC1_TRIG3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3295 #define CTIMER0_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3296 #define CTIMER0_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3297 #define CTIMER0_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3298 #define CTIMER0_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3299 #define CTIMER1_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3300 #define CTIMER1_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3301 #define CTIMER1_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3302 #define CTIMER1_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3303 #define CTIMER2_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3304 #define CTIMER2_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3305 #define CTIMER2_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3306 #define CTIMER2_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3307 #define CTIMER3_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3308 #define CTIMER3_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3309 #define CTIMER3_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3310 #define CTIMER3_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3311 #define CTIMER4_CAPTURE0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3312 #define CTIMER4_CAPTURE1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3313 #define CTIMER4_CAPTURE2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3314 #define CTIMER4_CAPTURE3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3315 #define CT_INP3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 3) /* PIO1_1 */ 3316 #define DMA0_TRIG00_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3317 #define DMA0_TRIG010_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3318 #define DMA0_TRIG011_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3319 #define DMA0_TRIG012_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3320 #define DMA0_TRIG013_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3321 #define DMA0_TRIG014_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3322 #define DMA0_TRIG015_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3323 #define DMA0_TRIG016_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3324 #define DMA0_TRIG017_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3325 #define DMA0_TRIG018_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3326 #define DMA0_TRIG019_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3327 #define DMA0_TRIG01_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3328 #define DMA0_TRIG020_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3329 #define DMA0_TRIG021_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3330 #define DMA0_TRIG022_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3331 #define DMA0_TRIG023_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3332 #define DMA0_TRIG024_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3333 #define DMA0_TRIG025_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3334 #define DMA0_TRIG026_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3335 #define DMA0_TRIG027_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3336 #define DMA0_TRIG028_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3337 #define DMA0_TRIG029_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3338 #define DMA0_TRIG02_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3339 #define DMA0_TRIG030_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3340 #define DMA0_TRIG031_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3341 #define DMA0_TRIG032_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3342 #define DMA0_TRIG033_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3343 #define DMA0_TRIG034_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3344 #define DMA0_TRIG035_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3345 #define DMA0_TRIG036_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3346 #define DMA0_TRIG037_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3347 #define DMA0_TRIG038_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3348 #define DMA0_TRIG039_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3349 #define DMA0_TRIG03_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3350 #define DMA0_TRIG040_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3351 #define DMA0_TRIG041_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3352 #define DMA0_TRIG042_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3353 #define DMA0_TRIG043_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3354 #define DMA0_TRIG044_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3355 #define DMA0_TRIG045_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3356 #define DMA0_TRIG046_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3357 #define DMA0_TRIG047_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3358 #define DMA0_TRIG048_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3359 #define DMA0_TRIG049_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3360 #define DMA0_TRIG04_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3361 #define DMA0_TRIG050_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3362 #define DMA0_TRIG051_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3363 #define DMA0_TRIG05_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3364 #define DMA0_TRIG06_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3365 #define DMA0_TRIG07_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3366 #define DMA0_TRIG08_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3367 #define DMA0_TRIG09_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3368 #define DMA1_TRIG10_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3369 #define DMA1_TRIG11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3370 #define DMA1_TRIG12_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3371 #define DMA1_TRIG13_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3372 #define DMA1_TRIG14_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3373 #define DMA1_TRIG15_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3374 #define DMA1_TRIG16_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3375 #define DMA1_TRIG17_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3376 #define DMA1_TRIG18_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3377 #define DMA1_TRIG19_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3378 #define FC3_RXD_SDA_MOSI_DATA_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 1) /* PIO1_1 */ 3379 #define GPIO_PIO11_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3380 #define HS_SPI_SSEL1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 5) /* PIO1_1 */ 3381 #define PINT_PINT0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3382 #define PINT_PINT1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3383 #define PINT_PINT2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3384 #define PINT_PINT3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3385 #define PINT_PINT4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3386 #define PINT_PINT5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3387 #define PINT_PINT6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3388 #define PINT_PINT7_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3389 #define PIO1_1_PIO1_1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3390 #define PWM0_B2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 12) /* PIO1_1 */ 3391 #define RTC_ALARMOUT_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 11) /* PIO1_1 */ 3392 #define RTC_TAMPER0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 0) /* PIO1_1 */ 3393 #define SCT0_IN0_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3394 #define SCT0_IN1_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3395 #define SCT0_IN2_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3396 #define SCT0_IN3_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3397 #define SCT0_IN4_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3398 #define SCT0_IN5_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3399 #define SCT0_IN6_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 4) /* PIO1_1 */ 3400 #define TRACECLK_PIO1_1 IOCON_MUX(33, IOCON_TYPE_D, 6) /* PIO1_1 */ 3401 #define ADC0_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3402 #define ADC0_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3403 #define ADC0_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3404 #define ADC0_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3405 #define ADC1_TRIG0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3406 #define ADC1_TRIG1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3407 #define ADC1_TRIG2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3408 #define ADC1_TRIG3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3409 #define AOI0_OUT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 12) /* PIO1_2 */ 3410 #define CAN0_TD_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 1) /* PIO1_2 */ 3411 #define CTIMER0_MATCH3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 3) /* PIO1_2 */ 3412 #define DMA0_TRIG00_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3413 #define DMA0_TRIG010_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3414 #define DMA0_TRIG011_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3415 #define DMA0_TRIG012_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3416 #define DMA0_TRIG013_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3417 #define DMA0_TRIG014_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3418 #define DMA0_TRIG015_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3419 #define DMA0_TRIG016_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3420 #define DMA0_TRIG017_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3421 #define DMA0_TRIG018_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3422 #define DMA0_TRIG019_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3423 #define DMA0_TRIG01_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3424 #define DMA0_TRIG020_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3425 #define DMA0_TRIG021_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3426 #define DMA0_TRIG022_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3427 #define DMA0_TRIG023_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3428 #define DMA0_TRIG024_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3429 #define DMA0_TRIG025_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3430 #define DMA0_TRIG026_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3431 #define DMA0_TRIG027_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3432 #define DMA0_TRIG028_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3433 #define DMA0_TRIG029_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3434 #define DMA0_TRIG02_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3435 #define DMA0_TRIG030_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3436 #define DMA0_TRIG031_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3437 #define DMA0_TRIG032_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3438 #define DMA0_TRIG033_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3439 #define DMA0_TRIG034_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3440 #define DMA0_TRIG035_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3441 #define DMA0_TRIG036_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3442 #define DMA0_TRIG037_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3443 #define DMA0_TRIG038_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3444 #define DMA0_TRIG039_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3445 #define DMA0_TRIG03_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3446 #define DMA0_TRIG040_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3447 #define DMA0_TRIG041_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3448 #define DMA0_TRIG042_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3449 #define DMA0_TRIG043_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3450 #define DMA0_TRIG044_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3451 #define DMA0_TRIG045_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3452 #define DMA0_TRIG046_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3453 #define DMA0_TRIG047_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3454 #define DMA0_TRIG048_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3455 #define DMA0_TRIG049_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3456 #define DMA0_TRIG04_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3457 #define DMA0_TRIG050_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3458 #define DMA0_TRIG051_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3459 #define DMA0_TRIG05_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3460 #define DMA0_TRIG06_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3461 #define DMA0_TRIG07_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3462 #define DMA0_TRIG08_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3463 #define DMA0_TRIG09_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3464 #define DMA1_TRIG10_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3465 #define DMA1_TRIG11_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3466 #define DMA1_TRIG12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3467 #define DMA1_TRIG13_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3468 #define DMA1_TRIG14_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3469 #define DMA1_TRIG15_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3470 #define DMA1_TRIG16_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3471 #define DMA1_TRIG17_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3472 #define DMA1_TRIG18_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3473 #define DMA1_TRIG19_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3474 #define DMIC0_CLK1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 5) /* PIO1_2 */ 3475 #define GPIO_PIO12_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3476 #define HS_SPI_SCK_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 6) /* PIO1_2 */ 3477 #define PINT_PINT0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3478 #define PINT_PINT1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3479 #define PINT_PINT2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3480 #define PINT_PINT3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3481 #define PINT_PINT4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3482 #define PINT_PINT5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3483 #define PINT_PINT6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3484 #define PINT_PINT7_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3485 #define PIO1_2_PIO1_2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 0) /* PIO1_2 */ 3486 #define PWM0_B0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 11) /* PIO1_2 */ 3487 #define SCT0_IN0_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3488 #define SCT0_IN1_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3489 #define SCT0_IN2_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3490 #define SCT0_IN3_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3491 #define SCT0_IN4_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3492 #define SCT0_IN5_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3493 #define SCT0_IN6_PIO1_2 IOCON_MUX(34, IOCON_TYPE_D, 4) /* PIO1_2 */ 3494 #define ADC0_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3495 #define ADC0_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3496 #define ADC0_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3497 #define ADC0_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3498 #define ADC1_TRIG0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3499 #define ADC1_TRIG1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3500 #define ADC1_TRIG2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3501 #define ADC1_TRIG3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3502 #define CAN0_RD_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 1) /* PIO1_3 */ 3503 #define DMA0_TRIG00_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3504 #define DMA0_TRIG010_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3505 #define DMA0_TRIG011_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3506 #define DMA0_TRIG012_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3507 #define DMA0_TRIG013_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3508 #define DMA0_TRIG014_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3509 #define DMA0_TRIG015_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3510 #define DMA0_TRIG016_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3511 #define DMA0_TRIG017_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3512 #define DMA0_TRIG018_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3513 #define DMA0_TRIG019_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3514 #define DMA0_TRIG01_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3515 #define DMA0_TRIG020_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3516 #define DMA0_TRIG021_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3517 #define DMA0_TRIG022_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3518 #define DMA0_TRIG023_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3519 #define DMA0_TRIG024_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3520 #define DMA0_TRIG025_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3521 #define DMA0_TRIG026_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3522 #define DMA0_TRIG027_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3523 #define DMA0_TRIG028_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3524 #define DMA0_TRIG029_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3525 #define DMA0_TRIG02_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3526 #define DMA0_TRIG030_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3527 #define DMA0_TRIG031_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3528 #define DMA0_TRIG032_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3529 #define DMA0_TRIG033_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3530 #define DMA0_TRIG034_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3531 #define DMA0_TRIG035_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3532 #define DMA0_TRIG036_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3533 #define DMA0_TRIG037_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3534 #define DMA0_TRIG038_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3535 #define DMA0_TRIG039_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3536 #define DMA0_TRIG03_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3537 #define DMA0_TRIG040_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3538 #define DMA0_TRIG041_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3539 #define DMA0_TRIG042_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3540 #define DMA0_TRIG043_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3541 #define DMA0_TRIG044_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3542 #define DMA0_TRIG045_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3543 #define DMA0_TRIG046_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3544 #define DMA0_TRIG047_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3545 #define DMA0_TRIG048_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3546 #define DMA0_TRIG049_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3547 #define DMA0_TRIG04_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3548 #define DMA0_TRIG050_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3549 #define DMA0_TRIG051_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3550 #define DMA0_TRIG05_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3551 #define DMA0_TRIG06_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3552 #define DMA0_TRIG07_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3553 #define DMA0_TRIG08_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3554 #define DMA0_TRIG09_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3555 #define DMA1_TRIG10_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3556 #define DMA1_TRIG11_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3557 #define DMA1_TRIG12_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3558 #define DMA1_TRIG13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3559 #define DMA1_TRIG14_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3560 #define DMA1_TRIG15_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3561 #define DMA1_TRIG16_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3562 #define DMA1_TRIG17_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3563 #define DMA1_TRIG18_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3564 #define DMA1_TRIG19_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3565 #define DMIC0_DATA1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 5) /* PIO1_3 */ 3566 #define FC2_TXD_SCL_MISO_WS_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 3) /* PIO1_3 */ 3567 #define GPIO_PIO13_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3568 #define HS_SPI_MISO_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 6) /* PIO1_3 */ 3569 #define PINT_PINT0_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3570 #define PINT_PINT1_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3571 #define PINT_PINT2_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3572 #define PINT_PINT3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3573 #define PINT_PINT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3574 #define PINT_PINT5_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3575 #define PINT_PINT6_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3576 #define PINT_PINT7_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3577 #define PIO1_3_PIO1_3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 0) /* PIO1_3 */ 3578 #define PWM0_A3_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 11) /* PIO1_3 */ 3579 #define SCT0_OUT4_PIO1_3 IOCON_MUX(35, IOCON_TYPE_D, 4) /* PIO1_3 */ 3580 #define ADC0_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3581 #define ADC0_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3582 #define ADC0_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3583 #define ADC0_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3584 #define ADC1_TRIG0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3585 #define ADC1_TRIG1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3586 #define ADC1_TRIG2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3587 #define ADC1_TRIG3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3588 #define CTIMER0_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3589 #define CTIMER0_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3590 #define CTIMER0_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3591 #define CTIMER0_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3592 #define CTIMER1_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3593 #define CTIMER1_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3594 #define CTIMER1_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3595 #define CTIMER1_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3596 #define CTIMER2_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3597 #define CTIMER2_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3598 #define CTIMER2_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3599 #define CTIMER2_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3600 #define CTIMER3_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3601 #define CTIMER3_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3602 #define CTIMER3_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3603 #define CTIMER3_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3604 #define CTIMER4_CAPTURE0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3605 #define CTIMER4_CAPTURE1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3606 #define CTIMER4_CAPTURE2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3607 #define CTIMER4_CAPTURE3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3608 #define CT_INP5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 3) /* PIO1_11 */ 3609 #define DMA0_TRIG00_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3610 #define DMA0_TRIG010_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3611 #define DMA0_TRIG011_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3612 #define DMA0_TRIG012_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3613 #define DMA0_TRIG013_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3614 #define DMA0_TRIG014_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3615 #define DMA0_TRIG015_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3616 #define DMA0_TRIG016_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3617 #define DMA0_TRIG017_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3618 #define DMA0_TRIG018_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3619 #define DMA0_TRIG019_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3620 #define DMA0_TRIG01_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3621 #define DMA0_TRIG020_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3622 #define DMA0_TRIG021_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3623 #define DMA0_TRIG022_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3624 #define DMA0_TRIG023_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3625 #define DMA0_TRIG024_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3626 #define DMA0_TRIG025_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3627 #define DMA0_TRIG026_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3628 #define DMA0_TRIG027_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3629 #define DMA0_TRIG028_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3630 #define DMA0_TRIG029_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3631 #define DMA0_TRIG02_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3632 #define DMA0_TRIG030_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3633 #define DMA0_TRIG031_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3634 #define DMA0_TRIG032_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3635 #define DMA0_TRIG033_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3636 #define DMA0_TRIG034_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3637 #define DMA0_TRIG035_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3638 #define DMA0_TRIG036_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3639 #define DMA0_TRIG037_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3640 #define DMA0_TRIG038_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3641 #define DMA0_TRIG039_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3642 #define DMA0_TRIG03_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3643 #define DMA0_TRIG040_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3644 #define DMA0_TRIG041_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3645 #define DMA0_TRIG042_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3646 #define DMA0_TRIG043_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3647 #define DMA0_TRIG044_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3648 #define DMA0_TRIG045_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3649 #define DMA0_TRIG046_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3650 #define DMA0_TRIG047_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3651 #define DMA0_TRIG048_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3652 #define DMA0_TRIG049_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3653 #define DMA0_TRIG04_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3654 #define DMA0_TRIG050_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3655 #define DMA0_TRIG051_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3656 #define DMA0_TRIG05_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3657 #define DMA0_TRIG06_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3658 #define DMA0_TRIG07_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3659 #define DMA0_TRIG08_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3660 #define DMA0_TRIG09_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3661 #define DMA1_TRIG10_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3662 #define DMA1_TRIG11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3663 #define DMA1_TRIG12_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3664 #define DMA1_TRIG13_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3665 #define DMA1_TRIG14_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3666 #define DMA1_TRIG15_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3667 #define DMA1_TRIG16_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3668 #define DMA1_TRIG17_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3669 #define DMA1_TRIG18_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3670 #define DMA1_TRIG19_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3671 #define ENC0_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3672 #define ENC0_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3673 #define ENC1_PHASEA_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3674 #define ENC1_PHASEB_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3675 #define EXTTRIG_IN8_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3676 #define FC1_TXD_SCL_MISO_WS_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 2) /* PIO1_11 */ 3677 #define FC6_SCK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 10) /* PIO1_11 */ 3678 #define GPIO_PIO111_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3679 #define HS_SPI_SSEL0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 7) /* PIO1_11 */ 3680 #define PINT_PINT0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3681 #define PINT_PINT1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3682 #define PINT_PINT2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3683 #define PINT_PINT3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3684 #define PINT_PINT4_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3685 #define PINT_PINT5_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3686 #define PINT_PINT6_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3687 #define PINT_PINT7_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3688 #define PIO1_11_PIO1_11_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 0) /* PIO1_11 */ 3689 #define PWM0_A0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 11) /* PIO1_11 */ 3690 #define PWM0_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3691 #define PWM0_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3692 #define PWM0_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3693 #define PWM0_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3694 #define PWM0_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3695 #define PWM0_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3696 #define PWM0_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3697 #define PWM0_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3698 #define PWM0_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3699 #define PWM0_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3700 #define PWM0_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3701 #define PWM0_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3702 #define PWM1_EXTA0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3703 #define PWM1_EXTA1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3704 #define PWM1_EXTA2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3705 #define PWM1_EXTA3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3706 #define PWM1_PWM_EXSYNC_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3707 #define PWM1_PWM_EXSYNC_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3708 #define PWM1_PWM_EXSYNC_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3709 #define PWM1_PWM_EXSYNC_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3710 #define PWM1_PWM_FAULT_TRG_CH0_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3711 #define PWM1_PWM_FAULT_TRG_CH1_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3712 #define PWM1_PWM_FAULT_TRG_CH2_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3713 #define PWM1_PWM_FAULT_TRG_CH3_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 13) /* PIO1_11 */ 3714 #define SPI_SCLK_PIO1_11 IOCON_MUX(43, IOCON_TYPE_D, 12) /* PIO1_11 */ 3715 #define AOI0_OUT2_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 12) /* PIO2_1 */ 3716 #define CTIMER1_MATCH0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 4) /* PIO2_1 */ 3717 #define FC0_TXD_SCL_MISO_WS_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 2) /* PIO2_1 */ 3718 #define GPIO_PIO21_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ 3719 #define I3C0_SDA_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 5) /* PIO2_1 */ 3720 #define OPAMP2_DP0_PIO2_1 IOCON_MUX(65, IOCON_TYPE_D, 0) /* PIO2_1 */ 3721 3722 #endif 3723
