1 /*
2  * Copyright 2022 NXP
3  *
4  * SPDX-License-Identifier: BSD-3-Clause
5  */
6 
7 #ifndef SIUL2_PORT_IP_DEFINES
8 #define SIUL2_PORT_IP_DEFINES
9 
10 /**
11 *   @file    Siul2_Port_Ip_Defines.h
12 *
13 *   @addtogroup Port_CFG
14 *   @{
15 */
16 
17 #ifdef __cplusplus
18 extern "C"{
19 #endif
20 
21 /*==================================================================================================
22 *                                        INCLUDE FILES
23 * 1) system and project includes
24 * 2) needed interfaces from external units
25 * 3) internal and external interfaces from this unit
26 ==================================================================================================*/
27 #include "S32Z2_SIUL2.h"
28 /*==================================================================================================
29 *                              SOURCE FILE VERSION INFORMATION
30 ==================================================================================================*/
31 #define SIUL2_PORT_IP_DEFINES_VENDOR_ID_H                       43
32 #define SIUL2_PORT_IP_DEFINES_AR_RELEASE_MAJOR_VERSION_H        4
33 #define SIUL2_PORT_IP_DEFINES_AR_RELEASE_MINOR_VERSION_H        7
34 #define SIUL2_PORT_IP_DEFINES_AR_RELEASE_REVISION_VERSION_H     0
35 #define SIUL2_PORT_IP_DEFINES_SW_MAJOR_VERSION_H                0
36 #define SIUL2_PORT_IP_DEFINES_SW_MINOR_VERSION_H                9
37 #define SIUL2_PORT_IP_DEFINES_SW_PATCH_VERSION_H                0
38 
39 /*==================================================================================================
40 *                                     FILE VERSION CHECKS
41 ==================================================================================================*/
42 
43 /*==================================================================================================
44 *                                          CONSTANTS
45 ==================================================================================================*/
46 
47 /*==================================================================================================
48 *                                      DEFINES AND MACROS
49 ==================================================================================================*/
50 
51 /* S32ZE */
52 #define SIUL2_PORT_IP_MULTIPLE_SIUL2_INSTANCES
53 
54 /**
55 * @brief Number of SIUL2 instances present on the subderivative
56 */
57 #define SIUL2_NUM_SIUL2_INSTANCES_U8 (5)
58 
59 /**
60 * @brief Macros defined for the SIUL2 IPV that are protected.
61 */
62 #define MCAL_SIUL2_REG_PROT_AVAILABLE   (STD_ON)
63 
64 /**
65 * @brief Support for User mode.
66 * If this parameter has been configured to STD_ON, the PORT driver code can be executed from both supervisor and user mode.
67 */
68 #define PORT_ENABLE_USER_MODE_SUPPORT   (STD_OFF)
69 /**
70 * @brief Support for REG_PROT in SIUL2 IP.
71 *        If the current platform implements REG_PROT for SIUL2 IP, this parameter will be defined, and will enable REG_PROT configuration for SIUL2 IP in PORT drvier
72 */
73 #define PORT_SIUL2_REG_PROT_AVAILABLE   (STD_OFF)
74 
75 #ifndef MCAL_ENABLE_USER_MODE_SUPPORT
76     #ifdef PORT_ENABLE_USER_MODE_SUPPORT
77         #if (STD_ON == PORT_ENABLE_USER_MODE_SUPPORT)
78             #error MCAL_ENABLE_USER_MODE_SUPPORT is not enabled. For running Port in user mode the MCAL_ENABLE_USER_MODE_SUPPORT needs to be defined
79         #endif /* (STD_ON == PORT_ENABLE_USER_MODE_SUPPORT) */
80     #endif /* ifdef PORT_ENABLE_USER_MODE_SUPPORT*/
81 #endif /* ifndef MCAL_ENABLE_USER_MODE_SUPPORT */
82 
83 /* Pre-processor switch to enable/disable development error detection for Siul2 Ip API */
84 #define SIUL2_PORT_IP_DEV_ERROR_DETECT                         (STD_ON)
85 
86 /*! @brief SIUL2 module has RCVR bit */
87 #define FEATURE_SIUL2_PORT_IP_HAS_RECEIVER_SELECT             (STD_ON)
88 /*! @brief SIUL2 module has ODE bit */
89 #define FEATURE_SIUL2_PORT_IP_HAS_OPEN_DRAIN                  (STD_ON)
90 /*! @brief SIUL2 module has TRC bit */
91 #define FEATURE_SIUL2_PORT_IP_HAS_TERMINATION_RESISTOR        (STD_ON)
92 /*! @brief SIUL2 module has CREF bit */
93 #define FEATURE_SIUL2_PORT_IP_HAS_CURRENT_REFERENCE_CONTROL   (STD_ON)
94 /*! @brief SIUL2 module has RXCB bit */
95 #define FEATURE_SIUL2_PORT_IP_HAS_RX_CURRENT_BOOST            (STD_ON)
96 
97 /* Workaround when this define in header is incorrect */
98 /*! @name MSCR - SIUL2 Multiplexed Signal Configuration Register */
99 /*! @{ */
100 #ifdef SIUL2_MSCR_SRE_MASK
101 #undef SIUL2_MSCR_SRE_MASK
102 #undef SIUL2_MSCR_SRE_SHIFT
103 #undef SIUL2_MSCR_SRE_WIDTH
104 #undef SIUL2_MSCR_SRE
105 #define SIUL2_MSCR_SRE_MASK                      (0x1C000U)
106 #define SIUL2_MSCR_SRE_SHIFT                     (14U)
107 #define SIUL2_MSCR_SRE_WIDTH                     (3U)
108 #define SIUL2_MSCR_SRE(x)                        (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_SRE_SHIFT)) & SIUL2_MSCR_SRE_MASK)
109 #endif /* SIUL2_MSCR_SRE_MASK */
110 
111 #ifdef SIUL2_MSCR_PUE_MASK
112 #undef SIUL2_MSCR_PUE_MASK
113 #undef SIUL2_MSCR_PUE_SHIFT
114 #undef SIUL2_MSCR_PUE_WIDTH
115 #undef SIUL2_MSCR_PUE
116 #define SIUL2_MSCR_PUE_MASK                      (0x2000U)
117 #define SIUL2_MSCR_PUE_SHIFT                     (13U)
118 #define SIUL2_MSCR_PUE_WIDTH                     (1U)
119 #define SIUL2_MSCR_PUE(x)                        (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PUE_SHIFT)) & SIUL2_MSCR_PUE_MASK)
120 #endif /* SIUL2_MSCR_PUE_MASK */
121 
122 #ifdef SIUL2_MSCR_PUS_MASK
123 #undef SIUL2_MSCR_PUS_MASK
124 #undef SIUL2_MSCR_PUS_SHIFT
125 #undef SIUL2_MSCR_PUS_WIDTH
126 #undef SIUL2_MSCR_PUS
127 #define SIUL2_MSCR_PUS_MASK                      (0x1000U)
128 #define SIUL2_MSCR_PUS_SHIFT                     (12U)
129 #define SIUL2_MSCR_PUS_WIDTH                     (1U)
130 #define SIUL2_MSCR_PUS(x)                        (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_PUS_SHIFT)) & SIUL2_MSCR_PUS_MASK)
131 #endif /* SIUL2_MSCR_PUS_MASK */
132 
133 #ifdef SIUL2_MSCR_OBE_MASK
134 #undef SIUL2_MSCR_OBE_MASK
135 #undef SIUL2_MSCR_OBE_SHIFT
136 #undef SIUL2_MSCR_OBE_WIDTH
137 #undef SIUL2_MSCR_OBE
138 #define SIUL2_MSCR_OBE_MASK                      (0x200000U)
139 #define SIUL2_MSCR_OBE_SHIFT                     (21U)
140 #define SIUL2_MSCR_OBE_WIDTH                     (1U)
141 #define SIUL2_MSCR_OBE(x)                        (((uint32_t)(((uint32_t)(x)) << SIUL2_MSCR_OBE_SHIFT)) & SIUL2_MSCR_OBE_MASK)
142 #endif /* SIUL2_MSCR_OBE_MASK */
143 
144 /*! @} */
145 
146 #define SIUL2_0_MSCR_BASE                (IP_SIUL2_0->MSCR)
147 #define SIUL2_1_MSCR_BASE                (IP_SIUL2_1->MSCR)
148 #define SIUL2_3_MSCR_BASE                (IP_SIUL2_3->MSCR)
149 #define SIUL2_4_MSCR_BASE                (IP_SIUL2_4->MSCR)
150 #define SIUL2_5_MSCR_BASE                (IP_SIUL2_5->MSCR)
151 
152 /** SIUL2_0 */
153 /** Peripheral PORTA base pointer. Pins start from PAD_000 to PAD_015. */
154 #define PORTA                            ((Siul2_Port_Ip_PortType *)(SIUL2_0_MSCR_BASE + 0x00))
155 /** Peripheral PORTB base pointer. Pins start from PAD_016 to PAD_030. */
156 #define PORTB                            ((Siul2_Port_Ip_PortType *)(SIUL2_0_MSCR_BASE + 0x10))
157 /** SIUL2_1 */
158 /** Peripheral PORTC base pointer. Pins: PAD_031. */
159 #define PORTC                            ((Siul2_Port_Ip_PortType *)(SIUL2_1_MSCR_BASE + 0x10))
160 /** Peripheral PORTD base pointer. Pins start from PAD_032 to PAD_047. */
161 #define PORTD                            ((Siul2_Port_Ip_PortType *)(SIUL2_1_MSCR_BASE + 0x20))
162 /** Peripheral PORTE base pointer. Pins start from PAD_048 to PAD_063. */
163 #define PORTE                            ((Siul2_Port_Ip_PortType *)(SIUL2_1_MSCR_BASE + 0x30))
164 /** Peripheral PORTF base pointer. Pins start from PAD_064 to PAD_079. */
165 #define PORTF                            ((Siul2_Port_Ip_PortType *)(SIUL2_1_MSCR_BASE + 0x40))
166 /** Peripheral PORTG base pointer. Pins start from PAD_080 to PAD_091. */
167 #define PORTG                            ((Siul2_Port_Ip_PortType *)(SIUL2_1_MSCR_BASE + 0x50))
168 /** SIUL2_4 */
169 /** Peripheral PORTH base pointer. Pins start from PAD_092 to PAD_095. */
170 #define PORTH                            ((Siul2_Port_Ip_PortType *)(SIUL2_4_MSCR_BASE + 0x50))
171 /** Peripheral PORTI base pointer. Pins start from PAD_096 to PAD_111. */
172 #define PORTI                            ((Siul2_Port_Ip_PortType *)(SIUL2_4_MSCR_BASE + 0x60))
173 /** Peripheral PORTJ base pointer. Pins start from PAD_112 to PAD_127. */
174 #define PORTJ                            ((Siul2_Port_Ip_PortType *)(SIUL2_4_MSCR_BASE + 0x70))
175 /** Peripheral PORTK base pointer. Pins start from PAD_128 to PAD_143. */
176 #define PORTK                            ((Siul2_Port_Ip_PortType *)(SIUL2_4_MSCR_BASE + 0x80))
177 /** Peripheral PORTL base pointer. Pins start from PAD_144 to PAD_145. */
178 #define PORTL                            ((Siul2_Port_Ip_PortType *)(SIUL2_4_MSCR_BASE + 0x90))
179 /** SIUL2_5 */
180 /** Peripheral PORTM base pointer. Pins start from PAD_146 to PAD_159. */
181 #define PORTM                            ((Siul2_Port_Ip_PortType *)(SIUL2_5_MSCR_BASE + 0x90))
182 /** Peripheral PORTN base pointer. Pins start from PAD_160 to PAD_169. */
183 #define PORTN                            ((Siul2_Port_Ip_PortType *)(SIUL2_5_MSCR_BASE + 0xA0))
184 /** SIUL2_0 */
185 /** Peripheral PORTO base pointer. Pins start from PAD_170 to PAD_173. */
186 #define PORTO                            ((Siul2_Port_Ip_PortType *)(SIUL2_0_MSCR_BASE + 0xA0))
187 
188 #define PORT_SIUL2_0_IMCRS_IDX_END_U16     ((uint16)89)
189 #define PORT_SIUL2_1_IMCRS_IDX_END_U16     ((uint16)209)
190 #define PORT_SIUL2_3_IMCRS_IDX_END_U16     ((uint16)23)
191 #define PORT_SIUL2_4_IMCRS_IDX_END_U16     ((uint16)371)
192 #define PORT_SIUL2_5_IMCRS_IDX_END_U16     ((uint16)474)
193 
194 /* Pre-processor switch to enable/disable VirtWrapper support */
195 #define PORT_VIRTWRAPPER_SUPPORT                      (STD_OFF)
196 
197 
198 /*==================================================================================================
199 *                                             ENUMS
200 ==================================================================================================*/
201 
202 /*==================================================================================================
203 *                                STRUCTURES AND OTHER TYPEDEFS
204 ==================================================================================================*/
205 
206 
207 /*==================================================================================================
208 *                                GLOBAL VARIABLE DECLARATIONS
209 ==================================================================================================*/
210 
211 /*==================================================================================================
212 *                                    FUNCTION PROTOTYPES
213 ==================================================================================================*/
214 
215 
216 #ifdef __cplusplus
217 }
218 #endif
219 
220 /** @} */
221 
222 #endif /* SIUL2_PORT_IP_DEFINES */
223