1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6
7 /**
8 * @file
9 *
10 * @addtogroup RTE_MODULE
11 * @{
12 */
13
14 #ifdef __cplusplus
15 extern "C"{
16 #endif
17
18 /*==================================================================================================
19 * INCLUDE FILES
20 * 1) system and project includes
21 * 2) needed interfaces from external units
22 * 3) internal and external interfaces from this unit
23 ==================================================================================================*/
24 #include "Std_Types.h"
25 #include "Mcal.h"
26 #include "OsIf.h"
27 #include "SchM_EthSwt_43_NETC.h"
28 #ifdef MCAL_TESTING_ENVIRONMENT
29 #include "EUnit.h" /* EUnit Test Suite */
30 #endif
31
32 /*==================================================================================================
33 * SOURCE FILE VERSION INFORMATION
34 ==================================================================================================*/
35 #define SCHM_ETHSWT_43_NETC_AR_RELEASE_MAJOR_VERSION_C 4
36 #define SCHM_ETHSWT_43_NETC_AR_RELEASE_MINOR_VERSION_C 7
37 #define SCHM_ETHSWT_43_NETC_AR_RELEASE_REVISION_VERSION_C 0
38 #define SCHM_ETHSWT_43_NETC_SW_MAJOR_VERSION_C 0
39 #define SCHM_ETHSWT_43_NETC_SW_MINOR_VERSION_C 9
40 #define SCHM_ETHSWT_43_NETC_SW_PATCH_VERSION_C 0
41
42 /*==================================================================================================
43 * LOCAL CONSTANTS
44 ==================================================================================================*/
45 #ifdef MCAL_PLATFORM_ARM
46 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
47 #define ISR_STATE_MASK ((uint32)0x000000C0UL) /**< @brief DAIF bit I and F */
48 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
49 #define ISR_STATE_MASK ((uint32)0x00000080UL) /**< @brief CPSR bit I */
50 #else
51 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
52 #define ISR_STATE_MASK ((uint32)0x000000FFUL) /**< @brief BASEPRI[7:0] mask */
53 #else
54 #define ISR_STATE_MASK ((uint32)0x00000001UL) /**< @brief PRIMASK bit 0 */
55 #endif
56 #endif
57 #else
58 #ifdef MCAL_PLATFORM_S12
59 #define ISR_STATE_MASK ((uint32)0x00000010UL) /**< @brief I bit of CCR */
60 #else
61 #define ISR_STATE_MASK ((uint32)0x00008000UL) /**< @brief EE bit of MSR */
62 #endif
63 #endif
64 /*==================================================================================================
65 * LOCAL MACROS
66 ==================================================================================================*/
67 #ifdef MCAL_PLATFORM_ARM
68 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
69 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
70 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
71 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) != (uint32)(ISR_STATE_MASK))
72 #else
73 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
74 #endif
75 #else
76 #ifdef MCAL_PLATFORM_S12
77 #define ISR_ON(msr) (uint32)(((uint32)(msr) & (uint32)(ISR_STATE_MASK)) == (uint32)0)
78 #else
79 #define ISR_ON(msr) (uint32)((uint32)(msr) & (uint32)(ISR_STATE_MASK))
80 #endif
81 #endif
82
83 /*==================================================================================================
84 * FILE VERSION CHECKS
85 ==================================================================================================*/
86
87 /*==================================================================================================
88 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
89 ==================================================================================================*/
90
91
92 /*==================================================================================================
93 * LOCAL VARIABLES
94 ==================================================================================================*/
95 #define RTE_START_SEC_VAR_CLEARED_32_NO_CACHEABLE
96 #include "Rte_MemMap.h"
97
98 #define RTE_STOP_SEC_VAR_CLEARED_32_NO_CACHEABLE
99 #include "Rte_MemMap.h"
100 /*==================================================================================================
101 * GLOBAL CONSTANTS
102 ==================================================================================================*/
103
104
105 /*==================================================================================================
106 * GLOBAL VARIABLES
107 ==================================================================================================*/
108
109 /*==================================================================================================
110 * LOCAL FUNCTION PROTOTYPES
111 ==================================================================================================*/
112
113 #ifndef _COSMIC_C_S32ZE_
114 /*================================================================================================*/
115 /**
116 * @brief This function returns the MSR register value (32 bits).
117 * @details This function returns the MSR register value (32 bits).
118 *
119 * @param[in] void No input parameters
120 * @return uint32 msr This function returns the MSR register value (32 bits).
121 *
122 * @pre None
123 * @post None
124 *
125 */
126 uint32 EthSwt_43_NETC_schm_read_msr(void);
127 #endif /*ifndef _COSMIC_C_S32ZE_*/
128 /*==================================================================================================
129 * LOCAL FUNCTIONS
130 ==================================================================================================*/
131 #define RTE_START_SEC_CODE
132 #include "Rte_MemMap.h"
133
134 #if (defined(_GREENHILLS_C_S32ZE_) || defined(_CODEWARRIOR_C_S32ZE_))
135 /*================================================================================================*/
136 /**
137 * @brief This macro returns the MSR register value (32 bits).
138 * @details This macro function implementation returns the MSR register value in r3 (32 bits).
139 *
140 * @pre None
141 * @post None
142 *
143 */
144 #ifdef MCAL_PLATFORM_ARM
145 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
EthSwt_43_NETC_schm_read_msr(void)146 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
147 {
148 mrs x0, S3_3_c4_c2_1
149 }
150 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
EthSwt_43_NETC_schm_read_msr(void)151 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
152 {
153 mrs r0, CPSR
154 }
155 #else
EthSwt_43_NETC_schm_read_msr(void)156 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
157 {
158 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
159 mrs r0, BASEPRI
160 #else
161 mrs r0, PRIMASK
162 #endif
163 }
164 #endif
165 #else
166 #ifdef MCAL_PLATFORM_S12
EthSwt_43_NETC_schm_read_msr(void)167 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
168 {
169 tfr ccr, d6
170 }
171 #else
EthSwt_43_NETC_schm_read_msr(void)172 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
173 {
174 mfmsr r3
175 }
176 #endif
177 #endif
178 #endif /*#ifdef GHS||CW*/
179
180 #ifdef _DIABDATA_C_S32ZE_
181 /**
182 * @brief This function returns the MSR register value (32 bits).
183 * @details This function returns the MSR register value (32 bits).
184 *
185 * @param[in] void No input parameters
186 * @return uint32 msr This function returns the MSR register value (32 bits).
187 *
188 * @pre None
189 * @post None
190 *
191 */
192 #ifdef MCAL_PLATFORM_ARM
EthSwt_43_NETC_schm_read_msr(void)193 uint32 EthSwt_43_NETC_schm_read_msr(void)
194 {
195 register uint32 reg_tmp;
196 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
197 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
198 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
199 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
200 #else
201 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
202 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
203 #else
204 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
205 #endif
206 #endif
207 return (uint32)reg_tmp;
208 }
209 #else
EthSwt_43_NETC_schm_read_msr(void)210 ASM_KEYWORD uint32 EthSwt_43_NETC_schm_read_msr(void)
211 {
212 mfmsr r3
213 }
214 #endif /* MCAL_PLATFORM_ARM */
215
216 #endif /* _DIABDATA_C_S32ZE_*/
217
218 #ifdef _COSMIC_C_S32ZE_
219 /*================================================================================================*/
220 /**
221 * @brief This function returns the MSR register value (32 bits).
222 * @details This function returns the MSR register value (32 bits).
223 *
224 * @param[in] void No input parameters
225 * @return uint32 msr This function returns the MSR register value (32 bits).
226 *
227 * @pre None
228 * @post None
229 *
230 */
231
232 #ifdef MCAL_PLATFORM_S12
233 #define EthSwt_43_NETC_schm_read_msr() ASM_KEYWORD("tfr ccr, d6")
234 #else
235 #define EthSwt_43_NETC_schm_read_msr() ASM_KEYWORD("mfmsr r3")
236 #endif
237
238 #endif /*Cosmic compiler only*/
239
240
241 #ifdef _HITECH_C_S32ZE_
242 /*================================================================================================*/
243 /**
244 * @brief This function returns the MSR register value (32 bits).
245 * @details This function returns the MSR register value (32 bits).
246 *
247 * @param[in] void No input parameters
248 * @return uint32 msr This function returns the MSR register value (32 bits).
249 *
250 * @pre None
251 * @post None
252 *
253 */
EthSwt_43_NETC_schm_read_msr(void)254 uint32 EthSwt_43_NETC_schm_read_msr(void)
255 {
256 uint32 result;
257 __asm volatile("mfmsr %0" : "=r" (result) :);
258 return result;
259 }
260
261 #endif /*HighTec compiler only*/
262 /*================================================================================================*/
263 #ifdef _LINARO_C_S32ZE_
264 /**
265 * @brief This function returns the MSR register value (32 bits).
266 * @details This function returns the MSR register value (32 bits).
267 *
268 * @param[in] void No input parameters
269 * @return uint32 msr This function returns the MSR register value (32 bits).
270 *
271 * @pre None
272 * @post None
273 *
274 */
EthSwt_43_NETC_schm_read_msr(void)275 uint32 EthSwt_43_NETC_schm_read_msr(void)
276 {
277 register uint32 reg_tmp;
278 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
279 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
280 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
281 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
282 #else
283 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
284 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
285 #else
286 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
287 #endif
288 #endif
289 return (uint32)reg_tmp;
290 }
291 #endif /* _LINARO_C_S32ZE_*/
292 /*================================================================================================*/
293
294 #ifdef _ARM_DS5_C_S32ZE_
295 /**
296 * @brief This function returns the MSR register value (32 bits).
297 * @details This function returns the MSR register value (32 bits).
298 *
299 * @param[in] void No input parameters
300 * @return uint32 msr This function returns the MSR register value (32 bits).
301 *
302 * @pre None
303 * @post None
304 *
305 */
EthSwt_43_NETC_schm_read_msr(void)306 uint32 EthSwt_43_NETC_schm_read_msr(void)
307 {
308 register uint32 reg_tmp;
309 #if (MCAL_PLATFORM_ARM == MCAL_ARM_AARCH64)
310 __asm volatile( " mrs %x0, DAIF " : "=r" (reg_tmp) );
311 #elif (MCAL_PLATFORM_ARM == MCAL_ARM_RARCH)
312 __asm volatile( " mrs %0, CPSR " : "=r" (reg_tmp) );
313 #else
314 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
315 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
316 #else
317 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
318 #endif
319 #endif
320 return (uint32)reg_tmp;
321 }
322 #endif /* _ARM_DS5_C_S32ZE_ */
323
324 #ifdef _IAR_C_S32ZE_
325 /**
326 * @brief This function returns the MSR register value (32 bits).
327 * @details This function returns the MSR register value (32 bits).
328 *
329 * @param[in] void No input parameters
330 * @return uint32 msr This function returns the MSR register value (32 bits).
331 *
332 * @pre None
333 * @post None
334 *
335 */
EthSwt_43_NETC_schm_read_msr(void)336 uint32 EthSwt_43_NETC_schm_read_msr(void)
337 {
338 register uint32 reg_tmp;
339
340 #if ((defined MCAL_ENABLE_USER_MODE_SUPPORT)&&(!defined MCAL_PLATFORM_ARM_M0PLUS))
341 __asm volatile( " mrs %0, basepri " : "=r" (reg_tmp) );
342 #else
343 __asm volatile( " mrs %0, primask " : "=r" (reg_tmp) );
344 #endif
345
346 return (uint32)reg_tmp;
347 }
348 #endif /* _IAR_C_S32ZE_ */
349
350 #define RTE_STOP_SEC_CODE
351 #include "Rte_MemMap.h"
352
353 /*==================================================================================================
354 * GLOBAL FUNCTIONS
355 ==================================================================================================*/
356 #define RTE_START_SEC_CODE
357 #include "Rte_MemMap.h"
358
359
360 #ifdef MCAL_TESTING_ENVIRONMENT
361 /**
362 @brief This function checks that all entered exclusive areas were also exited.
363 @details This function checks that all entered exclusive areas were also exited. The check
364 is done by verifying that all reentry_guard_* static variables are back to the
365 zero value.
366
367 @param[in] void No input parameters
368 @return void This function does not return a value. Test asserts are used instead.
369
370 @pre None
371 @post None
372
373 @remarks Covers
374 @remarks Implements
375 */
SchM_Check_ethswt_43_netc(void)376 void SchM_Check_ethswt_43_netc(void)
377 {
378 uint32 u32CoreId = (uint32)OsIf_GetCoreID();
379
380
381 }
382 #endif /*MCAL_TESTING_ENVIRONMENT*/
383
384 #define RTE_STOP_SEC_CODE
385 #include "Rte_MemMap.h"
386
387 #ifdef __cplusplus
388 }
389 #endif
390
391 /** @} */
392
