1 /*
2 * Copyright 2021-2022 NXP
3 *
4 * SPDX-License-Identifier: BSD-3-Clause
5 */
6 /**
7 * @file Clock_Ip_Monitor.c
8 * @version 0.9.0
9 *
10 * @brief CLOCK driver implementations.
11 * @details CLOCK driver implementations.
12 *
13 * @addtogroup CLOCK_DRIVER Clock Ip Driver
14 * @{
15 */
16
17
18 #ifdef __cplusplus
19 extern "C"{
20 #endif
21
22
23 /*==================================================================================================
24 * INCLUDE FILES
25 * 1) system and project includes
26 * 2) needed interfaces from external units
27 * 3) internal and external interfaces from this unit
28 ==================================================================================================*/
29
30 #include "Clock_Ip_Private.h"
31 #include "SchM_Mcu.h"
32
33 /*==================================================================================================
34 SOURCE FILE VERSION INFORMATION
35 ==================================================================================================*/
36 #define CLOCK_IP_MONITOR_VENDOR_ID_C 43
37 #define CLOCK_IP_MONITOR_AR_RELEASE_MAJOR_VERSION_C 4
38 #define CLOCK_IP_MONITOR_AR_RELEASE_MINOR_VERSION_C 7
39 #define CLOCK_IP_MONITOR_AR_RELEASE_REVISION_VERSION_C 0
40 #define CLOCK_IP_MONITOR_SW_MAJOR_VERSION_C 0
41 #define CLOCK_IP_MONITOR_SW_MINOR_VERSION_C 9
42 #define CLOCK_IP_MONITOR_SW_PATCH_VERSION_C 0
43
44 /*==================================================================================================
45 * FILE VERSION CHECKS
46 ==================================================================================================*/
47 /* Check if Clock_Ip_Monitor.c file and Clock_Ip_Private.h file are of the same vendor */
48 #if (CLOCK_IP_MONITOR_VENDOR_ID_C != CLOCK_IP_PRIVATE_VENDOR_ID)
49 #error "Clock_Ip_Monitor.c and Clock_Ip_Private.h have different vendor ids"
50 #endif
51
52 /* Check if Clock_Ip_Monitor.c file and Clock_Ip_Private.h file are of the same Autosar version */
53 #if ((CLOCK_IP_MONITOR_AR_RELEASE_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MAJOR_VERSION) || \
54 (CLOCK_IP_MONITOR_AR_RELEASE_MINOR_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_MINOR_VERSION) || \
55 (CLOCK_IP_MONITOR_AR_RELEASE_REVISION_VERSION_C != CLOCK_IP_PRIVATE_AR_RELEASE_REVISION_VERSION) \
56 )
57 #error "AutoSar Version Numbers of Clock_Ip_Monitor.c and Clock_Ip_Private.h are different"
58 #endif
59
60 /* Check if Clock_Ip_Monitor.c file and Clock_Ip_Private.h file are of the same Software version */
61 #if ((CLOCK_IP_MONITOR_SW_MAJOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MAJOR_VERSION) || \
62 (CLOCK_IP_MONITOR_SW_MINOR_VERSION_C != CLOCK_IP_PRIVATE_SW_MINOR_VERSION) || \
63 (CLOCK_IP_MONITOR_SW_PATCH_VERSION_C != CLOCK_IP_PRIVATE_SW_PATCH_VERSION) \
64 )
65 #error "Software Version Numbers of Clock_Ip_Monitor.c and Clock_Ip_Private.h are different"
66 #endif
67 #ifndef DISABLE_MCAL_INTERMODULE_ASR_CHECK
68 /* Check if Clock_Ip_Monitor.c file and SchM_Mcu.h file are of the same Autosar version */
69 #if ((CLOCK_IP_MONITOR_AR_RELEASE_MAJOR_VERSION_C != SCHM_MCU_AR_RELEASE_MAJOR_VERSION) || \
70 (CLOCK_IP_MONITOR_AR_RELEASE_MINOR_VERSION_C != SCHM_MCU_AR_RELEASE_MINOR_VERSION))
71 #error "AutoSar Version Numbers of Clock_Ip_Monitor.c and SchM_Mcu.h are different"
72 #endif
73 #endif
74
75 /*==================================================================================================
76 * LOCAL TYPEDEFS (STRUCTURES, UNIONS, ENUMS)
77 ==================================================================================================*/
78
79 /*==================================================================================================
80 * LOCAL MACROS
81 ==================================================================================================*/
82 #ifdef CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF
83 #define CLOCK_IP_CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER 10U
84 #define CLOCK_IP_CMU_FC_VAR 3U
85 #define CLOCK_IP_CMU_REFERENCE_CLOCK_VARIATION 33U
86 #define CLOCK_IP_CMU_MONITORED_CLOCK_VARIATION 11U
87 #define CLOCK_IP_DIVIDE_BY_1000 1000U
88
89 #if defined(CLOCK_IP_FEATURE_OFFSET_REFERENCE_COUNT_FORMULA1)
90 #define CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA1 CLOCK_IP_FEATURE_OFFSET_REFERENCE_COUNT_FORMULA1
91 #else
92 #define CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA1 1U
93 #endif
94
95 #if defined(CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA1)
96 #define CLOCK_IP_MULTIPLIER_REFERENCE_COUNT_FORMULA1 CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA1
97 #else
98 #define CLOCK_IP_MULTIPLIER_REFERENCE_COUNT_FORMULA1 3U
99 #endif
100
101 #if defined(CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA2)
102 #define CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA2 CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA2
103 #else
104 #define CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA2 9U
105 #endif
106
107 #if defined(CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA2)
108 #define CLOCK_IP_MULTIPLIER_REFERENCE_COUNT_FORMULA2 CLOCK_IP_FEATURE_MULTIPLIER_REFERENCE_COUNT_FORMULA2
109 #else
110 #define CLOCK_IP_MULTIPLIER_REFERENCE_COUNT_FORMULA2 5U
111 #endif
112
113 #endif
114
115 /*==================================================================================================
116 * LOCAL CONSTANTS
117 ==================================================================================================*/
118
119 /*==================================================================================================
120 * LOCAL VARIABLES
121 ==================================================================================================*/
122
123 /* Clock start initialized section data */
124 #define MCU_START_SEC_VAR_CLEARED_32
125 #include "Mcu_MemMap.h"
126
127 #if !(defined(CLOCK_IP_REGISTER_VALUES_OPTIMIZATION) && (CLOCK_IP_REGISTER_VALUES_OPTIMIZATION == STD_ON))
128 static uint32 HashCmu[CLOCK_IP_CMUS_NO];
129 #endif
130
131 /* Clock stop initialized section data */
132 #define MCU_STOP_SEC_VAR_CLEARED_32
133 #include "Mcu_MemMap.h"
134
135 /*==================================================================================================
136 * GLOBAL VARIABLES
137 ==================================================================================================*/
138
139 /*==================================================================================================
140 * LOCAL FUNCTION PROTOTYPES
141 ==================================================================================================*/
142 /* Clock start section code */
143 #define MCU_START_SEC_CODE
144
145 #include "Mcu_MemMap.h"
146
147 /* TODO ARTD-738 Implement CMU in Clock_Ip driver */
148
149 static void Clock_Ip_ClockMonitorEmpty(Clock_Ip_CmuConfigType const* Config);
150 static void Clock_Ip_ClockMonitorEmpty_Set(Clock_Ip_CmuConfigType const* Config, uint32 Index);
151 static void Clock_Ip_ClockMonitorEmpty_Disable(Clock_Ip_NameType Name);
152 static void Clock_Ip_ClockMonitorEmpty_ClearStatus(Clock_Ip_NameType Name);
153 static Clock_Ip_CmuStatusType Clock_Ip_ClockMonitorEmpty_GetStatus(Clock_Ip_NameType Name);
154
155 #ifdef CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF
156 static void Clock_Ip_ResetCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const* Config);
157 #if !(defined(CLOCK_IP_REGISTER_VALUES_OPTIMIZATION) && (CLOCK_IP_REGISTER_VALUES_OPTIMIZATION == STD_ON))
158 static void Clock_Ip_SetCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const* Config, uint32 Index);
159 #endif
160 static void Clock_Ip_DisableCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name);
161 static void Clock_Ip_ClearStatusCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name);
162 static Clock_Ip_CmuStatusType Clock_Ip_GetStatusCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name);
163 static void Clock_Ip_EnableCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const* Config);
164 #endif
165
166
167 /* Clock stop section code */
168 #define MCU_STOP_SEC_CODE
169
170 #include "Mcu_MemMap.h"
171
172 /*==================================================================================================
173 * LOCAL FUNCTIONS
174 ==================================================================================================*/
175
176 /* Clock start section code */
177 #define MCU_START_SEC_CODE
178
179 #include "Mcu_MemMap.h"
180
Clock_Ip_ClockMonitorEmpty(Clock_Ip_CmuConfigType const * Config)181 static void Clock_Ip_ClockMonitorEmpty(Clock_Ip_CmuConfigType const* Config)
182 {
183 (void)Config;
184 /* No implementation */
185 }
186
Clock_Ip_ClockMonitorEmpty_Set(Clock_Ip_CmuConfigType const * Config,uint32 Index)187 static void Clock_Ip_ClockMonitorEmpty_Set(Clock_Ip_CmuConfigType const* Config, uint32 Index)
188 {
189 (void)Config;
190 (void)Index;
191 /* No implementation */
192 }
193
Clock_Ip_ClockMonitorEmpty_Disable(Clock_Ip_NameType Name)194 static void Clock_Ip_ClockMonitorEmpty_Disable(Clock_Ip_NameType Name)
195 {
196 (void)Name;
197 /* No implementation */
198 }
199
Clock_Ip_ClockMonitorEmpty_ClearStatus(Clock_Ip_NameType Name)200 static void Clock_Ip_ClockMonitorEmpty_ClearStatus(Clock_Ip_NameType Name)
201 {
202 (void)Name;
203 /* No implementation */
204 }
205
Clock_Ip_ClockMonitorEmpty_GetStatus(Clock_Ip_NameType Name)206 static Clock_Ip_CmuStatusType Clock_Ip_ClockMonitorEmpty_GetStatus(Clock_Ip_NameType Name)
207 {
208 (void)Name;
209 /* No implementation */
210 return CLOCK_IP_CMU_STATUS_UNDEFINED;
211 }
212 #if (defined(CLOCK_IP_REGISTER_VALUES_OPTIMIZATION) && (CLOCK_IP_REGISTER_VALUES_OPTIMIZATION == STD_ON))
213 /* Set clock monitor via register value configuration */
Clock_Ip_SetClockMonitorRegisterValues(Clock_Ip_CmuConfigType const * Config,uint32 Index)214 static void Clock_Ip_SetClockMonitorRegisterValues(Clock_Ip_CmuConfigType const* Config, uint32 Index)
215 {
216 (void)Index;
217 Clock_Ip_WriteRegisterValues(&Config->Indexes);
218 }
219 #endif
220
221 #ifdef CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF
Clock_Ip_DisableCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name)222 static void Clock_Ip_DisableCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name)
223 {
224 const Clock_Ip_CmuInfoType * CmuInformation = &Clock_Ip_axCmuInfo[Clock_Ip_au8ClockFeatures[Name][CLOCK_IP_CMU_INDEX]];
225 Clock_Ip_ClockMonitorType* const CmuFc = CmuInformation->CmuInstance;
226
227 boolean TimeoutOccurred = FALSE;
228 uint32 StartTime;
229 uint32 ElapsedTime;
230 uint32 TimeoutTicks;
231 uint32 FrequencyCheckStatus;
232
233 #if (defined (CLOCK_IP_S32K118) || defined(CLOCK_IP_S32K116))
234 if(0U == ((IP_PCC->PCCn[62] & PCC_PCCn_CGC_MASK) >> PCC_PCCn_CGC_SHIFT))
235 {
236 #if defined(CLOCK_IP_HAS_FIRC_MON1_CLK)
237 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
238 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
239 OsIf_Trusted_Call(Clock_Ip_EnableCmu0Gate_TrustedCall);
240 #else
241 Clock_Ip_EnableCmu0Gate_TrustedCall();
242 #endif
243 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
244 #endif
245 /* Enable clock gate for CMU0 device */
246 IP_PCC->PCCn[62] |= PCC_PCCn_CGC_MASK;
247 }
248
249 if(0U == ((IP_PCC->PCCn[63] & PCC_PCCn_CGC_MASK) >> PCC_PCCn_CGC_SHIFT))
250 {
251 #if defined(CLOCK_IP_HAS_FIRC_MON2_CLK)
252 #ifdef CLOCK_IP_ENABLE_USER_MODE_SUPPORT
253 #if (STD_ON == CLOCK_IP_ENABLE_USER_MODE_SUPPORT)
254 OsIf_Trusted_Call(Clock_Ip_EnableCmu1Gate_TrustedCall);
255 #else
256 Clock_Ip_EnableCmu1Gate_TrustedCall();
257 #endif
258 #endif /* CLOCK_IP_ENABLE_USER_MODE_SUPPORT */
259 #endif
260 /* Enable clock gate for CMU1 device */
261 IP_PCC->PCCn[63] |= PCC_PCCn_CGC_MASK;
262 }
263 #endif
264
265 /* Enter critical region*/
266 SchM_Enter_Mcu_MCU_EXCLUSIVE_AREA_01();
267 /* Only disable frequency check if it is enabled */
268 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK))
269 {
270 Clock_Ip_StartTimeout(&StartTime, &ElapsedTime, &TimeoutTicks, CLOCK_IP_TIMEOUT_VALUE_US);
271 /* Wait for frequency check to be running. */
272 do
273 {
274 FrequencyCheckStatus = (CmuFc->SR & CMU_FC_SR_RS_MASK);
275 TimeoutOccurred = Clock_Ip_TimeoutExpired(&StartTime, &ElapsedTime, TimeoutTicks);
276 }
277 while((CLOCK_IP_CMU_FREQUENCY_CHECK_STOPPED == FrequencyCheckStatus) && (!TimeoutOccurred));
278
279 /* timeout notification */
280 if (TimeoutOccurred)
281 {
282 /* Report timeout error */
283 Clock_Ip_ReportClockErrors(CLOCK_IP_REPORT_TIMEOUT_ERROR, Name);
284 }
285 else
286 {
287 /* Disable frequency check */
288 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK;
289
290 /* Disable interupts */
291 CmuFc->IER &= ~(CMU_FC_IER_FLLIE_MASK | CMU_FC_IER_FHHIE_MASK | CMU_FC_IER_FLLAIE_MASK | CMU_FC_IER_FHHAIE_MASK);
292
293 /* Clear flags */
294 CmuFc->SR |= (CMU_FC_SR_FLL_MASK | CMU_FC_SR_FHH_MASK);
295 }
296 }
297 else
298 {
299 /* Disable interupts */
300 CmuFc->IER &= ~(CMU_FC_IER_FLLIE_MASK | CMU_FC_IER_FHHIE_MASK | CMU_FC_IER_FLLAIE_MASK | CMU_FC_IER_FHHAIE_MASK);
301
302 /* Clear flags */
303 CmuFc->SR |= (CMU_FC_SR_FLL_MASK | CMU_FC_SR_FHH_MASK);
304 }
305
306 /* Exit critical region. */
307 SchM_Exit_Mcu_MCU_EXCLUSIVE_AREA_01();
308 }
309
310 /* Reset CMU register */
Clock_Ip_ResetCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const * Config)311 static void Clock_Ip_ResetCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const* Config)
312 {
313 Clock_Ip_DisableCmuFcFceRefCntLfrefHfref(Config->Name);
314 }
315
316 #if !(defined(CLOCK_IP_REGISTER_VALUES_OPTIMIZATION) && (CLOCK_IP_REGISTER_VALUES_OPTIMIZATION == STD_ON))
Clock_Ip_SetCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const * Config,uint32 Index)317 static void Clock_Ip_SetCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const* Config, uint32 Index)
318 {
319 const Clock_Ip_CmuInfoType * CmuInformation = &Clock_Ip_axCmuInfo[Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_CMU_INDEX]];
320 Clock_Ip_ClockMonitorType* const CmuFc = CmuInformation->CmuInstance;
321
322 uint32 ReferenceClk = 0U;
323 uint32 MonitoredClk = 0U;
324 uint32 BusClk = 0U;
325 uint32 RefCount = 0U;
326 uint32 HfRef = 0U;
327 uint32 LfRef = 0U;
328 uint32 Cmp1;
329 uint32 Cmp2;
330 uint32 DivideBy;
331 uint32 DividerResult;
332 uint32 ModuloValue;
333
334 /* Do not calculate cmu values if these values are already calculated and written in hw registers */
335 if (HashCmu[Index] != ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->MonitoredClockFrequency) ^ ((uint32)Config->Name))))
336 {
337 HashCmu[Index] = ((((uint32)Config->Enable) ^ ((uint32)Config->Interrupt) ^ ((uint32)Config->MonitoredClockFrequency) ^ ((uint32)Config->Name)));
338
339 ReferenceClk = Clock_Ip_pxConfig->ConfiguredFrequencies[Clock_Ip_FreqIds[CmuInformation->Reference]].ConfiguredFrequencyValue / CLOCK_IP_DIVIDE_BY_1000;
340 BusClk = Clock_Ip_pxConfig->ConfiguredFrequencies[Clock_Ip_FreqIds[CmuInformation->Bus]].ConfiguredFrequencyValue / CLOCK_IP_DIVIDE_BY_1000;
341 MonitoredClk = Config->MonitoredClockFrequency / CLOCK_IP_DIVIDE_BY_1000;
342
343 #if (defined(CLOCK_IP_DEV_ERROR_DETECT) && (CLOCK_IP_DEV_ERROR_DETECT == STD_ON))
344 CLOCK_IP_DEV_ASSERT(ReferenceClk != 0U);
345 CLOCK_IP_DEV_ASSERT(BusClk != 0U);
346 CLOCK_IP_DEV_ASSERT(MonitoredClk != 0U);
347 #endif
348 /* Avoid divide by zero */
349 if ((ReferenceClk != 0U) && (BusClk != 0U) && (MonitoredClk != 0U))
350 {
351 /* Cmp1 = ceiling of (3 * fRef/ fBus) */
352 Cmp1 = CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA1 + (uint32)((CLOCK_IP_MULTIPLIER_REFERENCE_COUNT_FORMULA1 * ReferenceClk) / BusClk);
353 /* Cmp2 = ceiling of (8 + (5 * fRef / fMonitor)) */
354 Cmp2 = CLOCK_IP_OFFSET_REFERENCE_COUNT_FORMULA2 + (uint32)((CLOCK_IP_MULTIPLIER_REFERENCE_COUNT_FORMULA2 * ReferenceClk) / MonitoredClk);
355
356 /* REF count = Max(cmp1,cmp2) */
357 RefCount = (Cmp1 > Cmp2) ? Cmp1 : Cmp2;
358
359
360 /* (fMonitoredClk mul_by (1000U plus CLOCK_IP_CMU_MONITORED_CLOCK_VARIATION)) divide_by (fReferenceClk mul_by (1000U minus CLOCK_IP_CMU_REFERENCE_CLOCK_VARIATION)) plus CLOCK_IP_CMU_FC_VAR plus 1U */
361 HfRef = MonitoredClk * (1000U + CLOCK_IP_CMU_MONITORED_CLOCK_VARIATION) * RefCount;
362 DivideBy = ReferenceClk * (1000U - CLOCK_IP_CMU_REFERENCE_CLOCK_VARIATION);
363 DividerResult = (uint32) HfRef / DivideBy;
364 ModuloValue = HfRef - (DivideBy * DividerResult);
365 HfRef = (DividerResult * CLOCK_IP_CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER) + ((uint32)((ModuloValue * CLOCK_IP_CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER) / DivideBy)) + (CLOCK_IP_CMU_FC_VAR + 1U);
366
367 /* (fMonitoredClk mul_by (1000U minus CLOCK_IP_CMU_MONITORED_CLOCK_VARIATION)) divide_by (fReferenceClk mul_by (1000U plus CLOCK_IP_CMU_REFERENCE_CLOCK_VARIATION)) minus CLOCK_IP_CMU_FC_VAR */
368 LfRef = MonitoredClk * (1000U - CLOCK_IP_CMU_MONITORED_CLOCK_VARIATION) * RefCount;
369 DivideBy = ReferenceClk * (1000U + CLOCK_IP_CMU_REFERENCE_CLOCK_VARIATION);
370 DividerResult = (uint32) LfRef / DivideBy;
371 ModuloValue = LfRef - (DivideBy * DividerResult);
372 LfRef = (DividerResult * CLOCK_IP_CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER) + ((uint32)((ModuloValue * CLOCK_IP_CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER) / DivideBy)) - CLOCK_IP_CMU_FC_VAR;
373
374
375 /* Set reference counter */
376 CmuFc->RCCR = RefCount * CLOCK_IP_CMU_REFERENCE_COUNTER_MINIMUM_VALUE_MULTIPLIER;
377
378 /* Set high limit */
379 CmuFc->HTCR = HfRef;
380
381 /* Set low limit */
382 CmuFc->LTCR = LfRef;
383 }
384 }
385
386 /* Enable/disable interrupts */
387 CmuFc->IER = Config->Interrupt;
388 }
389 #endif
390
Clock_Ip_ClearStatusCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name)391 static void Clock_Ip_ClearStatusCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name)
392 {
393 const Clock_Ip_CmuInfoType * CmuInformation = &Clock_Ip_axCmuInfo[Clock_Ip_au8ClockFeatures[Name][CLOCK_IP_CMU_INDEX]];
394 Clock_Ip_ClockMonitorType* const CmuFc = CmuInformation->CmuInstance;
395
396 uint32 CmuIsrValue;
397
398 /* Read flags */
399 CmuIsrValue = CmuFc->SR & CLOCK_IP_CMU_ISR_MASK;
400
401 /* Clear flags */
402 CmuFc->SR = CmuIsrValue;
403 }
404
Clock_Ip_GetStatusCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name)405 static Clock_Ip_CmuStatusType Clock_Ip_GetStatusCmuFcFceRefCntLfrefHfref(Clock_Ip_NameType Name)
406 {
407 const Clock_Ip_CmuInfoType * CmuInformation = &Clock_Ip_axCmuInfo[Clock_Ip_au8ClockFeatures[Name][CLOCK_IP_CMU_INDEX]];
408 const Clock_Ip_ClockMonitorType* CmuFc = CmuInformation->CmuInstance;
409
410 Clock_Ip_CmuStatusType Status = CLOCK_IP_CMU_STATUS_UNDEFINED;
411 uint32 CmuIerValue;
412 uint32 CmuIsrValue;
413
414
415 /* Read flags */
416 CmuIsrValue = CmuFc->SR & CLOCK_IP_CMU_ISR_MASK;
417
418 /* Read interrupt enable */
419 CmuIerValue = CmuFc->IER & CLOCK_IP_CMU_ISR_MASK;
420
421 CmuIsrValue = CmuIsrValue & CmuIerValue;
422
423
424 /* Gheck flash if frequency check is enabled */
425 if (CLOCK_IP_CMU_FREQUENCY_CHECK_ENABLED == (CmuFc->GCR & CMU_FC_GCR_FCE_MASK))
426 {
427 if ( ( CMU_FC_SR_FHH_MASK == (CmuIsrValue & CMU_FC_SR_FHH_MASK) ) )
428 {
429 Status = CLOCK_IP_CMU_HIGH_FREQ;
430 }
431 else if ( CMU_FC_SR_FLL_MASK == (CmuIsrValue & CMU_FC_SR_FLL_MASK) )
432 {
433 Status = CLOCK_IP_CMU_LOW_FREQ;
434 }
435 else
436 {
437 Status = CLOCK_IP_CMU_IN_RANGE;
438 }
439 }
440
441 return Status;
442
443 }
Clock_Ip_EnableCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const * Config)444 static void Clock_Ip_EnableCmuFcFceRefCntLfrefHfref(Clock_Ip_CmuConfigType const* Config)
445 {
446 const Clock_Ip_CmuInfoType *CmuInformation = &Clock_Ip_axCmuInfo[Clock_Ip_au8ClockFeatures[Config->Name][CLOCK_IP_CMU_INDEX]];
447 Clock_Ip_ClockMonitorType* const CmuFc = CmuInformation->CmuInstance;
448
449 /* Enable cmu */
450 if (Config->Enable != 0U)
451 {
452 CmuFc->GCR |= CMU_FC_GCR_FCE_MASK;
453 }
454 else
455 {
456 CmuFc->GCR &= ~CMU_FC_GCR_FCE_MASK;
457 }
458 }
459
460 #endif
461
462 /*==================================================================================================
463 * GLOBAL FUNCTIONS
464 ==================================================================================================*/
465
466 #if CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE > 0U
467
Clock_Ip_CMU_GetInterruptStatus(uint8 IndexCmu)468 uint32 Clock_Ip_CMU_GetInterruptStatus(uint8 IndexCmu)
469 {
470 uint32 CmuIsrValue;
471
472 /* Read flags */
473 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK;
474 return CmuIsrValue;
475 }
476
477 /**
478 * @brief This function clear the CMU interrupt flag from CMU module.
479 * @details Called by RGM ISR routine when a user notification for CMU FCCU events is configured
480 *
481 * @return void
482 *
483 * @implements Clock_Ip_CMU_ClockFailInt_Activity
484 *
485 */
Clock_Ip_CMU_ClockFailInt(void)486 void Clock_Ip_CMU_ClockFailInt(void)
487 {
488 uint32 CmuIerValue;
489 uint32 CmuIsrValue;
490 uint32 IndexCmu;
491
492 for (IndexCmu = 0U; IndexCmu < CLOCK_IP_CMU_INSTANCES_ARRAY_SIZE; IndexCmu++)
493 {
494 /* Check whether driver is initialized */
495 if(NULL_PTR != Clock_Ip_pxConfig)
496 {
497 /* Read flags */
498 CmuIsrValue = Clock_Ip_apxCmu[IndexCmu]->SR & CLOCK_IP_CMU_ISR_MASK;
499 /* Read interrupt enable */
500 CmuIerValue = Clock_Ip_apxCmu[IndexCmu]->IER & CLOCK_IP_CMU_ISR_MASK;
501 /* Filter all interrupts that are not enabled from cmuIsrValue */
502 CmuIsrValue = CmuIsrValue & CmuIerValue;
503
504 /* If at least one interrupt has been triggered */
505 if (CmuIsrValue != 0U)
506 {
507 /* Clear status flag */
508 Clock_Ip_apxCmu[IndexCmu]->SR = CmuIsrValue;
509 #ifdef CLOCK_IP_CMU_FCCU_NOTIFICATION
510 CLOCK_IP_CMU_FCCU_NOTIFICATION(Clock_Ip_aeCmuNames[IndexCmu]);
511 #else
512 Clock_Ip_ReportClockErrors(CLOCK_IP_CMU_ERROR, Clock_Ip_aeCmuNames[IndexCmu]);
513 #endif
514 }
515 }
516 }
517 }
518 #endif
519
520
521 /* Clock stop section code */
522 #define MCU_STOP_SEC_CODE
523
524 #include "Mcu_MemMap.h"
525
526 /*==================================================================================================
527 * GLOBAL CONSTANTS
528 ==================================================================================================*/
529
530 /* Clock start constant section data */
531 #define MCU_START_SEC_CONST_UNSPECIFIED
532
533 #include "Mcu_MemMap.h"
534
535 const Clock_Ip_ClockMonitorCallbackType Clock_Ip_axCmuCallbacks[CLOCK_IP_CMU_CALLBACKS_COUNT] =
536 {
537 {
538 Clock_Ip_ClockMonitorEmpty, /* Reset */
539 Clock_Ip_ClockMonitorEmpty_Set, /* Set */
540 Clock_Ip_ClockMonitorEmpty_Disable, /* Disable */
541 Clock_Ip_ClockMonitorEmpty_ClearStatus, /* Clear */
542 Clock_Ip_ClockMonitorEmpty_GetStatus, /* Get status */
543 Clock_Ip_ClockMonitorEmpty, /* Enable */
544 },
545 #ifdef CLOCK_IP_CMU_FC_FCE_REF_CNT_LFREF_HFREF
546 {
547 Clock_Ip_ResetCmuFcFceRefCntLfrefHfref, /* Reset */
548 #if (defined(CLOCK_IP_REGISTER_VALUES_OPTIMIZATION) && (CLOCK_IP_REGISTER_VALUES_OPTIMIZATION == STD_ON))
549 Clock_Ip_SetClockMonitorRegisterValues, /* Set */
550 #else
551 Clock_Ip_SetCmuFcFceRefCntLfrefHfref, /* Set */
552 #endif
553 Clock_Ip_DisableCmuFcFceRefCntLfrefHfref, /* Disable */
554 Clock_Ip_ClearStatusCmuFcFceRefCntLfrefHfref, /* Clear */
555 Clock_Ip_GetStatusCmuFcFceRefCntLfrefHfref, /* Get status */
556 Clock_Ip_EnableCmuFcFceRefCntLfrefHfref, /* Enable */
557 },
558 #endif
559
560
561 };
562
563 /* Clock stop constant section data */
564 #define MCU_STOP_SEC_CONST_UNSPECIFIED
565
566 #include "Mcu_MemMap.h"
567
568
569 #ifdef __cplusplus
570 }
571 #endif
572
573 /** @} */
574
575
