1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_PIT.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_PIT 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_PIT_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_PIT_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- PIT Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer 68 * @{ 69 */ 70 71 /** PIT - Size of Registers Arrays */ 72 #define PIT_TIMER_COUNT 7u 73 74 /** PIT - Register Layout Typedef */ 75 typedef struct { 76 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */ 77 uint8_t RESERVED_0[220]; 78 __I uint32_t LTMR64H; /**< PIT Upper Lifetime Timer Register, offset: 0xE0 */ 79 __I uint32_t LTMR64L; /**< PIT Lower Lifetime Timer Register, offset: 0xE4 */ 80 uint8_t RESERVED_1[24]; 81 struct { /* offset: 0x100, array step: 0x10 */ 82 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */ 83 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */ 84 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */ 85 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */ 86 } CHANNEL[PIT_TIMER_COUNT]; 87 } PIT_Type, *PIT_MemMapPtr; 88 89 /** Number of instances of the PIT module. */ 90 #define PIT_INSTANCE_COUNT (12u) 91 92 /* PIT - Peripheral instance base addresses */ 93 /** Peripheral CE_PIT_0 base address */ 94 #define IP_CE_PIT_0_BASE (0x44A80000u) 95 /** Peripheral CE_PIT_0 base pointer */ 96 #define IP_CE_PIT_0 ((PIT_Type *)IP_CE_PIT_0_BASE) 97 /** Peripheral CE_PIT_1 base address */ 98 #define IP_CE_PIT_1_BASE (0x44A90000u) 99 /** Peripheral CE_PIT_1 base pointer */ 100 #define IP_CE_PIT_1 ((PIT_Type *)IP_CE_PIT_1_BASE) 101 /** Peripheral CE_PIT_2 base address */ 102 #define IP_CE_PIT_2_BASE (0x44AA0000u) 103 /** Peripheral CE_PIT_2 base pointer */ 104 #define IP_CE_PIT_2 ((PIT_Type *)IP_CE_PIT_2_BASE) 105 /** Peripheral CE_PIT_3 base address */ 106 #define IP_CE_PIT_3_BASE (0x44AB0000u) 107 /** Peripheral CE_PIT_3 base pointer */ 108 #define IP_CE_PIT_3 ((PIT_Type *)IP_CE_PIT_3_BASE) 109 /** Peripheral CE_PIT_4 base address */ 110 #define IP_CE_PIT_4_BASE (0x44AC0000u) 111 /** Peripheral CE_PIT_4 base pointer */ 112 #define IP_CE_PIT_4 ((PIT_Type *)IP_CE_PIT_4_BASE) 113 /** Peripheral CE_PIT_5 base address */ 114 #define IP_CE_PIT_5_BASE (0x44AD0000u) 115 /** Peripheral CE_PIT_5 base pointer */ 116 #define IP_CE_PIT_5 ((PIT_Type *)IP_CE_PIT_5_BASE) 117 /** Peripheral PIT_0 base address */ 118 #define IP_PIT_0_BASE (0x40120000u) 119 /** Peripheral PIT_0 base pointer */ 120 #define IP_PIT_0 ((PIT_Type *)IP_PIT_0_BASE) 121 /** Peripheral PIT_1 base address */ 122 #define IP_PIT_1_BASE (0x40920000u) 123 /** Peripheral PIT_1 base pointer */ 124 #define IP_PIT_1 ((PIT_Type *)IP_PIT_1_BASE) 125 /** Peripheral PIT_4 base address */ 126 #define IP_PIT_4_BASE (0x42120000u) 127 /** Peripheral PIT_4 base pointer */ 128 #define IP_PIT_4 ((PIT_Type *)IP_PIT_4_BASE) 129 /** Peripheral PIT_5 base address */ 130 #define IP_PIT_5_BASE (0x42920000u) 131 /** Peripheral PIT_5 base pointer */ 132 #define IP_PIT_5 ((PIT_Type *)IP_PIT_5_BASE) 133 /** Peripheral RTU0__PIT base address */ 134 #define IP_RTU0__PIT_BASE (0x76150000u) 135 /** Peripheral RTU0__PIT base pointer */ 136 #define IP_RTU0__PIT ((PIT_Type *)IP_RTU0__PIT_BASE) 137 /** Peripheral RTU1__PIT base address */ 138 #define IP_RTU1__PIT_BASE (0x76950000u) 139 /** Peripheral RTU1__PIT base pointer */ 140 #define IP_RTU1__PIT ((PIT_Type *)IP_RTU1__PIT_BASE) 141 /** Array initializer of PIT peripheral base addresses */ 142 #define IP_PIT_BASE_ADDRS { IP_CE_PIT_0_BASE, IP_CE_PIT_1_BASE, IP_CE_PIT_2_BASE, IP_CE_PIT_3_BASE, IP_CE_PIT_4_BASE, IP_CE_PIT_5_BASE, IP_PIT_0_BASE, IP_PIT_1_BASE, IP_PIT_4_BASE, IP_PIT_5_BASE, IP_RTU0__PIT_BASE, IP_RTU1__PIT_BASE } 143 /** Array initializer of PIT peripheral base pointers */ 144 #define IP_PIT_BASE_PTRS { IP_CE_PIT_0, IP_CE_PIT_1, IP_CE_PIT_2, IP_CE_PIT_3, IP_CE_PIT_4, IP_CE_PIT_5, IP_PIT_0, IP_PIT_1, IP_PIT_4, IP_PIT_5, IP_RTU0__PIT, IP_RTU1__PIT } 145 146 /* ---------------------------------------------------------------------------- 147 -- PIT Register Masks 148 ---------------------------------------------------------------------------- */ 149 150 /*! 151 * @addtogroup PIT_Register_Masks PIT Register Masks 152 * @{ 153 */ 154 155 /*! @name MCR - PIT Module Control Register */ 156 /*! @{ */ 157 158 #define PIT_MCR_FRZ_MASK (0x1U) 159 #define PIT_MCR_FRZ_SHIFT (0U) 160 #define PIT_MCR_FRZ_WIDTH (1U) 161 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK) 162 163 #define PIT_MCR_MDIS_MASK (0x2U) 164 #define PIT_MCR_MDIS_SHIFT (1U) 165 #define PIT_MCR_MDIS_WIDTH (1U) 166 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK) 167 /*! @} */ 168 169 /*! @name LTMR64H - PIT Upper Lifetime Timer Register */ 170 /*! @{ */ 171 172 #define PIT_LTMR64H_LTH_MASK (0xFFFFFFFFU) 173 #define PIT_LTMR64H_LTH_SHIFT (0U) 174 #define PIT_LTMR64H_LTH_WIDTH (32U) 175 #define PIT_LTMR64H_LTH(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64H_LTH_SHIFT)) & PIT_LTMR64H_LTH_MASK) 176 /*! @} */ 177 178 /*! @name LTMR64L - PIT Lower Lifetime Timer Register */ 179 /*! @{ */ 180 181 #define PIT_LTMR64L_LTL_MASK (0xFFFFFFFFU) 182 #define PIT_LTMR64L_LTL_SHIFT (0U) 183 #define PIT_LTMR64L_LTL_WIDTH (32U) 184 #define PIT_LTMR64L_LTL(x) (((uint32_t)(((uint32_t)(x)) << PIT_LTMR64L_LTL_SHIFT)) & PIT_LTMR64L_LTL_MASK) 185 /*! @} */ 186 187 /*! @name LDVAL - Timer Load Value Register */ 188 /*! @{ */ 189 190 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU) /* Merged from fields with different position or width, of widths (24, 32), largest definition used */ 191 #define PIT_LDVAL_TSV_SHIFT (0U) 192 #define PIT_LDVAL_TSV_WIDTH (32U) 193 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK) /* Merged from fields with different position or width, of widths (24, 32), largest definition used */ 194 /*! @} */ 195 196 /*! @name CVAL - Current Timer Value Register */ 197 /*! @{ */ 198 199 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU) 200 #define PIT_CVAL_TVL_SHIFT (0U) 201 #define PIT_CVAL_TVL_WIDTH (32U) 202 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK) 203 /*! @} */ 204 205 /*! @name TCTRL - Timer Control Register */ 206 /*! @{ */ 207 208 #define PIT_TCTRL_TEN_MASK (0x1U) 209 #define PIT_TCTRL_TEN_SHIFT (0U) 210 #define PIT_TCTRL_TEN_WIDTH (1U) 211 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK) 212 213 #define PIT_TCTRL_TIE_MASK (0x2U) 214 #define PIT_TCTRL_TIE_SHIFT (1U) 215 #define PIT_TCTRL_TIE_WIDTH (1U) 216 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK) 217 218 #define PIT_TCTRL_CHN_MASK (0x4U) 219 #define PIT_TCTRL_CHN_SHIFT (2U) 220 #define PIT_TCTRL_CHN_WIDTH (1U) 221 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK) 222 /*! @} */ 223 224 /*! @name TFLG - Timer Flag Register */ 225 /*! @{ */ 226 227 #define PIT_TFLG_TIF_MASK (0x1U) 228 #define PIT_TFLG_TIF_SHIFT (0U) 229 #define PIT_TFLG_TIF_WIDTH (1U) 230 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK) 231 /*! @} */ 232 233 /*! 234 * @} 235 */ /* end of group PIT_Register_Masks */ 236 237 /*! 238 * @} 239 */ /* end of group PIT_Peripheral_Access_Layer */ 240 241 #endif /* #if !defined(S32Z2_PIT_H_) */ 242
