1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_EDMA3_TCD.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_EDMA3_TCD 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_EDMA3_TCD_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_EDMA3_TCD_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- EDMA3_TCD Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup EDMA3_TCD_Peripheral_Access_Layer EDMA3_TCD Peripheral Access Layer 68 * @{ 69 */ 70 71 /** EDMA3_TCD - Size of Registers Arrays */ 72 #define EDMA3_TCD_TCD_COUNT 32u 73 74 /** EDMA3_TCD - Register Layout Typedef */ 75 typedef struct { 76 struct { /* offset: 0x0, array step: 0x10000 */ 77 __IO uint32_t CH_CSR; /**< Channel Control and Status, array offset: 0x0, array step: 0x10000 */ 78 __IO uint32_t CH_ES; /**< Channel Error Status, array offset: 0x4, array step: 0x10000 */ 79 __IO uint32_t CH_INT; /**< Channel Interrupt Status, array offset: 0x8, array step: 0x10000 */ 80 __IO uint32_t CH_SBR; /**< Channel System Bus, array offset: 0xC, array step: 0x10000 */ 81 __IO uint32_t CH_PRI; /**< Channel Priority, array offset: 0x10, array step: 0x10000 */ 82 uint8_t RESERVED_0[12]; 83 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x20, array step: 0x10000 */ 84 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x24, array step: 0x10000 */ 85 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x26, array step: 0x10000 */ 86 union { /* offset: 0x28, array step: 0x10000 */ 87 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Transfer Size Without Minor Loop Offsets, array offset: 0x28, array step: 0x10000 */ 88 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Transfer Size with Minor Loop Offsets, array offset: 0x28, array step: 0x10000 */ 89 } NBYTES; 90 __IO uint32_t SLAST_SDA; /**< TCD Last Source Address Adjustment / Store DADDR Address, array offset: 0x2C, array step: 0x10000 */ 91 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x30, array step: 0x10000 */ 92 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x34, array step: 0x10000 */ 93 union { /* offset: 0x36, array step: 0x10000 */ 94 __IO uint16_t CITER_ELINKNO; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x36, array step: 0x10000 */ 95 __IO uint16_t CITER_ELINKYES; /**< TCD Current Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x36, array step: 0x10000 */ 96 } CITER; 97 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment / Scatter Gather Address, array offset: 0x38, array step: 0x10000 */ 98 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x3C, array step: 0x10000 */ 99 union { /* offset: 0x3E, array step: 0x10000 */ 100 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled), array offset: 0x3E, array step: 0x10000 */ 101 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled), array offset: 0x3E, array step: 0x10000 */ 102 } BITER; 103 uint8_t RESERVED_1[65472]; 104 } TCD[EDMA3_TCD_TCD_COUNT]; 105 } EDMA3_TCD_Type, *EDMA3_TCD_MemMapPtr; 106 107 /** Number of instances of the EDMA3_TCD module. */ 108 #define EDMA3_TCD_INSTANCE_COUNT (5u) 109 110 /* EDMA3_TCD - Peripheral instance base addresses */ 111 /** Peripheral EDMA_0_TCD base address */ 112 #define IP_EDMA_0_TCD_BASE (0x40600000u) 113 /** Peripheral EDMA_0_TCD base pointer */ 114 #define IP_EDMA_0_TCD ((EDMA3_TCD_Type *)IP_EDMA_0_TCD_BASE) 115 /** Peripheral EDMA_1_TCD base address */ 116 #define IP_EDMA_1_TCD_BASE (0x40E00000u) 117 /** Peripheral EDMA_1_TCD base pointer */ 118 #define IP_EDMA_1_TCD ((EDMA3_TCD_Type *)IP_EDMA_1_TCD_BASE) 119 /** Peripheral EDMA_4_TCD base address */ 120 #define IP_EDMA_4_TCD_BASE (0x42600000u) 121 /** Peripheral EDMA_4_TCD base pointer */ 122 #define IP_EDMA_4_TCD ((EDMA3_TCD_Type *)IP_EDMA_4_TCD_BASE) 123 /** Peripheral EDMA_5_TCD base address */ 124 #define IP_EDMA_5_TCD_BASE (0x42E00000u) 125 /** Peripheral EDMA_5_TCD base pointer */ 126 #define IP_EDMA_5_TCD ((EDMA3_TCD_Type *)IP_EDMA_5_TCD_BASE) 127 /** Peripheral CE_EDMA_TCD base address */ 128 #define IP_CE_EDMA_TCD_BASE (0x44E04000u) 129 /** Peripheral CE_EDMA_TCD base pointer */ 130 #define IP_CE_EDMA_TCD ((EDMA3_TCD_Type *)IP_CE_EDMA_TCD_BASE) 131 /** Array initializer of EDMA3_TCD peripheral base addresses */ 132 #define IP_EDMA3_TCD_BASE_ADDRS { IP_EDMA_0_TCD_BASE, IP_EDMA_1_TCD_BASE, IP_EDMA_4_TCD_BASE, IP_EDMA_5_TCD_BASE, IP_CE_EDMA_TCD_BASE } 133 /** Array initializer of EDMA3_TCD peripheral base pointers */ 134 #define IP_EDMA3_TCD_BASE_PTRS { IP_EDMA_0_TCD, IP_EDMA_1_TCD, IP_EDMA_4_TCD, IP_EDMA_5_TCD, IP_CE_EDMA_TCD } 135 136 /* ---------------------------------------------------------------------------- 137 -- EDMA3_TCD Register Masks 138 ---------------------------------------------------------------------------- */ 139 140 /*! 141 * @addtogroup EDMA3_TCD_Register_Masks EDMA3_TCD Register Masks 142 * @{ 143 */ 144 145 /*! @name CH_CSR - Channel Control and Status */ 146 /*! @{ */ 147 148 #define EDMA3_TCD_CH_CSR_ERQ_MASK (0x1U) 149 #define EDMA3_TCD_CH_CSR_ERQ_SHIFT (0U) 150 #define EDMA3_TCD_CH_CSR_ERQ_WIDTH (1U) 151 #define EDMA3_TCD_CH_CSR_ERQ(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_CSR_ERQ_SHIFT)) & EDMA3_TCD_CH_CSR_ERQ_MASK) 152 153 #define EDMA3_TCD_CH_CSR_EARQ_MASK (0x2U) 154 #define EDMA3_TCD_CH_CSR_EARQ_SHIFT (1U) 155 #define EDMA3_TCD_CH_CSR_EARQ_WIDTH (1U) 156 #define EDMA3_TCD_CH_CSR_EARQ(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_CSR_EARQ_SHIFT)) & EDMA3_TCD_CH_CSR_EARQ_MASK) 157 158 #define EDMA3_TCD_CH_CSR_EEI_MASK (0x4U) 159 #define EDMA3_TCD_CH_CSR_EEI_SHIFT (2U) 160 #define EDMA3_TCD_CH_CSR_EEI_WIDTH (1U) 161 #define EDMA3_TCD_CH_CSR_EEI(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_CSR_EEI_SHIFT)) & EDMA3_TCD_CH_CSR_EEI_MASK) 162 163 #define EDMA3_TCD_CH_CSR_EBW_MASK (0x8U) 164 #define EDMA3_TCD_CH_CSR_EBW_SHIFT (3U) 165 #define EDMA3_TCD_CH_CSR_EBW_WIDTH (1U) 166 #define EDMA3_TCD_CH_CSR_EBW(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_CSR_EBW_SHIFT)) & EDMA3_TCD_CH_CSR_EBW_MASK) 167 168 #define EDMA3_TCD_CH_CSR_DONE_MASK (0x40000000U) 169 #define EDMA3_TCD_CH_CSR_DONE_SHIFT (30U) 170 #define EDMA3_TCD_CH_CSR_DONE_WIDTH (1U) 171 #define EDMA3_TCD_CH_CSR_DONE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_CSR_DONE_SHIFT)) & EDMA3_TCD_CH_CSR_DONE_MASK) 172 173 #define EDMA3_TCD_CH_CSR_ACTIVE_MASK (0x80000000U) 174 #define EDMA3_TCD_CH_CSR_ACTIVE_SHIFT (31U) 175 #define EDMA3_TCD_CH_CSR_ACTIVE_WIDTH (1U) 176 #define EDMA3_TCD_CH_CSR_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_CSR_ACTIVE_SHIFT)) & EDMA3_TCD_CH_CSR_ACTIVE_MASK) 177 /*! @} */ 178 179 /*! @name CH_ES - Channel Error Status */ 180 /*! @{ */ 181 182 #define EDMA3_TCD_CH_ES_DBE_MASK (0x1U) 183 #define EDMA3_TCD_CH_ES_DBE_SHIFT (0U) 184 #define EDMA3_TCD_CH_ES_DBE_WIDTH (1U) 185 #define EDMA3_TCD_CH_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_DBE_SHIFT)) & EDMA3_TCD_CH_ES_DBE_MASK) 186 187 #define EDMA3_TCD_CH_ES_SBE_MASK (0x2U) 188 #define EDMA3_TCD_CH_ES_SBE_SHIFT (1U) 189 #define EDMA3_TCD_CH_ES_SBE_WIDTH (1U) 190 #define EDMA3_TCD_CH_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_SBE_SHIFT)) & EDMA3_TCD_CH_ES_SBE_MASK) 191 192 #define EDMA3_TCD_CH_ES_SGE_MASK (0x4U) 193 #define EDMA3_TCD_CH_ES_SGE_SHIFT (2U) 194 #define EDMA3_TCD_CH_ES_SGE_WIDTH (1U) 195 #define EDMA3_TCD_CH_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_SGE_SHIFT)) & EDMA3_TCD_CH_ES_SGE_MASK) 196 197 #define EDMA3_TCD_CH_ES_NCE_MASK (0x8U) 198 #define EDMA3_TCD_CH_ES_NCE_SHIFT (3U) 199 #define EDMA3_TCD_CH_ES_NCE_WIDTH (1U) 200 #define EDMA3_TCD_CH_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_NCE_SHIFT)) & EDMA3_TCD_CH_ES_NCE_MASK) 201 202 #define EDMA3_TCD_CH_ES_DOE_MASK (0x10U) 203 #define EDMA3_TCD_CH_ES_DOE_SHIFT (4U) 204 #define EDMA3_TCD_CH_ES_DOE_WIDTH (1U) 205 #define EDMA3_TCD_CH_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_DOE_SHIFT)) & EDMA3_TCD_CH_ES_DOE_MASK) 206 207 #define EDMA3_TCD_CH_ES_DAE_MASK (0x20U) 208 #define EDMA3_TCD_CH_ES_DAE_SHIFT (5U) 209 #define EDMA3_TCD_CH_ES_DAE_WIDTH (1U) 210 #define EDMA3_TCD_CH_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_DAE_SHIFT)) & EDMA3_TCD_CH_ES_DAE_MASK) 211 212 #define EDMA3_TCD_CH_ES_SOE_MASK (0x40U) 213 #define EDMA3_TCD_CH_ES_SOE_SHIFT (6U) 214 #define EDMA3_TCD_CH_ES_SOE_WIDTH (1U) 215 #define EDMA3_TCD_CH_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_SOE_SHIFT)) & EDMA3_TCD_CH_ES_SOE_MASK) 216 217 #define EDMA3_TCD_CH_ES_SAE_MASK (0x80U) 218 #define EDMA3_TCD_CH_ES_SAE_SHIFT (7U) 219 #define EDMA3_TCD_CH_ES_SAE_WIDTH (1U) 220 #define EDMA3_TCD_CH_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_SAE_SHIFT)) & EDMA3_TCD_CH_ES_SAE_MASK) 221 222 #define EDMA3_TCD_CH_ES_ERR_MASK (0x80000000U) 223 #define EDMA3_TCD_CH_ES_ERR_SHIFT (31U) 224 #define EDMA3_TCD_CH_ES_ERR_WIDTH (1U) 225 #define EDMA3_TCD_CH_ES_ERR(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_ES_ERR_SHIFT)) & EDMA3_TCD_CH_ES_ERR_MASK) 226 /*! @} */ 227 228 /*! @name CH_INT - Channel Interrupt Status */ 229 /*! @{ */ 230 231 #define EDMA3_TCD_CH_INT_INT_MASK (0x1U) 232 #define EDMA3_TCD_CH_INT_INT_SHIFT (0U) 233 #define EDMA3_TCD_CH_INT_INT_WIDTH (1U) 234 #define EDMA3_TCD_CH_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_INT_INT_SHIFT)) & EDMA3_TCD_CH_INT_INT_MASK) 235 /*! @} */ 236 237 /*! @name CH_SBR - Channel System Bus */ 238 /*! @{ */ 239 240 #define EDMA3_TCD_CH_SBR_MID_MASK (0x3FU) 241 #define EDMA3_TCD_CH_SBR_MID_SHIFT (0U) 242 #define EDMA3_TCD_CH_SBR_MID_WIDTH (6U) 243 #define EDMA3_TCD_CH_SBR_MID(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_SBR_MID_SHIFT)) & EDMA3_TCD_CH_SBR_MID_MASK) 244 245 #define EDMA3_TCD_CH_SBR_PAL_MASK (0x8000U) 246 #define EDMA3_TCD_CH_SBR_PAL_SHIFT (15U) 247 #define EDMA3_TCD_CH_SBR_PAL_WIDTH (1U) 248 #define EDMA3_TCD_CH_SBR_PAL(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_SBR_PAL_SHIFT)) & EDMA3_TCD_CH_SBR_PAL_MASK) 249 250 #define EDMA3_TCD_CH_SBR_EMI_MASK (0x10000U) 251 #define EDMA3_TCD_CH_SBR_EMI_SHIFT (16U) 252 #define EDMA3_TCD_CH_SBR_EMI_WIDTH (1U) 253 #define EDMA3_TCD_CH_SBR_EMI(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_SBR_EMI_SHIFT)) & EDMA3_TCD_CH_SBR_EMI_MASK) 254 255 #define EDMA3_TCD_CH_SBR_ATTR_MASK (0x7E0000U) /* Merged from fields with different position or width, of widths (3, 6), largest definition used */ 256 #define EDMA3_TCD_CH_SBR_ATTR_SHIFT (17U) 257 #define EDMA3_TCD_CH_SBR_ATTR_WIDTH (6U) 258 #define EDMA3_TCD_CH_SBR_ATTR(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_SBR_ATTR_SHIFT)) & EDMA3_TCD_CH_SBR_ATTR_MASK) /* Merged from fields with different position or width, of widths (3, 6), largest definition used */ 259 /*! @} */ 260 261 /*! @name CH_PRI - Channel Priority */ 262 /*! @{ */ 263 264 #define EDMA3_TCD_CH_PRI_APL_MASK (0x7U) 265 #define EDMA3_TCD_CH_PRI_APL_SHIFT (0U) 266 #define EDMA3_TCD_CH_PRI_APL_WIDTH (3U) 267 #define EDMA3_TCD_CH_PRI_APL(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_PRI_APL_SHIFT)) & EDMA3_TCD_CH_PRI_APL_MASK) 268 269 #define EDMA3_TCD_CH_PRI_DPA_MASK (0x40000000U) 270 #define EDMA3_TCD_CH_PRI_DPA_SHIFT (30U) 271 #define EDMA3_TCD_CH_PRI_DPA_WIDTH (1U) 272 #define EDMA3_TCD_CH_PRI_DPA(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_PRI_DPA_SHIFT)) & EDMA3_TCD_CH_PRI_DPA_MASK) 273 274 #define EDMA3_TCD_CH_PRI_ECP_MASK (0x80000000U) 275 #define EDMA3_TCD_CH_PRI_ECP_SHIFT (31U) 276 #define EDMA3_TCD_CH_PRI_ECP_WIDTH (1U) 277 #define EDMA3_TCD_CH_PRI_ECP(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_CH_PRI_ECP_SHIFT)) & EDMA3_TCD_CH_PRI_ECP_MASK) 278 /*! @} */ 279 280 /*! @name SADDR - TCD Source Address */ 281 /*! @{ */ 282 283 #define EDMA3_TCD_SADDR_SADDR_MASK (0xFFFFFFFFU) 284 #define EDMA3_TCD_SADDR_SADDR_SHIFT (0U) 285 #define EDMA3_TCD_SADDR_SADDR_WIDTH (32U) 286 #define EDMA3_TCD_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_SADDR_SADDR_SHIFT)) & EDMA3_TCD_SADDR_SADDR_MASK) 287 /*! @} */ 288 289 /*! @name SOFF - TCD Signed Source Address Offset */ 290 /*! @{ */ 291 292 #define EDMA3_TCD_SOFF_SOFF_MASK (0xFFFFU) 293 #define EDMA3_TCD_SOFF_SOFF_SHIFT (0U) 294 #define EDMA3_TCD_SOFF_SOFF_WIDTH (16U) 295 #define EDMA3_TCD_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_SOFF_SOFF_SHIFT)) & EDMA3_TCD_SOFF_SOFF_MASK) 296 /*! @} */ 297 298 /*! @name ATTR - TCD Transfer Attributes */ 299 /*! @{ */ 300 301 #define EDMA3_TCD_ATTR_DSIZE_MASK (0x7U) 302 #define EDMA3_TCD_ATTR_DSIZE_SHIFT (0U) 303 #define EDMA3_TCD_ATTR_DSIZE_WIDTH (3U) 304 #define EDMA3_TCD_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_ATTR_DSIZE_SHIFT)) & EDMA3_TCD_ATTR_DSIZE_MASK) 305 306 #define EDMA3_TCD_ATTR_DMOD_MASK (0xF8U) 307 #define EDMA3_TCD_ATTR_DMOD_SHIFT (3U) 308 #define EDMA3_TCD_ATTR_DMOD_WIDTH (5U) 309 #define EDMA3_TCD_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_ATTR_DMOD_SHIFT)) & EDMA3_TCD_ATTR_DMOD_MASK) 310 311 #define EDMA3_TCD_ATTR_SSIZE_MASK (0x700U) 312 #define EDMA3_TCD_ATTR_SSIZE_SHIFT (8U) 313 #define EDMA3_TCD_ATTR_SSIZE_WIDTH (3U) 314 #define EDMA3_TCD_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_ATTR_SSIZE_SHIFT)) & EDMA3_TCD_ATTR_SSIZE_MASK) 315 316 #define EDMA3_TCD_ATTR_SMOD_MASK (0xF800U) 317 #define EDMA3_TCD_ATTR_SMOD_SHIFT (11U) 318 #define EDMA3_TCD_ATTR_SMOD_WIDTH (5U) 319 #define EDMA3_TCD_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_ATTR_SMOD_SHIFT)) & EDMA3_TCD_ATTR_SMOD_MASK) 320 /*! @} */ 321 322 /*! @name NBYTES_MLOFFNO - TCD Transfer Size Without Minor Loop Offsets */ 323 /*! @{ */ 324 325 #define EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU) 326 #define EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT (0U) 327 #define EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_WIDTH (30U) 328 #define EDMA3_TCD_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFNO_NBYTES_MASK) 329 330 #define EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U) 331 #define EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT (30U) 332 #define EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_WIDTH (1U) 333 #define EDMA3_TCD_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFNO_DMLOE_MASK) 334 335 #define EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U) 336 #define EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT (31U) 337 #define EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_WIDTH (1U) 338 #define EDMA3_TCD_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFNO_SMLOE_MASK) 339 /*! @} */ 340 341 /*! @name NBYTES_MLOFFYES - TCD Transfer Size with Minor Loop Offsets */ 342 /*! @{ */ 343 344 #define EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU) 345 #define EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT (0U) 346 #define EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_WIDTH (10U) 347 #define EDMA3_TCD_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFYES_NBYTES_MASK) 348 349 #define EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U) 350 #define EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT (10U) 351 #define EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_WIDTH (20U) 352 #define EDMA3_TCD_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFYES_MLOFF_MASK) 353 354 #define EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U) 355 #define EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT (30U) 356 #define EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_WIDTH (1U) 357 #define EDMA3_TCD_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFYES_DMLOE_MASK) 358 359 #define EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U) 360 #define EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT (31U) 361 #define EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_WIDTH (1U) 362 #define EDMA3_TCD_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_SHIFT)) & EDMA3_TCD_NBYTES_MLOFFYES_SMLOE_MASK) 363 /*! @} */ 364 365 /*! @name SLAST_SDA - TCD Last Source Address Adjustment / Store DADDR Address */ 366 /*! @{ */ 367 368 #define EDMA3_TCD_SLAST_SDA_SLAST_SDA_MASK (0xFFFFFFFFU) 369 #define EDMA3_TCD_SLAST_SDA_SLAST_SDA_SHIFT (0U) 370 #define EDMA3_TCD_SLAST_SDA_SLAST_SDA_WIDTH (32U) 371 #define EDMA3_TCD_SLAST_SDA_SLAST_SDA(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_SLAST_SDA_SLAST_SDA_SHIFT)) & EDMA3_TCD_SLAST_SDA_SLAST_SDA_MASK) 372 /*! @} */ 373 374 /*! @name DADDR - TCD Destination Address */ 375 /*! @{ */ 376 377 #define EDMA3_TCD_DADDR_DADDR_MASK (0xFFFFFFFFU) 378 #define EDMA3_TCD_DADDR_DADDR_SHIFT (0U) 379 #define EDMA3_TCD_DADDR_DADDR_WIDTH (32U) 380 #define EDMA3_TCD_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_DADDR_DADDR_SHIFT)) & EDMA3_TCD_DADDR_DADDR_MASK) 381 /*! @} */ 382 383 /*! @name DOFF - TCD Signed Destination Address Offset */ 384 /*! @{ */ 385 386 #define EDMA3_TCD_DOFF_DOFF_MASK (0xFFFFU) 387 #define EDMA3_TCD_DOFF_DOFF_SHIFT (0U) 388 #define EDMA3_TCD_DOFF_DOFF_WIDTH (16U) 389 #define EDMA3_TCD_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_DOFF_DOFF_SHIFT)) & EDMA3_TCD_DOFF_DOFF_MASK) 390 /*! @} */ 391 392 /*! @name CITER_ELINKNO - TCD Current Major Loop Count (Minor Loop Channel Linking Disabled) */ 393 /*! @{ */ 394 395 #define EDMA3_TCD_CITER_ELINKNO_CITER_MASK (0x7FFFU) 396 #define EDMA3_TCD_CITER_ELINKNO_CITER_SHIFT (0U) 397 #define EDMA3_TCD_CITER_ELINKNO_CITER_WIDTH (15U) 398 #define EDMA3_TCD_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CITER_ELINKNO_CITER_SHIFT)) & EDMA3_TCD_CITER_ELINKNO_CITER_MASK) 399 400 #define EDMA3_TCD_CITER_ELINKNO_ELINK_MASK (0x8000U) 401 #define EDMA3_TCD_CITER_ELINKNO_ELINK_SHIFT (15U) 402 #define EDMA3_TCD_CITER_ELINKNO_ELINK_WIDTH (1U) 403 #define EDMA3_TCD_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CITER_ELINKNO_ELINK_SHIFT)) & EDMA3_TCD_CITER_ELINKNO_ELINK_MASK) 404 /*! @} */ 405 406 /*! @name CITER_ELINKYES - TCD Current Major Loop Count (Minor Loop Channel Linking Enabled) */ 407 /*! @{ */ 408 409 #define EDMA3_TCD_CITER_ELINKYES_CITER_MASK (0x1FFU) 410 #define EDMA3_TCD_CITER_ELINKYES_CITER_SHIFT (0U) 411 #define EDMA3_TCD_CITER_ELINKYES_CITER_WIDTH (9U) 412 #define EDMA3_TCD_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CITER_ELINKYES_CITER_SHIFT)) & EDMA3_TCD_CITER_ELINKYES_CITER_MASK) 413 414 #define EDMA3_TCD_CITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 415 #define EDMA3_TCD_CITER_ELINKYES_LINKCH_SHIFT (9U) 416 #define EDMA3_TCD_CITER_ELINKYES_LINKCH_WIDTH (5U) 417 #define EDMA3_TCD_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CITER_ELINKYES_LINKCH_SHIFT)) & EDMA3_TCD_CITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 418 419 #define EDMA3_TCD_CITER_ELINKYES_ELINK_MASK (0x8000U) 420 #define EDMA3_TCD_CITER_ELINKYES_ELINK_SHIFT (15U) 421 #define EDMA3_TCD_CITER_ELINKYES_ELINK_WIDTH (1U) 422 #define EDMA3_TCD_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CITER_ELINKYES_ELINK_SHIFT)) & EDMA3_TCD_CITER_ELINKYES_ELINK_MASK) 423 /*! @} */ 424 425 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment / Scatter Gather Address */ 426 /*! @{ */ 427 428 #define EDMA3_TCD_DLAST_SGA_DLAST_SGA_MASK (0xFFFFFFFFU) 429 #define EDMA3_TCD_DLAST_SGA_DLAST_SGA_SHIFT (0U) 430 #define EDMA3_TCD_DLAST_SGA_DLAST_SGA_WIDTH (32U) 431 #define EDMA3_TCD_DLAST_SGA_DLAST_SGA(x) (((uint32_t)(((uint32_t)(x)) << EDMA3_TCD_DLAST_SGA_DLAST_SGA_SHIFT)) & EDMA3_TCD_DLAST_SGA_DLAST_SGA_MASK) 432 /*! @} */ 433 434 /*! @name CSR - TCD Control and Status */ 435 /*! @{ */ 436 437 #define EDMA3_TCD_CSR_START_MASK (0x1U) 438 #define EDMA3_TCD_CSR_START_SHIFT (0U) 439 #define EDMA3_TCD_CSR_START_WIDTH (1U) 440 #define EDMA3_TCD_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_START_SHIFT)) & EDMA3_TCD_CSR_START_MASK) 441 442 #define EDMA3_TCD_CSR_INTMAJOR_MASK (0x2U) 443 #define EDMA3_TCD_CSR_INTMAJOR_SHIFT (1U) 444 #define EDMA3_TCD_CSR_INTMAJOR_WIDTH (1U) 445 #define EDMA3_TCD_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_INTMAJOR_SHIFT)) & EDMA3_TCD_CSR_INTMAJOR_MASK) 446 447 #define EDMA3_TCD_CSR_INTHALF_MASK (0x4U) 448 #define EDMA3_TCD_CSR_INTHALF_SHIFT (2U) 449 #define EDMA3_TCD_CSR_INTHALF_WIDTH (1U) 450 #define EDMA3_TCD_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_INTHALF_SHIFT)) & EDMA3_TCD_CSR_INTHALF_MASK) 451 452 #define EDMA3_TCD_CSR_DREQ_MASK (0x8U) 453 #define EDMA3_TCD_CSR_DREQ_SHIFT (3U) 454 #define EDMA3_TCD_CSR_DREQ_WIDTH (1U) 455 #define EDMA3_TCD_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_DREQ_SHIFT)) & EDMA3_TCD_CSR_DREQ_MASK) 456 457 #define EDMA3_TCD_CSR_ESG_MASK (0x10U) 458 #define EDMA3_TCD_CSR_ESG_SHIFT (4U) 459 #define EDMA3_TCD_CSR_ESG_WIDTH (1U) 460 #define EDMA3_TCD_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_ESG_SHIFT)) & EDMA3_TCD_CSR_ESG_MASK) 461 462 #define EDMA3_TCD_CSR_MAJORELINK_MASK (0x20U) 463 #define EDMA3_TCD_CSR_MAJORELINK_SHIFT (5U) 464 #define EDMA3_TCD_CSR_MAJORELINK_WIDTH (1U) 465 #define EDMA3_TCD_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_MAJORELINK_SHIFT)) & EDMA3_TCD_CSR_MAJORELINK_MASK) 466 467 #define EDMA3_TCD_CSR_ESDA_MASK (0x80U) 468 #define EDMA3_TCD_CSR_ESDA_SHIFT (7U) 469 #define EDMA3_TCD_CSR_ESDA_WIDTH (1U) 470 #define EDMA3_TCD_CSR_ESDA(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_ESDA_SHIFT)) & EDMA3_TCD_CSR_ESDA_MASK) 471 472 #define EDMA3_TCD_CSR_MAJORLINKCH_MASK (0x1F00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 473 #define EDMA3_TCD_CSR_MAJORLINKCH_SHIFT (8U) 474 #define EDMA3_TCD_CSR_MAJORLINKCH_WIDTH (5U) 475 #define EDMA3_TCD_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_MAJORLINKCH_SHIFT)) & EDMA3_TCD_CSR_MAJORLINKCH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 476 477 #define EDMA3_TCD_CSR_BWC_MASK (0xC000U) 478 #define EDMA3_TCD_CSR_BWC_SHIFT (14U) 479 #define EDMA3_TCD_CSR_BWC_WIDTH (2U) 480 #define EDMA3_TCD_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_CSR_BWC_SHIFT)) & EDMA3_TCD_CSR_BWC_MASK) 481 /*! @} */ 482 483 /*! @name BITER_ELINKNO - TCD Beginning Major Loop Count (Minor Loop Channel Linking Disabled) */ 484 /*! @{ */ 485 486 #define EDMA3_TCD_BITER_ELINKNO_BITER_MASK (0x7FFFU) 487 #define EDMA3_TCD_BITER_ELINKNO_BITER_SHIFT (0U) 488 #define EDMA3_TCD_BITER_ELINKNO_BITER_WIDTH (15U) 489 #define EDMA3_TCD_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_BITER_ELINKNO_BITER_SHIFT)) & EDMA3_TCD_BITER_ELINKNO_BITER_MASK) 490 491 #define EDMA3_TCD_BITER_ELINKNO_ELINK_MASK (0x8000U) 492 #define EDMA3_TCD_BITER_ELINKNO_ELINK_SHIFT (15U) 493 #define EDMA3_TCD_BITER_ELINKNO_ELINK_WIDTH (1U) 494 #define EDMA3_TCD_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_BITER_ELINKNO_ELINK_SHIFT)) & EDMA3_TCD_BITER_ELINKNO_ELINK_MASK) 495 /*! @} */ 496 497 /*! @name BITER_ELINKYES - TCD Beginning Major Loop Count (Minor Loop Channel Linking Enabled) */ 498 /*! @{ */ 499 500 #define EDMA3_TCD_BITER_ELINKYES_BITER_MASK (0x1FFU) 501 #define EDMA3_TCD_BITER_ELINKYES_BITER_SHIFT (0U) 502 #define EDMA3_TCD_BITER_ELINKYES_BITER_WIDTH (9U) 503 #define EDMA3_TCD_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_BITER_ELINKYES_BITER_SHIFT)) & EDMA3_TCD_BITER_ELINKYES_BITER_MASK) 504 505 #define EDMA3_TCD_BITER_ELINKYES_LINKCH_MASK (0x3E00U) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 506 #define EDMA3_TCD_BITER_ELINKYES_LINKCH_SHIFT (9U) 507 #define EDMA3_TCD_BITER_ELINKYES_LINKCH_WIDTH (5U) 508 #define EDMA3_TCD_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_BITER_ELINKYES_LINKCH_SHIFT)) & EDMA3_TCD_BITER_ELINKYES_LINKCH_MASK) /* Merged from fields with different position or width, of widths (4, 5), largest definition used */ 509 510 #define EDMA3_TCD_BITER_ELINKYES_ELINK_MASK (0x8000U) 511 #define EDMA3_TCD_BITER_ELINKYES_ELINK_SHIFT (15U) 512 #define EDMA3_TCD_BITER_ELINKYES_ELINK_WIDTH (1U) 513 #define EDMA3_TCD_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << EDMA3_TCD_BITER_ELINKYES_ELINK_SHIFT)) & EDMA3_TCD_BITER_ELINKYES_ELINK_MASK) 514 /*! @} */ 515 516 /*! 517 * @} 518 */ /* end of group EDMA3_TCD_Register_Masks */ 519 520 /*! 521 * @} 522 */ /* end of group EDMA3_TCD_Peripheral_Access_Layer */ 523 524 #endif /* #if !defined(S32Z2_EDMA3_TCD_H_) */ 525
