1 /* 2 * Copyright 1997-2016 Freescale Semiconductor, Inc. 3 * Copyright 2016-2022 NXP 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 /*! 9 * @file S32Z2_AXBS.h 10 * @version 1.8 11 * @date 2022-07-13 12 * @brief Peripheral Access Layer for S32Z2_AXBS 13 * 14 * This file contains register definitions and macros for easy access to their 15 * bit fields. 16 * 17 * This file assumes LITTLE endian system. 18 */ 19 20 /** 21 * @page misra_violations MISRA-C:2012 violations 22 * 23 * @section [global] 24 * Violates MISRA 2012 Advisory Rule 2.3, local typedef not referenced 25 * The SoC header defines typedef for all modules. 26 * 27 * @section [global] 28 * Violates MISRA 2012 Advisory Rule 2.5, local macro not referenced 29 * The SoC header defines macros for all modules and registers. 30 * 31 * @section [global] 32 * Violates MISRA 2012 Advisory Directive 4.9, Function-like macro 33 * These are generated macros used for accessing the bit-fields from registers. 34 * 35 * @section [global] 36 * Violates MISRA 2012 Required Rule 5.1, identifier clash 37 * The supported compilers use more than 31 significant characters for identifiers. 38 * 39 * @section [global] 40 * Violates MISRA 2012 Required Rule 5.2, identifier clash 41 * The supported compilers use more than 31 significant characters for identifiers. 42 * 43 * @section [global] 44 * Violates MISRA 2012 Required Rule 5.4, identifier clash 45 * The supported compilers use more than 31 significant characters for identifiers. 46 * 47 * @section [global] 48 * Violates MISRA 2012 Required Rule 5.5, identifier clash 49 * The supported compilers use more than 31 significant characters for identifiers. 50 * 51 * @section [global] 52 * Violates MISRA 2012 Required Rule 21.1, defined macro '__I' is reserved to the compiler 53 * This type qualifier is needed to ensure correct I/O access and addressing. 54 */ 55 56 /* Prevention from multiple including the same memory map */ 57 #if !defined(S32Z2_AXBS_H_) /* Check if memory map has not been already included */ 58 #define S32Z2_AXBS_H_ 59 60 #include "S32Z2_COMMON.h" 61 62 /* ---------------------------------------------------------------------------- 63 -- AXBS Peripheral Access Layer 64 ---------------------------------------------------------------------------- */ 65 66 /*! 67 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer 68 * @{ 69 */ 70 71 /** AXBS - Size of Registers Arrays */ 72 #define AXBS_PORT_COUNT 8u 73 74 /** AXBS - Register Layout Typedef */ 75 typedef struct { 76 struct { /* offset: 0x0, array step: 0x100 */ 77 __IO uint32_t PRS; /**< Priority Slave Registers, array offset: 0x0, array step: 0x100 */ 78 uint8_t RESERVED_0[12]; 79 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */ 80 uint8_t RESERVED_1[236]; 81 } PORT[AXBS_PORT_COUNT]; 82 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */ 83 uint8_t RESERVED_0[252]; 84 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */ 85 uint8_t RESERVED_1[252]; 86 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */ 87 uint8_t RESERVED_2[252]; 88 __IO uint32_t MGPCR3; /**< Master General Purpose Control Register, offset: 0xB00 */ 89 uint8_t RESERVED_3[252]; 90 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */ 91 uint8_t RESERVED_4[252]; 92 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */ 93 } AXBS_Type, *AXBS_MemMapPtr; 94 95 /** Number of instances of the AXBS module. */ 96 #define AXBS_INSTANCE_COUNT (2u) 97 98 /* AXBS - Peripheral instance base addresses */ 99 /** Peripheral CE_AXBS base address */ 100 #define IP_CE_AXBS_BASE (0x44860000u) 101 /** Peripheral CE_AXBS base pointer */ 102 #define IP_CE_AXBS ((AXBS_Type *)IP_CE_AXBS_BASE) 103 /** Peripheral SMU__AXBS base address */ 104 #define IP_SMU__AXBS_BASE (0x45060000u) 105 /** Peripheral SMU__AXBS base pointer */ 106 #define IP_SMU__AXBS ((AXBS_Type *)IP_SMU__AXBS_BASE) 107 /** Array initializer of AXBS peripheral base addresses */ 108 #define IP_AXBS_BASE_ADDRS { IP_CE_AXBS_BASE, IP_SMU__AXBS_BASE } 109 /** Array initializer of AXBS peripheral base pointers */ 110 #define IP_AXBS_BASE_PTRS { IP_CE_AXBS, IP_SMU__AXBS } 111 112 /* ---------------------------------------------------------------------------- 113 -- AXBS Register Masks 114 ---------------------------------------------------------------------------- */ 115 116 /*! 117 * @addtogroup AXBS_Register_Masks AXBS Register Masks 118 * @{ 119 */ 120 121 /*! @name PRS - Priority Slave Registers */ 122 /*! @{ */ 123 124 #define AXBS_PRS_M0_MASK (0x7U) 125 #define AXBS_PRS_M0_SHIFT (0U) 126 #define AXBS_PRS_M0_WIDTH (3U) 127 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK) 128 129 #define AXBS_PRS_M1_MASK (0x70U) 130 #define AXBS_PRS_M1_SHIFT (4U) 131 #define AXBS_PRS_M1_WIDTH (3U) 132 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK) 133 134 #define AXBS_PRS_M2_MASK (0x700U) 135 #define AXBS_PRS_M2_SHIFT (8U) 136 #define AXBS_PRS_M2_WIDTH (3U) 137 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK) 138 139 #define AXBS_PRS_M3_MASK (0x7000U) 140 #define AXBS_PRS_M3_SHIFT (12U) 141 #define AXBS_PRS_M3_WIDTH (3U) 142 #define AXBS_PRS_M3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M3_SHIFT)) & AXBS_PRS_M3_MASK) 143 144 #define AXBS_PRS_M4_MASK (0x70000U) 145 #define AXBS_PRS_M4_SHIFT (16U) 146 #define AXBS_PRS_M4_WIDTH (3U) 147 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK) 148 149 #define AXBS_PRS_M5_MASK (0x700000U) 150 #define AXBS_PRS_M5_SHIFT (20U) 151 #define AXBS_PRS_M5_WIDTH (3U) 152 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK) 153 /*! @} */ 154 155 /*! @name CRS - Control Register */ 156 /*! @{ */ 157 158 #define AXBS_CRS_PARK_MASK (0x7U) 159 #define AXBS_CRS_PARK_SHIFT (0U) 160 #define AXBS_CRS_PARK_WIDTH (3U) 161 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK) 162 163 #define AXBS_CRS_PCTL_MASK (0x30U) 164 #define AXBS_CRS_PCTL_SHIFT (4U) 165 #define AXBS_CRS_PCTL_WIDTH (2U) 166 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK) 167 168 #define AXBS_CRS_ARB_MASK (0x300U) 169 #define AXBS_CRS_ARB_SHIFT (8U) 170 #define AXBS_CRS_ARB_WIDTH (2U) 171 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK) 172 173 #define AXBS_CRS_HPE0_MASK (0x10000U) 174 #define AXBS_CRS_HPE0_SHIFT (16U) 175 #define AXBS_CRS_HPE0_WIDTH (1U) 176 #define AXBS_CRS_HPE0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE0_SHIFT)) & AXBS_CRS_HPE0_MASK) 177 178 #define AXBS_CRS_HPE1_MASK (0x20000U) 179 #define AXBS_CRS_HPE1_SHIFT (17U) 180 #define AXBS_CRS_HPE1_WIDTH (1U) 181 #define AXBS_CRS_HPE1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE1_SHIFT)) & AXBS_CRS_HPE1_MASK) 182 183 #define AXBS_CRS_HPE2_MASK (0x40000U) 184 #define AXBS_CRS_HPE2_SHIFT (18U) 185 #define AXBS_CRS_HPE2_WIDTH (1U) 186 #define AXBS_CRS_HPE2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE2_SHIFT)) & AXBS_CRS_HPE2_MASK) 187 188 #define AXBS_CRS_HPE3_MASK (0x80000U) 189 #define AXBS_CRS_HPE3_SHIFT (19U) 190 #define AXBS_CRS_HPE3_WIDTH (1U) 191 #define AXBS_CRS_HPE3(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE3_SHIFT)) & AXBS_CRS_HPE3_MASK) 192 193 #define AXBS_CRS_HPE4_MASK (0x100000U) 194 #define AXBS_CRS_HPE4_SHIFT (20U) 195 #define AXBS_CRS_HPE4_WIDTH (1U) 196 #define AXBS_CRS_HPE4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE4_SHIFT)) & AXBS_CRS_HPE4_MASK) 197 198 #define AXBS_CRS_HPE5_MASK (0x200000U) 199 #define AXBS_CRS_HPE5_SHIFT (21U) 200 #define AXBS_CRS_HPE5_WIDTH (1U) 201 #define AXBS_CRS_HPE5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE5_SHIFT)) & AXBS_CRS_HPE5_MASK) 202 203 #define AXBS_CRS_HPE6_MASK (0x400000U) 204 #define AXBS_CRS_HPE6_SHIFT (22U) 205 #define AXBS_CRS_HPE6_WIDTH (1U) 206 #define AXBS_CRS_HPE6(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE6_SHIFT)) & AXBS_CRS_HPE6_MASK) 207 208 #define AXBS_CRS_HPE7_MASK (0x800000U) 209 #define AXBS_CRS_HPE7_SHIFT (23U) 210 #define AXBS_CRS_HPE7_WIDTH (1U) 211 #define AXBS_CRS_HPE7(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HPE7_SHIFT)) & AXBS_CRS_HPE7_MASK) 212 213 #define AXBS_CRS_HLP_MASK (0x40000000U) 214 #define AXBS_CRS_HLP_SHIFT (30U) 215 #define AXBS_CRS_HLP_WIDTH (1U) 216 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK) 217 218 #define AXBS_CRS_RO_MASK (0x80000000U) 219 #define AXBS_CRS_RO_SHIFT (31U) 220 #define AXBS_CRS_RO_WIDTH (1U) 221 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK) 222 /*! @} */ 223 224 /*! @name MGPCR0 - Master General Purpose Control Register */ 225 /*! @{ */ 226 227 #define AXBS_MGPCR0_AULB_MASK (0x7U) 228 #define AXBS_MGPCR0_AULB_SHIFT (0U) 229 #define AXBS_MGPCR0_AULB_WIDTH (3U) 230 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK) 231 /*! @} */ 232 233 /*! @name MGPCR1 - Master General Purpose Control Register */ 234 /*! @{ */ 235 236 #define AXBS_MGPCR1_AULB_MASK (0x7U) 237 #define AXBS_MGPCR1_AULB_SHIFT (0U) 238 #define AXBS_MGPCR1_AULB_WIDTH (3U) 239 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK) 240 /*! @} */ 241 242 /*! @name MGPCR2 - Master General Purpose Control Register */ 243 /*! @{ */ 244 245 #define AXBS_MGPCR2_AULB_MASK (0x7U) 246 #define AXBS_MGPCR2_AULB_SHIFT (0U) 247 #define AXBS_MGPCR2_AULB_WIDTH (3U) 248 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK) 249 /*! @} */ 250 251 /*! @name MGPCR3 - Master General Purpose Control Register */ 252 /*! @{ */ 253 254 #define AXBS_MGPCR3_AULB_MASK (0x7U) 255 #define AXBS_MGPCR3_AULB_SHIFT (0U) 256 #define AXBS_MGPCR3_AULB_WIDTH (3U) 257 #define AXBS_MGPCR3_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR3_AULB_SHIFT)) & AXBS_MGPCR3_AULB_MASK) 258 /*! @} */ 259 260 /*! @name MGPCR4 - Master General Purpose Control Register */ 261 /*! @{ */ 262 263 #define AXBS_MGPCR4_AULB_MASK (0x7U) 264 #define AXBS_MGPCR4_AULB_SHIFT (0U) 265 #define AXBS_MGPCR4_AULB_WIDTH (3U) 266 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK) 267 /*! @} */ 268 269 /*! @name MGPCR5 - Master General Purpose Control Register */ 270 /*! @{ */ 271 272 #define AXBS_MGPCR5_AULB_MASK (0x7U) 273 #define AXBS_MGPCR5_AULB_SHIFT (0U) 274 #define AXBS_MGPCR5_AULB_WIDTH (3U) 275 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK) 276 /*! @} */ 277 278 /*! 279 * @} 280 */ /* end of group AXBS_Register_Masks */ 281 282 /*! 283 * @} 284 */ /* end of group AXBS_Peripheral_Access_Layer */ 285 286 #endif /* #if !defined(S32Z2_AXBS_H_) */ 287
