1 /*
2 * Copyright 2017-2018 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 /***********************************************************************************************************************
9 * This file was generated by the MCUXpresso Config Tools. Any manual edits made to this file
10 * will be overwritten if the respective MCUXpresso Config Tools is used to update this file.
11 **********************************************************************************************************************/
12 /*
13 * How to set up clock using clock driver functions:
14 *
15 * 1. Setup clock sources.
16 *
17 * 2. Set up wait states of the flash.
18 *
19 * 3. Set up all dividers.
20 *
21 * 4. Set up all selectors to provide selected clocks.
22 */
23
24 /* clang-format off */
25 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
26 !!GlobalInfo
27 product: Clocks v4.1
28 processor: LPC55S69
29 package_id: LPC55S69JBD100
30 mcu_data: ksdk2_0
31 processor_version: 0.0.0
32 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
33 /* clang-format on */
34
35 #include "fsl_power.h"
36 #include "fsl_clock.h"
37 #include "clock_config.h"
38
39 /*******************************************************************************
40 * Definitions
41 ******************************************************************************/
42
43 /*******************************************************************************
44 * Variables
45 ******************************************************************************/
46 /* System clock frequency. */
47 extern uint32_t SystemCoreClock;
48
49 /*******************************************************************************
50 ************************ BOARD_InitBootClocks function ************************
51 ******************************************************************************/
BOARD_InitBootClocks(void)52 void BOARD_InitBootClocks(void)
53 {
54 BOARD_BootClockFROHF96M();
55 }
56
57 /*******************************************************************************
58 ******************** Configuration BOARD_BootClockFRO12M **********************
59 ******************************************************************************/
60 /* clang-format off */
61 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
62 !!Configuration
63 name: BOARD_BootClockFRO12M
64 outputs:
65 - {id: System_clock.outFreq, value: 12 MHz}
66 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
67 /* clang-format on */
68
69 /*******************************************************************************
70 * Variables for BOARD_BootClockFRO12M configuration
71 ******************************************************************************/
72 /*******************************************************************************
73 * Code for BOARD_BootClockFRO12M configuration
74 ******************************************************************************/
BOARD_BootClockFRO12M(void)75 void BOARD_BootClockFRO12M(void)
76 {
77 #ifndef SDK_SECONDARY_CORE
78 /*!< Set up the clock sources */
79 /*!< Configure FRO192M */
80 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
81 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
82 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
83
84 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
85
86 CLOCK_SetFLASHAccessCyclesForFreq(12000000U); /*!< Set FLASH wait states for core */
87
88 /*!< Set up dividers */
89 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
90
91 /*!< Set up clock selectors - Attach clocks to the peripheries */
92 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO12M */
93
94 /*< Set SystemCoreClock variable. */
95 SystemCoreClock = BOARD_BOOTCLOCKFRO12M_CORE_CLOCK;
96 #endif
97 }
98
99 /*******************************************************************************
100 ******************* Configuration BOARD_BootClockFROHF96M *********************
101 ******************************************************************************/
102 /* clang-format off */
103 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
104 !!Configuration
105 name: BOARD_BootClockFROHF96M
106 called_from_default_init: true
107 outputs:
108 - {id: System_clock.outFreq, value: 96 MHz}
109 settings:
110 - {id: SYSCON.MAINCLKSELA.sel, value: ANACTRL.fro_hf_clk}
111 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
112 /* clang-format on */
113
114 /*******************************************************************************
115 * Variables for BOARD_BootClockFROHF96M configuration
116 ******************************************************************************/
117 /*******************************************************************************
118 * Code for BOARD_BootClockFROHF96M configuration
119 ******************************************************************************/
BOARD_BootClockFROHF96M(void)120 void BOARD_BootClockFROHF96M(void)
121 {
122 #ifndef SDK_SECONDARY_CORE
123 /*!< Set up the clock sources */
124 /*!< Configure FRO192M */
125 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
126 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
127 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
128
129 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
130
131 CLOCK_SetFLASHAccessCyclesForFreq(96000000U); /*!< Set FLASH wait states for core */
132
133 /*!< Set up dividers */
134 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
135
136 /*!< Set up clock selectors - Attach clocks to the peripheries */
137 CLOCK_AttachClk(kFRO_HF_to_MAIN_CLK); /*!< Switch MAIN_CLK to FRO_HF */
138
139 /*< Set SystemCoreClock variable. */
140 SystemCoreClock = BOARD_BOOTCLOCKFROHF96M_CORE_CLOCK;
141 #endif
142 }
143
144 /*******************************************************************************
145 ******************** Configuration BOARD_BootClockPLL100M *********************
146 ******************************************************************************/
147 /* clang-format off */
148 /* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
149 !!Configuration
150 name: BOARD_BootClockPLL100M
151 outputs:
152 - {id: System_clock.outFreq, value: 100 MHz}
153 settings:
154 - {id: PLL0_Mode, value: Normal}
155 - {id: ENABLE_CLKIN_ENA, value: Enabled}
156 - {id: ENABLE_SYSTEM_CLK_OUT, value: Enabled}
157 - {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL0_BYPASS}
158 - {id: SYSCON.PLL0CLKSEL.sel, value: SYSCON.CLK_IN_EN}
159 - {id: SYSCON.PLL0M_MULT.scale, value: '100', locked: true}
160 - {id: SYSCON.PLL0N_DIV.scale, value: '4', locked: true}
161 - {id: SYSCON.PLL0_PDEC.scale, value: '4', locked: true}
162 - {id: 'SYSCON::PLL0SSCG0[MD_LBS].bitField', value: BitFieldValue}
163 sources:
164 - {id: SYSCON.XTAL32M.outFreq, value: 16 MHz, enabled: true}
165 * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
166 /* clang-format on */
167
168 /*******************************************************************************
169 * Variables for BOARD_BootClockPLL100M configuration
170 ******************************************************************************/
171 /*******************************************************************************
172 * Code for BOARD_BootClockPLL100M configuration
173 ******************************************************************************/
BOARD_BootClockPLL100M(void)174 void BOARD_BootClockPLL100M(void)
175 {
176 #ifndef SDK_SECONDARY_CORE
177 /*!< Set up the clock sources */
178 /*!< Configure FRO192M */
179 POWER_DisablePD(kPDRUNCFG_PD_FRO192M); /*!< Ensure FRO is on */
180 CLOCK_SetupFROClocking(12000000U); /*!< Set up FRO to the 12 MHz, just for sure */
181 CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change the clock setting */
182
183 CLOCK_SetupFROClocking(96000000U); /* Enable FRO HF(96MHz) output */
184
185 POWER_DisablePD(kPDRUNCFG_PD_XTAL32M); /* Ensure XTAL32M is powered */
186 POWER_DisablePD(kPDRUNCFG_PD_LDOXO32M); /* Ensure XTAL32M is powered */
187 CLOCK_SetupExtClocking(16000000U); /* Enable clk_in clock */
188 SYSCON->CLOCK_CTRL |= SYSCON_CLOCK_CTRL_CLKIN_ENA_MASK; /* Enable clk_in from XTAL32M clock */
189 ANACTRL->XO32M_CTRL |= ANACTRL_XO32M_CTRL_ENABLE_SYSTEM_CLK_OUT_MASK; /* Enable clk_in to system */
190
191 CLOCK_SetFLASHAccessCyclesForFreq(100000000U); /*!< Set FLASH wait states for core */
192
193 /*!< Set up PLL */
194 CLOCK_AttachClk(kEXT_CLK_to_PLL0); /*!< Switch PLL0CLKSEL to EXT_CLK */
195 POWER_DisablePD(kPDRUNCFG_PD_PLL0); /* Ensure PLL is on */
196 POWER_DisablePD(kPDRUNCFG_PD_PLL0_SSCG);
197 const pll_setup_t pll0Setup = {
198 .pllctrl = SYSCON_PLL0CTRL_CLKEN_MASK | SYSCON_PLL0CTRL_SELI(54U) | SYSCON_PLL0CTRL_SELP(26U),
199 .pllndec = SYSCON_PLL0NDEC_NDIV(4U),
200 .pllpdec = SYSCON_PLL0PDEC_PDIV(2U),
201 .pllsscg = {0x0U,(SYSCON_PLL0SSCG1_MDIV_EXT(100U) | SYSCON_PLL0SSCG1_SEL_EXT_MASK)},
202 .pllRate = 100000000U,
203 .flags = PLL_SETUPFLAG_WAITLOCK
204 };
205 CLOCK_SetPLL0Freq(&pll0Setup); /*!< Configure PLL0 to the desired values */
206
207 /*!< Set up dividers */
208 CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Set AHBCLKDIV divider to value 1 */
209
210 /*!< Set up clock selectors - Attach clocks to the peripheries */
211 CLOCK_AttachClk(kPLL0_to_MAIN_CLK); /*!< Switch MAIN_CLK to PLL0 */
212
213 /*< Set SystemCoreClock variable. */
214 SystemCoreClock = BOARD_BOOTCLOCKPLL100M_CORE_CLOCK;
215 #endif
216 }
217
218
