1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2017 NXP 4 * All rights reserved. 5 * 6 * SPDX-License-Identifier: BSD-3-Clause 7 */ 8 #ifndef __RTE_DEVICE_H 9 #define __RTE_DEVICE_H 10 11 /*Driver name mapping*/ 12 #define RTE_I2C0 1 13 #define RTE_I2C0_DMA_EN 0 14 #define RTE_I2C1 1 15 #define RTE_I2C1_DMA_EN 0 16 17 #define RTE_SPI0 1 18 #define RTE_SPI0_DMA_EN 0 19 #define RTE_SPI1 0 20 #define RTE_SPI1_DMA_EN 0 21 22 #define RTE_USART0 1 23 #define RTE_USART0_DMA_EN 0 24 #define RTE_USART1 0 25 #define RTE_USART1_DMA_EN 0 26 27 /* UART configuration. */ 28 #define USART_RX_BUFFER_LEN 64 29 #define USART0_RX_BUFFER_ENABLE 1 30 31 #define RTE_USART0_DMA_TX_CH 0 32 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPSCI0Tx 33 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 34 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 35 #define RTE_USART0_DMA_RX_CH 1 36 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPSCI0Rx 37 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 38 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 39 40 #define RTE_USART1_DMA_TX_CH 0 41 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 42 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 43 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 44 #define RTE_USART1_DMA_RX_CH 1 45 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 46 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 47 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 48 49 #define RTE_USART2_DMA_TX_CH 0 50 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 51 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 52 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 53 #define RTE_USART2_DMA_RX_CH 1 54 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 55 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 56 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 57 58 /* SPI configuration. */ 59 #define RTE_SPI0_DMA_TX_CH 0 60 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 61 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 62 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 63 #define RTE_SPI0_DMA_RX_CH 1 64 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 65 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 66 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 67 68 #define RTE_SPI1_DMA_TX_CH 2 69 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx 70 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 71 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 72 #define RTE_SPI1_DMA_RX_CH 3 73 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx 74 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 75 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 76 77 /*I2C configuration*/ 78 #define RTE_I2C0_Master_DMA_BASE DMA0 79 #define RTE_I2C0_Master_DMA_CH 0 80 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 81 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 82 83 #define RTE_I2C1_Master_DMA_BASE DMA0 84 #define RTE_I2C1_Master_DMA_CH 1 85 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 86 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 87 88 #endif /* __RTE_DEVICE_H */ 89
