1 /*
2 * Copyright 2017 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #include "fsl_common.h"
9 #include "clock_config.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14 /* ARM PLL configuration for RUN mode */
15 const clock_arm_pll_config_t armPllConfig = {
16 .loopDivider = 100U};
17
18 /* SYS PLL configuration for RUN mode */
19 const clock_sys_pll_config_t sysPllConfig = {
20 .loopDivider = 1U};
21
22 /* USB1 PLL configuration for RUN mode */
23 const clock_usb_pll_config_t usb1PllConfig = {
24 .loopDivider = 0U};
25
26 /*******************************************************************************
27 * Variables
28 ******************************************************************************/
29 /* System clock frequency. */
30 extern uint32_t SystemCoreClock;
31
32 /*******************************************************************************
33 * Code
34 ******************************************************************************/
BOARD_BootClockGate(void)35 static void BOARD_BootClockGate(void)
36 {
37 /* Disable all unused peripheral clock */
38 CCM->CCGR0 = 0x00C0000FU;
39 CCM->CCGR1 = 0x30000000U;
40 CCM->CCGR2 = 0xFF3F003FU;
41 CCM->CCGR3 = 0xF0000330U;
42 CCM->CCGR4 = 0x0000FF3CU;
43 CCM->CCGR5 = 0xF003330FU;
44 CCM->CCGR6 = 0x00FC0F00U;
45 }
46
BOARD_BootClockRUN(void)47 void BOARD_BootClockRUN(void)
48 {
49 /* Boot ROM did initialize the XTAL, here we only sets external XTAL OSC freq */
50 CLOCK_SetXtalFreq(24000000U);
51 CLOCK_SetRtcXtalFreq(32768U);
52
53 CLOCK_SetMux(kCLOCK_PeriphClk2Mux, 0x1); /* Set PERIPH_CLK2 MUX to OSC */
54 CLOCK_SetMux(kCLOCK_PeriphMux, 0x1); /* Set PERIPH_CLK MUX to PERIPH_CLK2 */
55
56 /* Setting the VDD_SOC to 1.5V. It is necessary to config AHB to 600Mhz */
57 DCDC->REG3 = (DCDC->REG3 & (~DCDC_REG3_TRG_MASK)) | DCDC_REG3_TRG(0x12);
58
59 CLOCK_InitArmPll(&armPllConfig); /* Configure ARM PLL to 1200M */
60 #ifndef SKIP_SYSCLK_INIT
61 CLOCK_InitSysPll(&sysPllConfig); /* Configure SYS PLL to 528M */
62 #endif
63 #ifndef SKIP_USB_PLL_INIT
64 CLOCK_InitUsb1Pll(&usb1PllConfig); /* Configure USB1 PLL to 480M */
65 #endif
66 CLOCK_SetDiv(kCLOCK_ArmDiv, 0x1); /* Set ARM PODF to 0, divide by 2 */
67 CLOCK_SetDiv(kCLOCK_AhbDiv, 0x0); /* Set AHB PODF to 0, divide by 1 */
68 CLOCK_SetDiv(kCLOCK_IpgDiv, 0x3); /* Set IPG PODF to 3, divede by 4 */
69
70 CLOCK_SetMux(kCLOCK_PrePeriphMux, 0x3); /* Set PRE_PERIPH_CLK to PLL1, 1200M */
71 CLOCK_SetMux(kCLOCK_PeriphMux, 0x0); /* Set PERIPH_CLK MUX to PRE_PERIPH_CLK */
72
73 /* Disable unused clock */
74 BOARD_BootClockGate();
75
76 /* Power down all unused PLL */
77 CLOCK_DeinitAudioPll();
78 CLOCK_DeinitVideoPll();
79 CLOCK_DeinitEnetPll();
80 CLOCK_DeinitUsb2Pll();
81
82 /* Configure UART divider to default */
83 CLOCK_SetMux(kCLOCK_UartMux, 0); /* Set UART source to PLL3 80M */
84 CLOCK_SetDiv(kCLOCK_UartDiv, 0); /* Set UART divider to 1 */
85
86 /* Update core clock */
87 SystemCoreClockUpdate();
88 }
89
