1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019 NXP
4 * All rights reserved.
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_rit.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.rit"
14 #endif
15
16 /*******************************************************************************
17 * Prototypes
18 ******************************************************************************/
19 /*!
20 * @brief Gets the instance from the base address to be used to gate or ungate the module clock
21 *
22 * @param base RIT peripheral base address
23 *
24 * @return The RIT instance
25 */
26 static uint32_t RIT_GetInstance(RIT_Type *base);
27
28 /*******************************************************************************
29 * Variables
30 ******************************************************************************/
31 /*! @brief Pointers to RIT bases for each instance. */
32 static RIT_Type *const s_ritBases[] = RIT_BASE_PTRS;
33
34 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
35 /*! @brief Pointers to PIT clocks for each instance. */
36 static const clock_ip_name_t s_ritClocks[] = RIT_CLOCKS;
37 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
38
39 #if !(defined(FSL_FEATURE_RIT_HAS_NO_RESET) && FSL_FEATURE_RIT_HAS_NO_RESET)
40 /*! @brief Pointers to RIT resets for each instance. */
41 static const reset_ip_name_t s_ritResets[] = RIT_RSTS;
42 #endif
43
44 /*******************************************************************************
45 * Code
46 ******************************************************************************/
RIT_GetInstance(RIT_Type * base)47 static uint32_t RIT_GetInstance(RIT_Type *base)
48 {
49 uint32_t instance;
50
51 /* Find the instance index from base address mappings. */
52 for (instance = 0; instance < ARRAY_SIZE(s_ritBases); instance++)
53 {
54 if (s_ritBases[instance] == base)
55 {
56 break;
57 }
58 }
59
60 assert(instance < ARRAY_SIZE(s_ritBases));
61
62 return instance;
63 }
64
65 /*!
66 * brief Fills in the RIT configuration structure with the default settings.
67 *
68 * The default values are as follows.
69 * code
70 * config->enableRunInDebug = false;
71 * endcode
72 * param config Pointer to the onfiguration structure.
73 */
RIT_GetDefaultConfig(rit_config_t * config)74 void RIT_GetDefaultConfig(rit_config_t *config)
75 {
76 assert(NULL != config);
77
78 /* Initializes the configure structure to zero. */
79 (void)memset(config, 0, sizeof(*config));
80
81 /* Timer operation are no effect in Debug mode */
82 config->enableRunInDebug = false;
83 }
84
85 /*!
86 * brief Ungates the RIT clock, enables the RIT module, and configures the peripheral for basic operations.
87 *
88 * note This API should be called at the beginning of the application using the RIT driver.
89 *
90 * param base RIT peripheral base address
91 * param config Pointer to the user's RIT config structure
92 */
RIT_Init(RIT_Type * base,const rit_config_t * config)93 void RIT_Init(RIT_Type *base, const rit_config_t *config)
94 {
95 assert(NULL != config);
96
97 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
98 /* Ungate the RIT clock*/
99 CLOCK_EnableClock(s_ritClocks[RIT_GetInstance(base)]);
100 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
101
102 #if !(defined(FSL_FEATURE_RIT_HAS_NO_RESET) && FSL_FEATURE_RIT_HAS_NO_RESET)
103 /* Reset the RIT module */
104 RESET_PeripheralReset(s_ritResets[RIT_GetInstance(base)]);
105 #endif
106
107 /* Enable RIT timers */
108 base->CTRL |= RIT_CTRL_RITEN_MASK;
109
110 /* Config timer operation is no effect in debug mode */
111 if (!config->enableRunInDebug)
112 {
113 base->CTRL &= ~RIT_CTRL_RITENBR_MASK;
114 }
115 else
116 {
117 base->CTRL |= RIT_CTRL_RITENBR_MASK;
118 }
119 }
120
121 /*!
122 * brief Gates the RIT clock and disables the RIT module.
123 *
124 * param base RIT peripheral base address
125 */
RIT_Deinit(RIT_Type * base)126 void RIT_Deinit(RIT_Type *base)
127 {
128 /* Disable RIT timers */
129 base->CTRL &= ~RIT_CTRL_RITEN_MASK;
130 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
131 /* Gate the RIT clock*/
132 CLOCK_DisableClock(s_ritClocks[RIT_GetInstance(base)]);
133 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
134 }
135
136 /*!
137 * brief Sets the timer period in units of count.
138 *
139 * This function sets the RI compare value. If the counter value equals to the compare value,
140 * it will generate an interrupt.
141 *
142 * note Users can call the utility macros provided in fsl_common.h to convert to ticks
143 *
144 * param base RIT peripheral base address
145 * param count Timer period in units of ticks
146 */
RIT_SetTimerCompare(RIT_Type * base,uint64_t count)147 void RIT_SetTimerCompare(RIT_Type *base, uint64_t count)
148 {
149 /* Disable RIT timers */
150 base->CTRL &= ~RIT_CTRL_RITEN_MASK;
151 base->COMPVAL = (uint32_t)count;
152 base->COMPVAL_H = (uint16_t)(count >> 32U);
153 }
154
155 /*!
156 * brief Sets the mask bit of count compare.
157 *
158 * This function sets the RI mask value. A 1 written to any bit will force the compare to
159 * be true for the corresponding bit of the counter and compare register (causes the comparison of
160 * the register bits to be always true).
161 *
162 * note Users can call the utility macros provided in fsl_common.h to convert to ticks
163 *
164 * param base RIT peripheral base address
165 * param count Timer period in units of ticks
166 */
RIT_SetMaskBit(RIT_Type * base,uint64_t count)167 void RIT_SetMaskBit(RIT_Type *base, uint64_t count)
168 {
169 base->MASK = (uint32_t)count;
170 base->MASK_H = (uint16_t)(count >> 32U);
171 }
172
173 /*!
174 * brief Reads the current value of compare register.
175 *
176 * note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
177 *
178 * param base RIT peripheral base address
179 *
180 * return Current RI compare value
181 */
RIT_GetCompareTimerCount(RIT_Type * base)182 uint64_t RIT_GetCompareTimerCount(RIT_Type *base)
183 {
184 uint32_t valueH;
185 uint32_t valueL = 0U;
186
187 /* COMPVAL_H should be read before COMPVAL */
188 valueH = (base->COMPVAL_H & RIT_COMPVAL_H_RICOMP_MASK);
189 valueL = base->COMPVAL;
190
191 return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
192 }
193
194 /*!
195 * brief Reads the current timer counting value of counter register.
196 *
197 * This function returns the real-time timer counting value, in a range from 0 to a
198 * timer period.
199 *
200 * note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
201 *
202 * param base RIT peripheral base address
203 *
204 * return Current timer counting value in ticks
205 */
RIT_GetCounterTimerCount(RIT_Type * base)206 uint64_t RIT_GetCounterTimerCount(RIT_Type *base)
207 {
208 uint32_t valueH;
209 uint32_t valueL = 0U;
210
211 /* COUNTER_H should be read before COUNTER */
212 valueH = (base->COUNTER_H & RIT_COUNTER_H_RICOUNTER_MASK);
213 valueL = base->COUNTER;
214
215 return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
216 }
217
218 /*!
219 * brief Reads the current value of mask register.
220 *
221 * note Users can call the utility macros provided in fsl_common.h to convert ticks to usec or msec
222 *
223 * param base RIT peripheral base address
224 *
225 * return Current RI mask value
226 */
RIT_GetMaskTimerCount(RIT_Type * base)227 uint64_t RIT_GetMaskTimerCount(RIT_Type *base)
228 {
229 uint32_t valueH;
230 uint32_t valueL = 0U;
231
232 /* MASK_H should be read before MASK */
233 valueH = (base->MASK_H & RIT_MASK_H_RIMASK_MASK);
234 valueL = base->MASK;
235
236 return (((uint64_t)valueH << 32U) + (uint64_t)(valueL));
237 }
238
