1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #ifndef _FSL_GPC_H_
11 #define _FSL_GPC_H_
12
13 #include "fsl_common.h"
14
15 /*!
16 * @addtogroup gpc
17 * @{
18 */
19
20 /*******************************************************************************
21 * Definitions
22 ******************************************************************************/
23
24 /*! @name Driver version */
25 /*@{*/
26 /*! @brief GPC driver version 2.1.1. */
27 #define FSL_GPC_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
28 /*@}*/
29
30 #if defined(__cplusplus)
31 extern "C" {
32 #endif
33
34 /*******************************************************************************
35 * API
36 ******************************************************************************/
37
38 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM) && FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM)
39 /*!
40 * @brief Allow all the IRQ/Events within the charge of GPC.
41 *
42 * @param base GPC peripheral base address.
43 */
GPC_AllowIRQs(GPC_Type * base)44 static inline void GPC_AllowIRQs(GPC_Type *base)
45 {
46 base->CNTR &= ~GPC_CNTR_GPCIRQM_MASK; /* Events would not be masked. */
47 }
48
49 /*!
50 * @brief Disallow all the IRQ/Events within the charge of GPC.
51 *
52 * @param base GPC peripheral base address.
53 */
GPC_DisallowIRQs(GPC_Type * base)54 static inline void GPC_DisallowIRQs(GPC_Type *base)
55 {
56 base->CNTR |= GPC_CNTR_GPCIRQM_MASK; /* Mask all the events. */
57 }
58 #endif /* FSL_FEATURE_GPC_HAS_CNTR_GPCIRQM */
59
60 /*!
61 * @brief Enable the IRQ.
62 *
63 * @param base GPC peripheral base address.
64 * @param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
65 */
66 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId);
67
68 /*!
69 * @brief Disable the IRQ.
70 *
71 * @param base GPC peripheral base address.
72 * @param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms.
73 */
74 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId);
75
76 /*!
77 * @brief Get the IRQ/Event flag.
78 *
79 * @param base GPC peripheral base address.
80 * @param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
81 * @return Indicated IRQ/Event is asserted or not.
82 */
83 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId);
84
85 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_L2PGE) && FSL_FEATURE_GPC_HAS_CNTR_L2PGE)
86 /*!
87 * @brief L2 Cache Power Gate Enable
88 *
89 * This function configures the L2 cache if it will keep power when in low power mode.
90 * When the L2 cache power is OFF, L2 cache will be power down once when CPU core is power down
91 * and will be hardware invalidated automatically when CPU core is re-power up.
92 * When the L2 cache power is ON, L2 cache will keep power on even if CPU core is power down and
93 * will not be hardware invalidated.
94 * When CPU core is re-power up, the default setting is OFF.
95 *
96 * @param base GPC peripheral base address.
97 * @param enable Enable the request or not.
98 */
GPC_RequestL2CachePowerDown(GPC_Type * base,bool enable)99 static inline void GPC_RequestL2CachePowerDown(GPC_Type *base, bool enable)
100 {
101 if (enable)
102 {
103 base->CNTR |= GPC_CNTR_L2_PGE_MASK; /* OFF. */
104 }
105 else
106 {
107 base->CNTR &= ~GPC_CNTR_L2_PGE_MASK; /* ON. */
108 }
109 }
110 #endif /* FSL_FEATURE_GPC_HAS_CNTR_L2PGE */
111
112 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE) && FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE)
113 /*!
114 * @brief FLEXRAM PDRAM0 Power Gate Enable
115 *
116 * This function configures the FLEXRAM PDRAM0 if it will keep power when cpu core is power down.
117 * When the PDRAM0 Power is 1, PDRAM0 will be power down once when CPU core is power down.
118 * When the PDRAM0 Power is 0, PDRAM0 will keep power on even if CPU core is power down.
119 * When CPU core is re-power up, the default setting is 1.
120 *
121 * @param base GPC peripheral base address.
122 * @param enable Enable the request or not.
123 */
GPC_RequestPdram0PowerDown(GPC_Type * base,bool enable)124 static inline void GPC_RequestPdram0PowerDown(GPC_Type *base, bool enable)
125 {
126 if (enable)
127 {
128 base->CNTR |= GPC_CNTR_PDRAM0_PGE_MASK; /* OFF. */
129 }
130 else
131 {
132 base->CNTR &= ~GPC_CNTR_PDRAM0_PGE_MASK; /* ON. */
133 }
134 }
135 #endif /* FSL_FEATURE_GPC_HAS_CNTR_PDRAM0PGE */
136
137 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_VADC) && FSL_FEATURE_GPC_HAS_CNTR_VADC)
138 /*!
139 * @brief VADC power down.
140 *
141 * This function requests the VADC power down.
142 *
143 * @param base GPC peripheral base address.
144 * @param enable Enable the request or not.
145 */
GPC_RequestVADCPowerDown(GPC_Type * base,bool enable)146 static inline void GPC_RequestVADCPowerDown(GPC_Type *base, bool enable)
147 {
148 if (enable)
149 {
150 base->CNTR &= ~GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC power down. */
151 }
152 else
153 {
154 base->CNTR |= GPC_CNTR_VADC_EXT_PWD_N_MASK; /* VADC not power down. */
155 }
156 }
157
158 /*!
159 * @brief Checks if the VADC is power off.
160 *
161 * @param base GPC peripheral base address.
162 * @return Whether the VADC is power off or not.
163 */
GPC_GetVADCPowerDownFlag(GPC_Type * base)164 static inline bool GPC_GetVADCPowerDownFlag(GPC_Type *base)
165 {
166 return (GPC_CNTR_VADC_ANALOG_OFF_MASK == (GPC_CNTR_VADC_ANALOG_OFF_MASK & base->CNTR));
167 }
168 #endif /* FSL_FEATURE_GPC_HAS_CNTR_VADC */
169
170 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR) && FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR)
171 /*!
172 * @brief Checks if the DVFS0 is requesting for frequency/voltage update.
173 *
174 * @param base GPC peripheral base address.
175 * @return Whether the DVFS0 is requesting for frequency/voltage update.
176 */
GPC_HasDVFS0ChangeRequest(GPC_Type * base)177 static inline bool GPC_HasDVFS0ChangeRequest(GPC_Type *base)
178 {
179 return (GPC_CNTR_DVFS0CR_MASK == (GPC_CNTR_DVFS0CR_MASK & base->CNTR));
180 }
181 #endif /* FSL_FEATURE_GPC_HAS_CNTR_DVFS0CR */
182
183 #if (defined(FSL_FEATURE_GPC_HAS_CNTR_DISPLAY) && FSL_FEATURE_GPC_HAS_CNTR_DISPLAY)
184 /*!
185 * @brief Requests the display power switch sequence.
186 *
187 * @param base GPC peripheral base address.
188 * @param enable Enable the power on sequence, or the power down sequence.
189 */
GPC_RequestDisplayPowerOn(GPC_Type * base,bool enable)190 static inline void GPC_RequestDisplayPowerOn(GPC_Type *base, bool enable)
191 {
192 if (enable)
193 {
194 base->CNTR |= GPC_CNTR_DISPLAY_PUP_REQ_MASK; /* Power on sequence. */
195 }
196 else
197 {
198 base->CNTR |= GPC_CNTR_DISPLAY_PDN_REQ_MASK; /* Power down sequence. */
199 }
200 }
201 #endif /* FSL_FEATURE_GPC_HAS_CNTR_DISPLAY */
202
203 /*!
204 * @brief Requests the MEGA power switch sequence.
205 *
206 * @param base GPC peripheral base address.
207 * @param enable Enable the power on sequence, or the power down sequence.
208 */
GPC_RequestMEGAPowerOn(GPC_Type * base,bool enable)209 static inline void GPC_RequestMEGAPowerOn(GPC_Type *base, bool enable)
210 {
211 if (enable)
212 {
213 base->CNTR |= GPC_CNTR_MEGA_PUP_REQ_MASK; /* Power on sequence. */
214 }
215 else
216 {
217 base->CNTR |= GPC_CNTR_MEGA_PDN_REQ_MASK; /* Power down sequence. */
218 }
219 }
220
221 /*!
222 * @}
223 */
224
225 #if defined(__cplusplus)
226 }
227 #endif
228 /*!
229 * @}
230 */
231 #endif /* _FSL_GPC_H_ */
232
