1 /*
2 * Copyright (c) 2016, Freescale Semiconductor, Inc.
3 * Copyright 2016-2019 NXP
4 * All rights reserved.
5 *
6 *
7 * SPDX-License-Identifier: BSD-3-Clause
8 */
9
10 #include "fsl_gpc.h"
11
12 /* Component ID definition, used by tools. */
13 #ifndef FSL_COMPONENT_ID
14 #define FSL_COMPONENT_ID "platform.drivers.gpc_1"
15 #endif
16
17 /*!
18 * brief Enable the IRQ.
19 *
20 * param base GPC peripheral base address.
21 * param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
22 */
GPC_EnableIRQ(GPC_Type * base,uint32_t irqId)23 void GPC_EnableIRQ(GPC_Type *base, uint32_t irqId)
24 {
25 uint32_t irqRegNum = irqId / 32U;
26 uint32_t irqRegShiftNum = irqId % 32U;
27
28 assert(irqRegNum <= GPC_IMR_COUNT);
29
30 #if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
31 if (irqRegNum == GPC_IMR_COUNT)
32 {
33 base->IMR5 &= ~(1UL << irqRegShiftNum);
34 }
35 else
36 {
37 base->IMR[irqRegNum] &= ~(1UL << irqRegShiftNum);
38 }
39 #else
40 assert(irqRegNum > 0U);
41 base->IMR[irqRegNum - 1UL] &= ~(1UL << irqRegShiftNum);
42 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
43 }
44
45 /*!
46 * brief Disable the IRQ.
47 *
48 * param base GPC peripheral base address.
49 * param irqId ID number of IRQ to be disabled, available range is 32-159. 0-31 is available in some platforms.
50 */
GPC_DisableIRQ(GPC_Type * base,uint32_t irqId)51 void GPC_DisableIRQ(GPC_Type *base, uint32_t irqId)
52 {
53 uint32_t irqRegNum = irqId / 32U;
54 uint32_t irqRegShiftNum = irqId % 32U;
55
56 assert(irqRegNum <= GPC_IMR_COUNT);
57
58 #if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
59 if (irqRegNum == GPC_IMR_COUNT)
60 {
61 base->IMR5 |= (1UL << irqRegShiftNum);
62 }
63 else
64 {
65 base->IMR[irqRegNum] |= (1UL << irqRegShiftNum);
66 }
67 #else
68 assert(irqRegNum > 0U);
69 base->IMR[irqRegNum - 1UL] |= (1UL << irqRegShiftNum);
70 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
71 }
72
73 /*!
74 * brief Get the IRQ/Event flag.
75 *
76 * param base GPC peripheral base address.
77 * param irqId ID number of IRQ to be enabled, available range is 32-159. 0-31 is available in some platforms.
78 * return Indicated IRQ/Event is asserted or not.
79 */
GPC_GetIRQStatusFlag(GPC_Type * base,uint32_t irqId)80 bool GPC_GetIRQStatusFlag(GPC_Type *base, uint32_t irqId)
81 {
82 uint32_t irqRegNum = irqId / 32U;
83 uint32_t irqRegShiftNum = irqId % 32U;
84 uint32_t ret;
85
86 assert(irqRegNum <= GPC_IMR_COUNT);
87
88 #if ((defined FSL_FEATURE_GPC_HAS_IRQ_0_31) && FSL_FEATURE_GPC_HAS_IRQ_0_31)
89 if (irqRegNum == GPC_IMR_COUNT)
90 {
91 ret = base->ISR5 & (1UL << irqRegShiftNum);
92 }
93 else
94 {
95 ret = base->ISR[irqRegNum] & (1UL << irqRegShiftNum);
96 }
97 #else
98 assert(irqRegNum > 0U);
99 ret = base->ISR[irqRegNum - 1UL] & (1UL << irqRegShiftNum);
100 #endif /* FSL_FEATURE_GPC_HAS_IRQ_0_31 */
101
102 return (1UL << irqRegShiftNum) == ret;
103 }
104
