1 /*
2 * Copyright 2017, 2019-2020 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_dpu.h"
10
11 /*******************************************************************************
12 * Definitions
13 ******************************************************************************/
14
15 /* Component ID definition, used by tools. */
16 #ifndef FSL_COMPONENT_ID
17 #define FSL_COMPONENT_ID "platform.drivers.dpu"
18 #endif
19
20 typedef struct
21 {
22 __IO uint32_t IPIDENTIFIER;
23 uint8_t RESERVED_0[60];
24 __IO uint32_t LOCKUNLOCK;
25 __IO uint32_t LOCKSTATUS;
26 __IO uint32_t USERINTERRUPTMASK[2];
27 __IO uint32_t INTERRUPTENABLE[2];
28 __IO uint32_t INTERRUPTPRESET[2];
29 __IO uint32_t INTERRUPTCLEAR[2];
30 __IO uint32_t INTERRUPTSTATUS[2];
31 uint8_t RESERVED_1[16];
32 __IO uint32_t USERINTERRUPTENABLE[2];
33 __IO uint32_t USERINTERRUPTPRESET[2];
34 __IO uint32_t USERINTERRUPTCLEAR[2];
35 __IO uint32_t USERINTERRUPTSTATUS[2];
36 uint8_t RESERVED_2[96];
37 __IO uint32_t GENERALPURPOSE;
38 } DPU_COMCTRL_Type;
39
40 typedef struct
41 {
42 __IO uint32_t BASEADDRESS;
43 __IO uint32_t SOURCEBUFFERATTRIBUTES;
44 __IO uint32_t SOURCEBUFFERDIMENSION;
45 __IO uint32_t COLORCOMPONENTBITS;
46 __IO uint32_t COLORCOMPONENTSHIFT;
47 __IO uint32_t LAYEROFFSET;
48 __IO uint32_t CLIPWINDOWOFFSET;
49 __IO uint32_t CLIPWINDOWDIMENSIONS;
50 __IO uint32_t CONSTANTCOLOR;
51 __IO uint32_t LAYERPROPERTY;
52 } DPU_SUBLAYER_CONTROL_Type;
53
54 typedef struct
55 {
56 __IO uint32_t LOCKUNLOCK;
57 __I uint32_t LOCKSTATUS;
58 __IO uint32_t STATIC;
59 __IO uint32_t DYNAMIC;
60 __IO uint32_t REQUEST;
61 __O uint32_t TRIGGER;
62 __I uint32_t STATUS;
63 } DPU_PIPELINE_Type;
64
65 typedef struct
66 {
67 __IO uint32_t LOCKUNLOCK;
68 __IO uint32_t LOCKSTATUS;
69 __IO uint32_t STATICCONTROL;
70 __IO uint32_t BURSTBUFFERMANAGEMENT;
71 DPU_SUBLAYER_CONTROL_Type LAYER[1];
72 __IO uint32_t FRAMEDIMENSIONS;
73 __IO uint32_t FRAMERESAMPLING;
74 __IO uint32_t CONTROL;
75 __IO uint32_t CONTROLTRIGGER;
76 __IO uint32_t START;
77 __IO uint32_t FETCHTYPE;
78 __IO uint32_t BURSTBUFFERPROPERTIES;
79 __IO uint32_t HIDDENSTATUS;
80 } DPU_FETCHECO_Type;
81
82 typedef struct
83 {
84 __IO uint32_t LOCKUNLOCK;
85 __IO uint32_t LOCKSTATUS;
86 __IO uint32_t STATICCONTROL;
87 __IO uint32_t FRAMEDIMENSIONS;
88 __IO uint32_t CONSTANTCOLOR;
89 __IO uint32_t CONTROLTRIGGER;
90 __IO uint32_t START;
91 __IO uint32_t STATUS;
92 } DPU_CONSTFRAME_Type;
93
94 typedef struct
95 {
96 __IO uint32_t LOCKUNLOCK;
97 __IO uint32_t LOCKSTATUS;
98 __IO uint32_t STATICCONTROL;
99 __IO uint32_t CONTROL;
100 __IO uint32_t NEUTRALBORDER;
101 __IO uint32_t CONSTANTCOLOR;
102 __IO uint32_t COLORREDBLENDFUNCTION;
103 __IO uint32_t COLORGREENBLENDFUNCTION;
104 __IO uint32_t COLORBLUEBLENDFUNCTION;
105 __IO uint32_t ALPHABLENDFUNCTION;
106 __IO uint32_t BLENDMODE1;
107 __IO uint32_t BLENDMODE2;
108 __IO uint32_t DIRECTSETUP;
109 __IO uint32_t PRIMCONTROLWORD;
110 __IO uint32_t SECCONTROLWORD;
111 } DPU_BLITBLEND_Type;
112
113 typedef struct
114 {
115 __IO uint32_t LOCKUNLOCK;
116 __IO uint32_t LOCKSTATUS;
117 __IO uint32_t CLOCKCTRL;
118 __IO uint32_t POLARITYCTRL;
119 __IO uint32_t SRCSELECT;
120 uint8_t RESERVED[12];
121 } DPU_DISENGCONF_BLOCK_Type;
122
123 typedef struct
124 {
125 DPU_DISENGCONF_BLOCK_Type DISPLAY[2];
126 } DPU_DISENGCONF_Type;
127
128 typedef struct
129 {
130 __IO uint32_t LOCKUNLOCK;
131 __IO uint32_t LOCKSTATUS;
132 __IO uint32_t STATICCONTROL;
133 __IO uint32_t CONTROL;
134 __IO uint32_t SOFTWAREKICK;
135 __IO uint32_t STATUS;
136 __IO uint32_t CONTROLWORD;
137 __IO uint32_t CURPIXELCNT;
138 __IO uint32_t LASTPIXELCNT;
139 __IO uint32_t PERFCOUNTER;
140 } DPU_EXTDST_Type;
141
142 typedef struct
143 {
144 __IO uint32_t LOCKUNLOCK;
145 __IO uint32_t LOCKSTATUS;
146 __IO uint32_t STATICCONTROL;
147 __IO uint32_t BURSTBUFFERMANAGEMENT;
148 __IO uint32_t RINGBUFSTARTADDR0;
149 __IO uint32_t RINGBUFWRAPADDR0;
150 __IO uint32_t FRAMEPROPERTIES0;
151 DPU_SUBLAYER_CONTROL_Type LAYER[1];
152 __IO uint32_t FRAMEDIMENSIONS;
153 __IO uint32_t FRAMERESAMPLING;
154 __IO uint32_t DECODECONTROL;
155 __IO uint32_t SOURCEBUFFERLENGTH;
156 __IO uint32_t CONTROL;
157 __IO uint32_t CONTROLTRIGGER;
158 __IO uint32_t START;
159 __IO uint32_t FETCHTYPE;
160 __IO uint32_t DECODERSTATUS;
161 __IO uint32_t READADDRESS0;
162 __IO uint32_t BURSTBUFFERPROPERTIES;
163 __IO uint32_t STATUS;
164 __IO uint32_t HIDDENSTATUS;
165 uint8_t RESERVED_0[904];
166 __IO uint32_t COLORPALETTE;
167 } DPU_FETCHDECODER_Type;
168
169 typedef struct
170 {
171 __IO uint32_t LOCKUNLOCK;
172 __IO uint32_t LOCKSTATUS;
173 __IO uint32_t STATICCONTROL;
174 __IO uint32_t BURSTBUFFERMANAGEMENT;
175 DPU_SUBLAYER_CONTROL_Type LAYER[8];
176 __IO uint32_t FRAMEDIMENSIONS;
177 __IO uint32_t FRAMERESAMPLING;
178 __IO uint32_t CONTROL;
179 __IO uint32_t TRIGGERENABLE;
180 __IO uint32_t CONTROLTRIGGER;
181 __IO uint32_t START;
182 __IO uint32_t FETCHTYPE;
183 __IO uint32_t BURSTBUFFERPROPERTIES;
184 __IO uint32_t STATUS;
185 __IO uint32_t HIDDENSTATUS;
186 uint8_t RESERVED_0[648];
187 __IO uint32_t COLORPALETTE;
188 } DPU_FETCHLAYER_Type;
189
190 typedef struct
191 {
192 __IO uint32_t LOCKUNLOCK;
193 __IO uint32_t LOCKSTATUS;
194 __IO uint32_t STATICCONTROL;
195 __IO uint32_t BURSTBUFFERMANAGEMENT;
196 DPU_SUBLAYER_CONTROL_Type LAYER[8];
197 __IO uint32_t FRAMEDIMENSIONS;
198 __IO uint32_t FRAMERESAMPLING;
199 __IO uint32_t WARPCONTROL;
200 __IO uint32_t ARBSTARTX;
201 __IO uint32_t ARBSTARTY;
202 __IO uint32_t ARBDELTA;
203 __IO uint32_t FIRPOSITIONS;
204 __IO uint32_t FIRCOEFFICIENTS;
205 __IO uint32_t CONTROL;
206 __IO uint32_t TRIGGERENABLE;
207 __IO uint32_t CONTROLTRIGGER;
208 __IO uint32_t START;
209 __IO uint32_t FETCHTYPE;
210 __IO uint32_t BURSTBUFFERPROPERTIES;
211 __IO uint32_t STATUS;
212 __IO uint32_t HIDDENSTATUS;
213 } DPU_FETCHWARP_Type;
214
215 typedef struct
216 {
217 __IO uint32_t LOCKUNLOCK;
218 __IO uint32_t LOCKSTATUS;
219 __IO uint32_t FGSTCTRL;
220 __IO uint32_t HTCFG1;
221 __IO uint32_t HTCFG2;
222 __IO uint32_t VTCFG1;
223 __IO uint32_t VTCFG2;
224 __IO uint32_t INTCONFIG[4];
225 __IO uint32_t PKICKCONFIG;
226 __IO uint32_t SKICKCONFIG;
227 __IO uint32_t SECSTATCONFIG;
228 __IO uint32_t FGSRCR1;
229 __IO uint32_t FGSRCR2;
230 __IO uint32_t FGSRCR3;
231 __IO uint32_t FGSRCR4;
232 __IO uint32_t FGSRCR5;
233 __IO uint32_t FGSRCR6;
234 __IO uint32_t FGKSDR;
235 __IO uint32_t PACFG;
236 __IO uint32_t SACFG;
237 __IO uint32_t FGINCTRL;
238 __IO uint32_t FGINCTRLPANIC;
239 __IO uint32_t FGCCR;
240 __IO uint32_t FGENABLE;
241 __IO uint32_t FGSLR;
242 __IO uint32_t FGENSTS;
243 __IO uint32_t FGTIMESTAMP;
244 __IO uint32_t FGCHSTAT;
245 __IO uint32_t FGCHSTATCLR;
246 __IO uint32_t FGSKEWMON;
247 __IO uint32_t FGSFIFOMIN;
248 __IO uint32_t FGSFIFOMAX;
249 __IO uint32_t FGSFIFOFILLCLR;
250 __IO uint32_t FGSREPD;
251 __IO uint32_t FGSRFTD;
252 } DPU_FRAMEGEN_Type;
253
254 typedef struct
255 {
256 __IO uint32_t LOCKUNLOCK;
257 __IO uint32_t LOCKSTATUS;
258 __IO uint32_t STATICCONTROL;
259 __IO uint32_t SETUP1;
260 __IO uint32_t SETUP2;
261 __IO uint32_t CONTROL;
262 } DPU_HSCALER_Type;
263
264 typedef struct
265 {
266 __IO uint32_t LOCKUNLOCK;
267 __IO uint32_t LOCKSTATUS;
268 __IO uint32_t STATICCONTROL;
269 __IO uint32_t CONTROL;
270 __IO uint32_t BLENDCONTROL;
271 __IO uint32_t POSITION;
272 __IO uint32_t PRIMCONTROLWORD;
273 __IO uint32_t SECCONTROLWORD;
274 } DPU_LAYERBLEND_Type;
275
276 typedef struct
277 {
278 __IO uint32_t LOCKUNLOCK;
279 __IO uint32_t LOCKSTATUS;
280 __IO uint32_t STATICCONTROL;
281 __IO uint32_t SETUP1;
282 __IO uint32_t SETUP2;
283 __IO uint32_t SETUP3;
284 __IO uint32_t SETUP4;
285 __IO uint32_t SETUP5;
286 __IO uint32_t CONTROL;
287 } DPU_VSCALER_Type;
288
289 typedef struct
290 {
291 __IO uint32_t SSQCNTS;
292 uint8_t RESERVED_0[1020];
293 __IO uint32_t LOCKUNLOCK;
294 __IO uint32_t LOCKSTATUS;
295 __IO uint32_t SSQCYCLE;
296 __IO uint32_t SWRESET;
297 __IO uint32_t TCON_CTRL;
298 __IO uint32_t RSDSINVCTRL;
299 __IO uint32_t MAPBIT3_0;
300 __IO uint32_t MAPBIT7_4;
301 __IO uint32_t MAPBIT11_8;
302 __IO uint32_t MAPBIT15_12;
303 __IO uint32_t MAPBIT19_16;
304 __IO uint32_t MAPBIT23_20;
305 __IO uint32_t MAPBIT27_24;
306 __IO uint32_t MAPBIT31_28;
307 __IO uint32_t MAPBIT34_32;
308 __IO uint32_t MAPBIT3_0_DUAL;
309 __IO uint32_t MAPBIT7_4_DUAL;
310 __IO uint32_t MAPBIT11_8_DUAL;
311 __IO uint32_t MAPBIT15_12_DUAL;
312 __IO uint32_t MAPBIT19_16_DUAL;
313 __IO uint32_t MAPBIT23_20_DUAL;
314 __IO uint32_t MAPBIT27_24_DUAL;
315 __IO uint32_t MAPBIT31_28_DUAL;
316 __IO uint32_t MAPBIT34_32_DUAL;
317
318 struct
319 {
320 __IO uint32_t SPGPOSON;
321 __IO uint32_t SPGMASKON;
322 __IO uint32_t SPGPOSOFF;
323 __IO uint32_t SPGMASKOFF;
324 } SPG[12];
325
326 struct
327 {
328 __IO uint32_t SMXSIGS;
329 __IO uint32_t SMXFCTTABLE;
330 } SMX[12];
331
332 __IO uint32_t RESET_OVER_UNFERFLOW;
333 __IO uint32_t DUAL_DEBUG;
334 } DPU_TCON_Type;
335
336 typedef struct
337 {
338 __IO uint32_t LOCKUNLOCK;
339 __IO uint32_t LOCKSTATUS;
340 __IO uint32_t STATICCONTROL;
341 __IO uint32_t CONTROL;
342 __IO uint32_t RASTEROPERATIONINDICES;
343 __IO uint32_t PRIMCONTROLWORD;
344 __IO uint32_t SECCONTROLWORD;
345 __IO uint32_t TERTCONTROLWORD;
346 } DPU_ROP_Type;
347
348 typedef struct
349 {
350 __IO uint32_t LOCKUNLOCK;
351 __IO uint32_t LOCKSTATUS;
352 __IO uint32_t STATICCONTROL;
353 __IO uint32_t BURSTBUFFERMANAGEMENT;
354 __IO uint32_t RINGBUFSTARTADDR;
355 __IO uint32_t RINGBUFWRAPADDR;
356 __IO uint32_t BASEADDRESS;
357 __IO uint32_t DESTINATIONBUFFERATTRIBUTES;
358 __IO uint32_t DESTINATIONBUFFERDIMENSION;
359 __IO uint32_t FRAMEOFFSET;
360 __IO uint32_t COLORCOMPONENTBITS;
361 __IO uint32_t COLORCOMPONENTSHIFT;
362 __IO uint32_t CONTROL;
363 __IO uint32_t ENCODECONTROL;
364 __IO uint32_t DESTINATIONBUFFERLENGTH;
365 __IO uint32_t START;
366 __IO uint32_t ENCODERSTATUS;
367 __IO uint32_t WRITEADDRESS;
368 __IO uint32_t FRAMEPROPERTIES;
369 __IO uint32_t BURSTBUFFERPROPERTIES;
370 __IO uint32_t LASTCONTROLWORD;
371 __IO uint32_t PERFCOUNTER;
372 __IO uint32_t STATUS;
373 } DPU_STORE_Type;
374
375 typedef struct
376 {
377 __IO uint32_t LOCKUNLOCK;
378 __IO uint32_t LOCKSTATUS;
379 __IO uint32_t STATICCONTROL;
380 __IO uint32_t PANICCOLOR;
381 struct
382 {
383 __IO uint32_t EVALCONTROL;
384 __IO uint32_t EVALUPPERLEFT;
385 __IO uint32_t EVALLOWERRIGHT;
386 __IO uint32_t SIGCRCREDREF;
387 __IO uint32_t SIGCRCGREENREF;
388 __IO uint32_t SIGCRCBLUEREF;
389 __IO uint32_t SIGCRCRED;
390 __IO uint32_t SIGCRCGREEN;
391 __IO uint32_t SIGCRCBLUE;
392 } WINDOW[8];
393
394 __IO uint32_t SHADOWLOAD;
395 __IO uint32_t CONTINUOUSMODE;
396 __IO uint32_t SOFTWAREKICK;
397 __IO uint32_t STATUS;
398 } DPU_SIG_Type;
399
400 typedef struct
401 {
402 __IO uint32_t LOCKUNLOCK;
403 __IO uint32_t LOCKSTATUS;
404 __IO uint32_t STATICCONTROL;
405 __IO uint32_t CONTROL;
406 __IO uint32_t RED[2];
407 __IO uint32_t GREEN[2];
408 __IO uint32_t BLUE[2];
409 __IO uint32_t ALPHA[2];
410 __IO uint32_t OFFSETVECTOR[2];
411 __IO uint32_t LASTCONTROLWORD;
412 } DPU_MATRIX_Type;
413
414 typedef struct
415 {
416 __IO uint32_t LOCKUNLOCK;
417 __IO uint32_t LOCKSTATUS;
418 __IO uint32_t CONTROL;
419 __IO uint32_t DITHERCONTROL;
420 __IO uint32_t RELEASE;
421 } DPU_DITHER_Type;
422
423 typedef struct
424 {
425 __IO uint32_t LOCKUNLOCK;
426 __IO uint32_t LOCKSTATUS;
427 __IO uint32_t STATICCONTROL;
428 __IO uint32_t LUTSTART;
429 __IO uint32_t LUTDELTAS;
430 __IO uint32_t CONTROL;
431 __IO uint32_t STATUS;
432 __IO uint32_t LASTCONTROLWORD;
433 } DPU_GAMMACOR_Type;
434
435 typedef struct
436 {
437 DPU_FRAMEGEN_Type FRAMEGEN;
438 uint8_t RESERVED_0[872];
439 DPU_MATRIX_Type MATRIX;
440 uint8_t RESERVED_1[964];
441 DPU_GAMMACOR_Type GAMMACOR;
442 uint8_t RESERVED_2[992];
443 DPU_DITHER_Type DITHER;
444 uint8_t RESERVED_3[1004];
445 DPU_TCON_Type TCON;
446 uint8_t RESERVED_4[632];
447 DPU_SIG_Type SIG;
448 } DPU_DISPLAY_Type;
449
450 #define DPU_INT_GROUP_NUM 2U /* Interrupt group number. */
451 #define DPU_DISPLAY_COUNT 2U /* Display number. */
452 #define DPU_SIG_EAVL_WINDOW_COUNT 8U /* Signature unit evaluation window count. */
453
454 #define DPU_MAKE_DIMENSION(heigth, width) (((uint32_t)(heigth) << 16U) | ((uint32_t)(width) << 0U))
455 #define DPU_MAKE_POSITION(offsetY, offsetX) (((uint32_t)(offsetY) << 16U) | ((uint32_t)(offsetX) << 0U))
456 #define DPU_REG(base, offset) *((volatile uint32_t *)((uint32_t)(base) + (offset)))
457
458 /* Make the register <fetch_unit>_StaticControl */
459 #define DPU_MAKE_SOURCEBUFFERATTRIBUTES(bitsPerPixel, stride) \
460 ((((uint32_t)(bitsPerPixel) << 16U) & 0x003F0000U) | ((((uint32_t)(stride)-1U) << 0U) & 0x0000FFFFU))
461
462 #define DPU_MAKE_DESTINATIONBUFFERATTRIBUTES(bitsPerPixel, stride) \
463 ((((uint32_t)(bitsPerPixel) << 24U) & 0x7F000000U) | ((((uint32_t)(stride)-1U) << 0U) & 0x0001FFFFU))
464
465 #define DPU_SCALER_CONTROL_OUTPUTSIZE(output_size) ((((uint32_t)(output_size)) << 16U) & 0x3FFF0000U)
466 #define DPU_SCALER_CONTROL_SCALEMODE_MASK (0x10U)
467 #define DPU_SCALER_CONTROL_FILTERMODE_MASK (0x100U)
468 #define DPU_SCALER_CONTROL_MODE_MASK (0x01U)
469
470 /* Offset of register <unit>_StaticControl in each unit control block. */
471 #define DPU_STATIC_CONTROL_OFFSET 0x8U
472
473 /* Mask of the register feild ShdEn */
474 #define DPU_UNIT_SHDEN_MASK 0x01U
475
476 #define DPU_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK 0x80000000U
477 #define DPU_LAYERPROPERTY_CLIPWINDOWENABLE_MASK 0x40000000U
478 #define DPU_LAYERPROPERTY_PALETTEENABLE_MASK 0x1U
479 #define DPU_LAYERPROPERTY_GAMMAREMOVE_MASK 0x100000U
480
481 #define DPU_EXTDST_STATICCONTROL_KICKMODE_MASK 0x100U
482 #define DPU_EXTDST_CONTROL_GAMMAAPPLYENABLE_MASK 0x01U
483
484 /* Register TiggerEnable offset in FetchWarp unit. */
485 #define DPU_FETCHWARP_TRIGGERENABLE_OFFSET 0x174U
486 /* Register TiggerEnable offset in FetchLayer unit. */
487 #define DPU_FETCHLAYER_TRIGGERENABLE_OFFSET 0x15CU
488 /* Register Request offset in pipeline unit. */
489 #define DPU_PIPELINE_REQUEST_OFFSET 0x10U
490 /* Register Trigger offset in pipeline unit. */
491 #define DPU_PIPELINE_TRIGGER_OFFSET 0x14U
492 /* Mask of clken in <unit>_dynamic register. */
493 #define DPU_DYNAMIC_CLKEN_MASK 0x03000000U
494 /* Offset of <unit>_BurstBufferManagement. */
495 #define DPU_BURSTBUFFERMANAGEMENT_OFFSET 0x0CU
496
497 #define DPU_PALETTE_OFFSET 0x400U
498
499 #if DPU_USE_GENERATE_HEADER
500 #define DPU_STORE9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.STORE9_DYNAMIC)
501 #define DPU_FETCHWARP9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.FETCHWARP9_DYNAMIC)
502 #define DPU_FETCHDECODE9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.FETCHDECODE9_DYNAMIC)
503 #define DPU_ROP9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.ROP9_DYNAMIC)
504 #define DPU_BLITBLEND9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.BLITBLEND9_DYNAMIC)
505 #define DPU_H_SCALER9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.HSCALER9_DYNAMIC)
506 #define DPU_V_SCALER9_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.VSCALER9_DYNAMIC)
507 #define DPU_EXTDST0_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST0_DYNAMIC)
508 #define DPU_EXTDST4_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST4_DYNAMIC)
509 #define DPU_EXTDST1_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST1_DYNAMIC)
510 #define DPU_EXTDST5_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.EXTDST5_DYNAMIC)
511 #define DPU_FETCHWARP2_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.FETCHWARP2_DYNAMIC)
512 #define DPU_FETCHDECODE0_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.FETCHDECODE0_DYNAMIC)
513 #define DPU_FETCHDECODE1_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.FETCHDECODE1_DYNAMIC)
514 #define DPU_H_SCALER4_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.HSCALER4_DYNAMIC)
515 #define DPU_V_SCALER4_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.VSCALER4_DYNAMIC)
516 #define DPU_H_SCALER5_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.HSCALER5_DYNAMIC)
517 #define DPU_V_SCALER5_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.VSCALER5_DYNAMIC)
518 #define DPU_LAYERBLEND0_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.LAYERBLEND0_DYNAMIC)
519 #define DPU_LAYERBLEND1_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.LAYERBLEND1_DYNAMIC)
520 #define DPU_LAYERBLEND2_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.LAYERBLEND2_DYNAMIC)
521 #define DPU_LAYERBLEND3_DYNAMIC_OFFSET DPU_UNIT_OFFSET(PIXENGCFG.LAYERBLEND3_DYNAMIC)
522
523 #else /* DPU_USE_GENERATE_HEADER */
524
525 #define DPU_STORE9_DYNAMIC_OFFSET 0x094C
526 #define DPU_FETCHWARP9_DYNAMIC_OFFSET 0x0848
527 #define DPU_FETCHDECODE9_DYNAMIC_OFFSET 0x0828
528 #define DPU_ROP9_DYNAMIC_OFFSET 0x0868
529 #define DPU_BLITBLEND9_DYNAMIC_OFFSET 0x0928
530 #define DPU_H_SCALER9_DYNAMIC_OFFSET 0x08C8
531 #define DPU_V_SCALER9_DYNAMIC_OFFSET 0x08E8
532 #define DPU_EXTDST0_DYNAMIC_OFFSET 0x098C
533 #define DPU_EXTDST4_DYNAMIC_OFFSET 0x09CC
534 #define DPU_EXTDST1_DYNAMIC_OFFSET 0x0a0C
535 #define DPU_EXTDST5_DYNAMIC_OFFSET 0x0a4C
536 #define DPU_FETCHWARP2_DYNAMIC_OFFSET 0x0a68
537 #define DPU_FETCHDECODE0_DYNAMIC_OFFSET 0x0a88
538 #define DPU_FETCHDECODE1_DYNAMIC_OFFSET 0x0aA8
539 #define DPU_H_SCALER4_DYNAMIC_OFFSET 0x0b08
540 #define DPU_V_SCALER4_DYNAMIC_OFFSET 0x0b28
541 #define DPU_H_SCALER5_DYNAMIC_OFFSET 0x0b68
542 #define DPU_V_SCALER5_DYNAMIC_OFFSET 0x0b88
543 #define DPU_LAYERBLEND0_DYNAMIC_OFFSET 0x0bA8
544 #define DPU_LAYERBLEND1_DYNAMIC_OFFSET 0x0bC8
545 #define DPU_LAYERBLEND2_DYNAMIC_OFFSET 0x0bE8
546 #define DPU_LAYERBLEND3_DYNAMIC_OFFSET 0x0c08
547
548 #endif /* DPU_USE_GENERATE_HEADER */
549
550 #define DPU_STRUCT_OFFSET(structure, member) (uint32_t)(&((structure *)0)->member)
551
552 #define DPU_FETCHECO_FRAMEDIMENSIONS_OFFSET (uint32_t)(&((DPU_FETCHECO_Type *)0)->FRAMEDIMENSIONS)
553 #define DPU_FETCHDECODE_FRAMEDIMENSIONS_OFFSET (uint32_t)(&((DPU_FETCHDECODER_Type *)0)->FRAMEDIMENSIONS)
554 #define DPU_FETCHLAYER_FRAMEDIMENSIONS_OFFSET (uint32_t)(&((DPU_FETCHLAYER_Type *)0)->FRAMEDIMENSIONS)
555 #define DPU_FETCHWARP_FRAMEDIMENSIONS_OFFSET (uint32_t)(&((DPU_FETCHWARP_Type *)0)->FRAMEDIMENSIONS)
556 #define DPU_FETCHECO_FRAMERESAMPLING_OFFSET (uint32_t)(&((DPU_FETCHECO_Type *)0)->FRAMERESAMPLING)
557 #define DPU_FETCHDECODE_FRAMERESAMPLING_OFFSET (uint32_t)(&((DPU_FETCHDECODER_Type *)0)->FRAMERESAMPLING)
558 #define DPU_FETCHLAYER_FRAMERESAMPLING_OFFSET (uint32_t)(&((DPU_FETCHLAYER_Type *)0)->FRAMERESAMPLING)
559 #define DPU_FETCHWARP_FRAMERESAMPLING_OFFSET (uint32_t)(&((DPU_FETCHWARP_Type *)0)->FRAMERESAMPLING)
560 #define DPU_FETCHECO_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHECO_Type *)0)->CONTROL)
561 #define DPU_FETCHDECODE_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHDECODER_Type *)0)->CONTROL)
562 #define DPU_FETCHLAYER_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHLAYER_Type *)0)->CONTROL)
563 #define DPU_FETCHWARP_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHWARP_Type *)0)->CONTROL)
564 #define DPU_FETCHECO_SUBLAYER_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHECO_Type *)0)->LAYER)
565 #define DPU_FETCHDECODE_SUBLAYER_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHDECODER_Type *)0)->LAYER)
566 #define DPU_FETCHLAYER_SUBLAYER_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHLAYER_Type *)0)->LAYER)
567 #define DPU_FETCHWARP_SUBLAYER_CONTROL_OFFSET (uint32_t)(&((DPU_FETCHWARP_Type *)0)->LAYER)
568 #define DPU_FETCHUNIT_BURSTBUFFERMANAGEMENT_OFFSET (uint32_t)(&((DPU_FETCHWARP_Type *)0)->BURSTBUFFERMANAGEMENT)
569
570 #define DPU_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS(x) (((uint32_t)(x) << 0U) & 0xffU)
571 #define DPU_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH(x) (((uint32_t)(x) << 8U) & 0x1f00U)
572
573 #define DPU_MAKE_FETCH_RESAMPLING(swap, deltaX, deltaY, startX, startY) \
574 (((uint32_t)(swap) << 24U) | ((uint32_t)(deltaY) << 18U) | ((uint32_t)(deltaX) << 12U) | \
575 ((uint32_t)(startY) << 6U) | (uint32_t)(startX))
576
577 #define DPU_FETCH_CONTROL_RASTERMODE_MASK 0x7U
578 #define DPU_FETCH_CONTROL_INPUTSELECT_MASK 0x18U
579 #define DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE_MASK 0x20U
580 #define DPU_FETCH_CONTROL_RAWPIXEL_MASK 0x80U
581 #define DPU_FETCH_CONTROL_PALETTEIDXWIDTH_MASK 0x700U
582 #define DPU_FETCH_CONTROL_CLIPCOLOR_MASK 0x10000U
583 #define DPU_FETCH_CONTROL_CLIPLAYER_MASK 0xE0000U
584 #define DPU_FETCH_CONTROL_FILTERMODE_MASK 0x700000U
585
586 #define DPU_FETCH_CONTROL_RASTERMODE(x) ((uint32_t)(x))
587 #define DPU_FETCH_CONTROL_INPUTSELECT(x) ((uint32_t)(x) << 3U)
588 #define DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE(x) ((uint32_t)(x) << 5U)
589 #define DPU_FETCH_CONTROL_RAWPIXEL(x) ((uint32_t)(x) << 7U)
590 #define DPU_FETCH_CONTROL_PALETTEIDXWIDTH(x) ((uint32_t)(x) << 8U)
591 #define DPU_FETCH_CONTROL_CLIPCOLOR(x) ((uint32_t)(x) << 16U)
592 #define DPU_FETCH_CONTROL_CLIPLAYER(x) ((uint32_t)(x) << 17U)
593 #define DPU_FETCH_CONTROL_FILTERMODE(x) ((uint32_t)(x) << 20U)
594
595 #if DPU_USE_GENERATE_HEADER
596 #define DPU_PIPELINE_STATIC_SYNCMODE_MASK DPU_PIXENGCFG_EXTDST0_STATIC_extdst0_Sync_Mode_MASK
597 #define DPU_PIPELINE_STATIC_POWERDOWN_MASK DPU_PIXENGCFG_EXTDST0_STATIC_extdst0_powerdown_MASK
598 #define DPU_PIPELINE_STATIC_DIV(x) DPU_PIXENGCFG_EXTDST0_STATIC_extdst0_div(x)
599 #define DPU_PIPELINE_TRIGGER_SYNC_TRIGGER_MASK DPU_PIXENGCFG_EXTDST0_TRIGGER_extdst0_Sync_Trigger_MASK
600 #define DPU_PIPELINE_TRIGGER_SEQ_COMP_MASK DPU_PIXENGCFG_EXTDST0_TRIGGER_extdst0_trigger_sequence_complete_MASK;
601
602 #define DPU_FETCH_STATICCONTROL_SHDLDREQSTICKY_MASK DPU_FETCHLAYER_STATICCONTROL_ShdLdReqSticky_MASK
603
604 #else /* DPU_USE_GENERATE_HEADER */
605
606 #define DPU_PIPELINE_STATIC_SYNCMODE_MASK (1UL << 8U)
607 #define DPU_PIPELINE_STATIC_POWERDOWN_MASK (1UL << 4U)
608 #define DPU_PIPELINE_STATIC_DIV(x) (((uint32_t)(x) << 16U) & 0x00ff0000U)
609 #define DPU_PIPELINE_TRIGGER_SYNC_TRIGGER_MASK (1UL << 0U)
610 #define DPU_PIPELINE_TRIGGER_SEQ_COMP_MASK (1UL << 4U)
611 #define DPU_STORE_START_Start_MASK (1UL << 0U)
612
613 #define DPU_FETCH_STATICCONTROL_SHDLDREQSTICKY_MASK 0xFF000000U
614
615 #define DPU_LAYERBLEND_STATICCONTROL_ShdEn_MASK (1UL << 0U)
616 #define DPU_LAYERBLEND_STATICCONTROL_ShdTokSel(x) ((uint32_t)(x) << 3U)
617 #define DPU_LAYERBLEND_STATICCONTROL_ShdLdSel(x) ((uint32_t)(x) << 1U)
618
619 #define DPU_LAYERBLEND_BLENDCONTROL_BlendAlpha(x) (((uint32_t)(x)&0xFFU) << 16U)
620 #define DPU_LAYERBLEND_BLENDCONTROL_PRIM_C_BLD_FUNC(x) (((uint32_t)(x)&0x7U) << 0U)
621 #define DPU_LAYERBLEND_BLENDCONTROL_SEC_C_BLD_FUNC(x) (((uint32_t)(x)&0x7U) << 4U)
622 #define DPU_LAYERBLEND_BLENDCONTROL_PRIM_A_BLD_FUNC(x) (((uint32_t)(x)&0x7U) << 8U)
623 #define DPU_LAYERBLEND_BLENDCONTROL_SEC_A_BLD_FUNC(x) (((uint32_t)(x)&0x7U) << 12U)
624
625 #define DPU_LAYERBLEND_CONTROL_MODE_MASK (1UL << 0U)
626 #define DPU_LAYERBLEND_CONTROL_AlphaMaskEnable_MASK (1UL << 2U)
627 #define DPU_LAYERBLEND_CONTROL_AlphaMaskMode_MASK (7UL << 4U)
628 #define DPU_LAYERBLEND_CONTROL_AlphaMaskEnable(x) (((uint32_t)(x)&0x1U) << 2U)
629 #define DPU_LAYERBLEND_CONTROL_AlphaMaskMode(x) (((uint32_t)(x)&0x7U) << 4U)
630
631 #define DPU_FETCHWARP_WARPCONTROL_WarpBitsPerPixel(x) (((uint32_t)(x) << 0U) & 0x3FU)
632 #define DPU_FETCHWARP_WARPCONTROL_WarpCoordinateMode(x) (((uint32_t)(x)&0x03U) << 8U)
633 #define DPU_FETCHWARP_WARPCONTROL_WarpSymmetricOffset(x) (((uint32_t)(x)&0x01U) << 12U)
634
635 #define DPU_FETCHWARP_ARBDELTA_ArbDeltaXX(x) ((uint32_t)(x) << 0U)
636 #define DPU_FETCHWARP_ARBDELTA_ArbDeltaXY(x) ((uint32_t)(x) << 8U)
637 #define DPU_FETCHWARP_ARBDELTA_ArbDeltaYX(x) ((uint32_t)(x) << 16U)
638 #define DPU_FETCHWARP_ARBDELTA_ArbDeltaYY(x) ((uint32_t)(x) << 24U)
639
640 #define DPU_BLITBLEND_NEUTRALBORDER_NeutralBorderLeft(x) (((uint32_t)(x)&0x07U) << 8U)
641 #define DPU_BLITBLEND_NEUTRALBORDER_NeutralBorderRight(x) (((uint32_t)(x)&0x07U) << 12U)
642 #define DPU_BLITBLEND_NEUTRALBORDER_NeutralBorderMode(x) (((uint32_t)(x)&0x01U) << 0U)
643
644 #define DPU_BLITBLEND_CONTROL_Mode_MASK (1UL << 0U)
645
646 #define DPU_TCON_TCON_CTRL_Bypass_MASK (1UL << 3U)
647
648 #define DPU_TCON_SPGPOSON_SPGPSON_X(x) (((uint32_t)(x)&0x7FFFU) << 16U)
649 #define DPU_TCON_SPGPOSON_SPGPSON_Y(x) (((uint32_t)(x)&0xFFFFU) << 0U)
650 #define DPU_TCON_SPGPOSON_SPGPSON_X_MASK (0x7FFFUL << 16U)
651 #define DPU_TCON_SPGPOSON_SPGPSON_Y_MASK (0xFFFFUL << 0U)
652 #define DPU_TCON_SPGPOSOFF_SPGPSOFF_X(x) (((uint32_t)(x)&0x7FFFU) << 16U)
653 #define DPU_TCON_SPGPOSOFF_SPGPSOFF_Y(x) (((uint32_t)(x)&0xFFFFU) << 0U)
654 #define DPU_TCON_SPGPOSOFF_SPGPSOFF_X_MASK (0x7FFFUL << 16U)
655 #define DPU_TCON_SPGPOSOFF_SPGPSOFF_Y_MASK (0xFFFFUL << 0U)
656
657 #define DPU_TCON_SMXSIGS_SMXSIGS_S0(x) (((uint32_t)(x)&0x7U) << 0U)
658 #define DPU_TCON_SMXSIGS_SMXSIGS_S1(x) (((uint32_t)(x)&0x7U) << 3U)
659 #define DPU_TCON_SMXSIGS_SMXSIGS_S2(x) (((uint32_t)(x)&0x7U) << 6U)
660 #define DPU_TCON_SMXSIGS_SMXSIGS_S3(x) (((uint32_t)(x)&0x7U) << 9U)
661 #define DPU_TCON_SMXSIGS_SMXSIGS_S4(x) (((uint32_t)(x)&0x7U) << 12U)
662
663 #define DPU_FRAMEGEN_HTCFG1_Htotal(x) (((uint32_t)(x)&0x3FFFU) << 16U)
664 #define DPU_FRAMEGEN_HTCFG1_Hact(x) (((uint32_t)(x)&0x3FFFU) << 0U)
665 #define DPU_FRAMEGEN_HTCFG2_Hsync(x) (((uint32_t)(x)&0x3FFFU) << 0U)
666 #define DPU_FRAMEGEN_HTCFG2_Hsbp(x) (((uint32_t)(x)&0x3FFFU) << 16U)
667 #define DPU_FRAMEGEN_HTCFG2_HsEn_MASK (1UL << 31U)
668 #define DPU_FRAMEGEN_VTCFG1_Vtotal(x) (((uint32_t)(x)&0x3FFFU) << 16U)
669 #define DPU_FRAMEGEN_VTCFG1_Vact(x) (((uint32_t)(x)&0x3FFFU) << 0U)
670 #define DPU_FRAMEGEN_VTCFG2_Vsync(x) (((uint32_t)(x)&0x3FFFU) << 0U)
671 #define DPU_FRAMEGEN_VTCFG2_Vsbp(x) (((uint32_t)(x)&0x3FFFU) << 16U)
672 #define DPU_FRAMEGEN_VTCFG2_VsEn_MASK (1UL << 31U)
673
674 #define DPU_FRAMEGEN_PKICKCONFIG_PKickRow(x) (((uint32_t)(x)&0x3FFFU) << 16U)
675 #define DPU_FRAMEGEN_PKICKCONFIG_PKickCol(x) (((uint32_t)(x)&0x3FFFU) << 0U)
676 #define DPU_FRAMEGEN_PKICKCONFIG_PKickEn_MASK (1UL << 31U)
677 #define DPU_FRAMEGEN_SKICKCONFIG_SKickRow(x) (((uint32_t)(x)&0x3FFFU) << 16U)
678 #define DPU_FRAMEGEN_SKICKCONFIG_SKickCol(x) (((uint32_t)(x)&0x3FFFU) << 0U)
679 #define DPU_FRAMEGEN_SKICKCONFIG_SKickEn_MASK (1UL << 31U)
680
681 #define DPU_FRAMEGEN_PACFG_Pstartx(x) (((uint32_t)(x)&0x3FFFU) << 0U)
682 #define DPU_FRAMEGEN_PACFG_Pstarty(x) (((uint32_t)(x)&0x3FFFU) << 16U)
683 #define DPU_FRAMEGEN_SACFG_Sstartx(x) (((uint32_t)(x)&0x3FFFU) << 0U)
684 #define DPU_FRAMEGEN_SACFG_Sstarty(x) (((uint32_t)(x)&0x3FFFU) << 16U)
685 #define DPU_FRAMEGEN_FGINCTRL_FgDm(x) ((uint32_t)(x)&0x07U)
686 #define DPU_FRAMEGEN_FGINCTRL_EnSecAlpha_MASK (1UL << 4U)
687 #define DPU_FRAMEGEN_FGINCTRL_EnPrimAlpha_MASK (1UL << 3U)
688
689 #define DPU_FRAMEGEN_FGCCR_CcBlue(x) (((uint32_t)(x)&0x3FFU) << 0U)
690 #define DPU_FRAMEGEN_FGCCR_CcGreen(x) (((uint32_t)(x)&0x3FFU) << 10U)
691 #define DPU_FRAMEGEN_FGCCR_CcRed(x) (((uint32_t)(x)&0x3FFU) << 20U)
692 #define DPU_FRAMEGEN_FGCCR_CcAlpha(x) (((uint32_t)(x)&0x1U) << 30U)
693
694 #define DPU_FRAMEGEN_FGSLR_ShdTokGen_MASK (1UL << 0U)
695 #define DPU_FRAMEGEN_FGENABLE_FgEn_MASK (1UL << 0U)
696
697 #define DPU_SIG_STATICCONTROL_ErrThres_SHIFT 16U
698 #define DPU_SIG_STATICCONTROL_ErrThresReset_SHIFT 24U
699 #define DPU_SIG_STATICCONTROL_ShdEn_MASK (1UL << 0U)
700 #define DPU_SIG_PANICCOLOR_PanicRed_SHIFT 24U
701 #define DPU_SIG_PANICCOLOR_PanicGreen_SHIFT 16U
702 #define DPU_SIG_PANICCOLOR_PanicBlue_SHIFT 8U
703 #define DPU_SIG_PANICCOLOR_PanicAlpha_MASK (1UL << 7U)
704 #define DPU_SIG_CONTINUOUSMODE_EnCont_MASK (1UL << 0U)
705
706 #endif /* DPU_USE_GENERATE_HEADER */
707
708 typedef union _u32_f32
709 {
710 float f32;
711 uint32_t u32;
712 } u32_f32_t;
713
714 /*! @brief LayerBlend unit shadow token generate mode. */
715 enum _dpu_layer_blend_shadow_token_mode
716 {
717 kDPU_LayerBlendShadowTokenPrim, /*!< Generate shadow load token when token received from primary input. */
718 kDPU_LayerBlendShadowTokenSec, /*!< Generate shadow load token when token received from secondary input. */
719 kDPU_LayerBlendShadowTokenBoth /*!< Generate shadow load token when token received from any input. */
720 };
721
722 /*! @brief LayerBlend unit shadow load mode. */
723 enum _dpu_layer_blend_shadow_load_mode
724 {
725 kDPU_LayerBlendShadowLoadPrim, /*!< Load shadows when token received from primary input. */
726 kDPU_LayerBlendShadowLoadSec, /*!< Load shadows when token received from secondary input. */
727 kDPU_LayerBlendShadowLoadBoth /*!< Load shadows when token received from any input. */
728 };
729
730 /*! @brief Fetch unit control input select, selects function for the frame input port. */
731 enum _dpu_fetch_ctrl_input_sel
732 {
733 kDPU_FetchCtrlInputSelInactive = 0x00U, /*!< Not used. */
734 kDPU_FetchCtrlInputSelCompPack = 0x01U, /*!< Used for component packing, e.g. UV or source alpha buffer. */
735 kDPU_FetchCtrlInputSelAlphaMask = 0x02U, /*!< Used for RGB and alpha pre-multiply stage (mask alpha buffer). */
736 kDPU_FetchCtrlInputSelCoordinate = 0x03U, /*!< Used for arbitrary warping. */
737 };
738
739 /*! @brief Fetch unit control input select, selects function for the frame input port. */
740 enum _dpu_fetch_ctrl_raster_mode
741 {
742 kDPU_FetchCtrlRasterNormal = 0x00U,
743 kDPU_FetchCtrlRasterDecode = 0x01U,
744 kDPU_FetchCtrlRasterArbitrary = 0x02U,
745 kDPU_FetchCtrlRasterPerspective = 0x03U,
746 kDPU_FetchCtrlRasterYUV422 = 0x04U,
747 kDPU_FetchCtrlRasterAffine = 0x05U,
748 };
749
750 /*! @brief Fetch unit control filter mode. */
751 enum _dpu_fetch_ctrl_filter_mode
752 {
753 kDPU_FetchCtrlFilterNearest = 0U, /*!< Chooses pixel closest to sample point */
754 kDPU_FetchCtrlFilterBilinear = 1U, /*!< Calculates result from 4 pixels closest to sample point */
755 kDPU_FetchCtrlFilterFir2 = 2U, /*!< FIR mode with 2 programmable pixel positions and coefficients */
756 kDPU_FetchCtrlFilterFir4 = 3U, /*!< FIR mode with 4 programmable pixel positions and coefficients */
757 kDPU_FetchCtrlFilterHorLinear =
758 4U, /*!< Calculates result from 2 pixels closest to the sample point and on the same line */
759 };
760
761 /*! @brief DPU unit dynamic register offset. */
762 typedef struct _dpu_unit_dynamic_reg_offset
763 {
764 dpu_unit_t unit;
765 uint32_t offset;
766 } dpu_unit_dynamic_reg_offset_t;
767
768 /*!
769 * @name Macros for pixel format.
770 *
771 * In DPU, the pixel format are controlled by three parameters,
772 * ColorComponentBits, ColorComponentShift, and PixelPerBits. These macros define
773 * the parameter values for different pixel format, they could be used during
774 * source buffer and Destination buffer configuration.
775 *
776 * The width of color components as stored in memory can be setup individually to
777 * any value between
778 * - 0 and 10 bits for RGB or YUV
779 * - 0 and 8 bits for Alpha and Index
780 * Any bit position within the pixel word can be configured individually for each
781 * component. There are no restrictions regarding sequence or overlaps.
782 *
783 * Example for RGB565 (16 bpp):
784 * @verbatim
785 |--------------- total size --------------------|
786 |15|14|13|12|11|10| 9| 8| 7| 6| 5| 4| 3| 2| 1| 0|
787 |---bluebits---|----greenbits----|---redbits----|
788 |---------- blue shift ----------|
789 |-green shift -|
790 @endverbatim
791 *
792 * The value for components that are setup to null size is taken from constant color.
793 *
794 * If the @p itu is set to 1, then the ITU656 compatibility mode is used, the max value
795 * of 10-bit YUV codes is considered 1020 instead of 1023.
796 * @{
797 */
798 #define DPU_MAKE_COLORCOMPONENTBITS(itu, redbits, greenbits, bluebits, alphabits) \
799 (((itu) << 31U) | ((redbits) << 24U) | ((greenbits) << 16U) | ((bluebits) << 8U) | (alphabits))
800 #define DPU_MAKE_COLORCOMPONENTSHIFT(redshift, greenshift, blueshift, alphashift) \
801 (((redshift) << 24U) | ((greenshift) << 16U) | ((blueshift) << 8U) | (alphashift))
802 /*
803 * @}
804 */
805
806 /*!
807 * @brief DPU pixel format definition.
808 *
809 * This table works together with @ref dpu_pixel_format_t.
810 */
811 static const uint32_t s_dpuColorComponentFormats[][2] = {
812 /* kDPU_PixelFormatGray8 */
813 {
814 DPU_MAKE_COLORCOMPONENTBITS(0, 8, 8, 8, 0),
815 DPU_MAKE_COLORCOMPONENTSHIFT(0, 0, 0, 0),
816 },
817 /* kDPU_PixelFormatRGB565 */
818 {
819 DPU_MAKE_COLORCOMPONENTBITS(0, 5, 6, 5, 0),
820 DPU_MAKE_COLORCOMPONENTSHIFT(11, 5, 0, 0),
821 },
822 /* kDPU_PixelFormatARGB8888 */
823 {
824 DPU_MAKE_COLORCOMPONENTBITS(0, 8, 8, 8, 8),
825 DPU_MAKE_COLORCOMPONENTSHIFT(16, 8, 0, 24),
826 },
827 /* kDPU_PixelFormatRGB888 */
828 {
829 DPU_MAKE_COLORCOMPONENTBITS(0, 8, 8, 8, 0),
830 DPU_MAKE_COLORCOMPONENTSHIFT(16, 8, 0, 0),
831 },
832 /* kDPU_PixelFormatARGB1555 */
833 {
834 DPU_MAKE_COLORCOMPONENTBITS(0, 5, 5, 5, 1),
835 DPU_MAKE_COLORCOMPONENTSHIFT(10, 5, 0, 15),
836 },
837 };
838
839 /*! @brief Map to get the dynamic register in PIXENG for DPU unit. */
840 static const dpu_unit_dynamic_reg_offset_t s_dpuUnitDynamicRegOffsetTable[] = {
841 {
842 .unit = kDPU_Store9,
843 .offset = DPU_STORE9_DYNAMIC_OFFSET,
844 },
845 {
846 .unit = kDPU_FetchWarp9,
847 .offset = DPU_FETCHWARP9_DYNAMIC_OFFSET,
848 },
849 {
850 .unit = kDPU_FetchDecode9,
851 .offset = DPU_FETCHDECODE9_DYNAMIC_OFFSET,
852 },
853 {
854 .unit = kDPU_BlitBlend9,
855 .offset = DPU_BLITBLEND9_DYNAMIC_OFFSET,
856 },
857 {
858 .unit = kDPU_Rop9,
859 .offset = DPU_ROP9_DYNAMIC_OFFSET,
860 },
861 {
862 .unit = kDPU_Hscaler9,
863 .offset = DPU_H_SCALER9_DYNAMIC_OFFSET,
864 },
865 {
866 .unit = kDPU_Vscaler9,
867 .offset = DPU_V_SCALER9_DYNAMIC_OFFSET,
868 },
869 {
870 .unit = kDPU_Hscaler4,
871 .offset = DPU_H_SCALER4_DYNAMIC_OFFSET,
872 },
873 {
874 .unit = kDPU_Vscaler4,
875 .offset = DPU_V_SCALER4_DYNAMIC_OFFSET,
876 },
877 {
878 .unit = kDPU_Hscaler5,
879 .offset = DPU_H_SCALER5_DYNAMIC_OFFSET,
880 },
881 {
882 .unit = kDPU_Vscaler5,
883 .offset = DPU_V_SCALER5_DYNAMIC_OFFSET,
884 },
885 {
886 .unit = kDPU_ExtDst0,
887 .offset = DPU_EXTDST0_DYNAMIC_OFFSET,
888 },
889 {
890 .unit = kDPU_ExtDst4,
891 .offset = DPU_EXTDST4_DYNAMIC_OFFSET,
892 },
893 {
894 .unit = kDPU_ExtDst1,
895 .offset = DPU_EXTDST1_DYNAMIC_OFFSET,
896 },
897 {
898 .unit = kDPU_ExtDst5,
899 .offset = DPU_EXTDST5_DYNAMIC_OFFSET,
900 },
901 {
902 .unit = kDPU_FetchWarp2,
903 .offset = DPU_FETCHWARP2_DYNAMIC_OFFSET,
904 },
905 {
906 .unit = kDPU_FetchDecode0,
907 .offset = DPU_FETCHDECODE0_DYNAMIC_OFFSET,
908 },
909 {
910 .unit = kDPU_FetchDecode1,
911 .offset = DPU_FETCHDECODE1_DYNAMIC_OFFSET,
912 },
913 {
914 .unit = kDPU_LayerBlend0,
915 .offset = DPU_LAYERBLEND0_DYNAMIC_OFFSET,
916 },
917 {
918 .unit = kDPU_LayerBlend1,
919 .offset = DPU_LAYERBLEND1_DYNAMIC_OFFSET,
920 },
921 {
922 .unit = kDPU_LayerBlend2,
923 .offset = DPU_LAYERBLEND2_DYNAMIC_OFFSET,
924 },
925 {
926 .unit = kDPU_LayerBlend3,
927 .offset = DPU_LAYERBLEND3_DYNAMIC_OFFSET,
928 },
929 };
930
931 /*******************************************************************************
932 * Prototypes
933 ******************************************************************************/
934
935 /*!
936 * @brief Get the DPU instance from peripheral base address.
937 *
938 * @param base DPU peripheral base address.
939 * @return DPU instance.
940 */
941 uint32_t DPU_GetInstance(IRIS_MVPL_Type *base);
942
943 /*!
944 * @brief Get the offset of the register <unit>_dynamic.
945 *
946 * Only the unit with attribute @ref kDPU_UnitAttrHasSrc could use this function.
947 *
948 * @param unit See @ref dpu_unit_t.
949 * @return Offset of <unit>_dynamic.
950 */
951 static uint32_t DPU_GetDynamicRegOffset(dpu_unit_t unit);
952
953 /*!
954 * @brief Check whether the buffer is aligned for the pixel format.
955 *
956 * For source buffer and destination buffer, the buffer base address and stride
957 * must be aligned to the bitsPerPixel. For example. if bitsPerPixel is 32, then
958 * the buffer base address and stride should be 32-bit aligned.
959 *
960 * @param bitsPerPixel Bits per pixel of the buffer.
961 * @param baseAddr Base address of the buffer.
962 * @param strideBytes Stide of the buffer.
963 * @retval true Buffer is aligned.
964 * @retval false Buffer is not aligned.
965 */
966 static bool DPU_CheckBufferAlignment(uint8_t bitsPerPixel, uint32_t baseAddr, uint32_t strideBytes);
967
968 /*!
969 * @brief Get the sublayer control registers of fetch unit.
970 *
971 * The sublayer control register are defined by DPU_SUBLAYER_CONTROL_Type.
972 *
973 * @param base DPU peripheral base address.
974 * @param unit See @ref dpu_unit_t.
975 * @return Sublayer control registers.
976 */
977 static DPU_SUBLAYER_CONTROL_Type *DPU_GetSubLayer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer);
978
979 /*!
980 * @brief Convert IEEE 754 float value to the value could be written to registers.
981 *
982 * This function converts the float value to integer value to set the scaler parameters.
983 *
984 * @param floatValue The float value to convert.
985 * @param intBits Bits number of integer part in result.
986 * @param fracBits Bits number of fractional part in result.
987 * @return The value to set to register.
988 */
989 static uint32_t DPU_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits);
990
991 /*******************************************************************************
992 * Variables
993 ******************************************************************************/
994 static const uint32_t s_displayOffsetArray[] = {DPU_FRAME_GEN0_OFFSET, DPU_FRAME_GEN1_OFFSET};
995
996 static IRIS_MVPL_Type *const s_dpuBases[] = IRIS_MVPL_BASE_PTRS;
997
998 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
999 /* Array of DPU clock name. */
1000 static const clock_ip_name_t s_dpuClock[] = DPU_CLOCKS;
1001 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1002
1003 /*******************************************************************************
1004 * Code
1005 ******************************************************************************/
1006
DPU_GetInstance(IRIS_MVPL_Type * base)1007 uint32_t DPU_GetInstance(IRIS_MVPL_Type *base)
1008 {
1009 uint32_t instance;
1010 const uint32_t dpuArrayCount = ARRAY_SIZE(s_dpuBases);
1011
1012 /* Find the instance index from base address mappings. */
1013 for (instance = 0; instance < dpuArrayCount; instance++)
1014 {
1015 if (s_dpuBases[instance] == base)
1016 {
1017 break;
1018 }
1019 }
1020
1021 assert(instance < dpuArrayCount);
1022
1023 return instance;
1024 }
1025
DPU_CheckBufferAlignment(uint8_t bitsPerPixel,uint32_t baseAddr,uint32_t strideBytes)1026 static bool DPU_CheckBufferAlignment(uint8_t bitsPerPixel, uint32_t baseAddr, uint32_t strideBytes)
1027 {
1028 uint32_t mask = 0U;
1029 uint32_t i;
1030 bool ret;
1031
1032 /*
1033 * Frame buffer alignment restrictions:
1034 * 32 bpp: Base address and stride must be a multiple of 4 bytes.
1035 * 16 bpp: Base address and stride must be a multiple of 2 bytes.
1036 * others: any byte alignment allowed
1037 */
1038 static const uint32_t s_dpuBufferAlignMask[][2] = {
1039 {32U, 0x03U},
1040 {16U, 0x01U},
1041 };
1042
1043 /* Find the mask to compare. */
1044 for (i = 0U; i < ARRAY_SIZE(s_dpuBufferAlignMask); i++)
1045 {
1046 if (s_dpuBufferAlignMask[i][0] == bitsPerPixel)
1047 {
1048 mask = s_dpuBufferAlignMask[i][1];
1049 break;
1050 }
1051 }
1052
1053 if (0U != ((baseAddr & mask) | (strideBytes & mask)))
1054 {
1055 ret = false;
1056 }
1057 else
1058 {
1059 ret = true;
1060 }
1061
1062 return ret;
1063 }
1064
DPU_GetDynamicRegOffset(dpu_unit_t unit)1065 static uint32_t DPU_GetDynamicRegOffset(dpu_unit_t unit)
1066 {
1067 uint32_t offset = 0U;
1068 uint32_t i;
1069
1070 for (i = 0; i < ARRAY_SIZE(s_dpuUnitDynamicRegOffsetTable); i++)
1071 {
1072 if (s_dpuUnitDynamicRegOffsetTable[i].unit == unit)
1073 {
1074 offset = s_dpuUnitDynamicRegOffsetTable[i].offset;
1075 break;
1076 }
1077 }
1078
1079 return offset;
1080 }
1081
DPU_GetSubLayer(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer)1082 static DPU_SUBLAYER_CONTROL_Type *DPU_GetSubLayer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer)
1083 {
1084 /* The sublayer register offset in the fetch unit control block. */
1085 uint32_t offset;
1086
1087 /* If the fetch unit does not support sublayer, then configure sublayer 0. */
1088 if (0U == ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrSubLayer)))
1089 {
1090 sublayer = 0;
1091 }
1092
1093 if ((uint32_t)kDPU_FetchDecode == DPU_GET_UNIT_TYPE(unit))
1094 {
1095 offset = DPU_FETCHDECODE_SUBLAYER_CONTROL_OFFSET;
1096 }
1097 else
1098 {
1099 offset = DPU_FETCHLAYER_SUBLAYER_CONTROL_OFFSET;
1100 }
1101
1102 return (DPU_SUBLAYER_CONTROL_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit) + offset +
1103 (uint32_t)sublayer * sizeof(DPU_SUBLAYER_CONTROL_Type));
1104 }
1105
DPU_ConvertFloat(float floatValue,uint8_t intBits,uint8_t fracBits)1106 static uint32_t DPU_ConvertFloat(float floatValue, uint8_t intBits, uint8_t fracBits)
1107 {
1108 /* One bit reserved for sign bit. */
1109 assert(intBits + fracBits < 32U);
1110
1111 u32_f32_t u32_f32;
1112 uint32_t ret;
1113 uint32_t expBits;
1114
1115 u32_f32.f32 = floatValue;
1116 uint32_t floatBits = u32_f32.u32;
1117 expBits = (floatBits & 0x7F800000U) >> 23U;
1118 int32_t expValue = (int32_t)expBits - 127;
1119
1120 ret = (floatBits & 0x007FFFFFU) | 0x00800000U;
1121 expValue += (int32_t)fracBits;
1122
1123 if (expValue < 0)
1124 {
1125 return 0U;
1126 }
1127 else if (expValue > 23)
1128 {
1129 /* should not exceed 31-bit when left shift. */
1130 assert((expValue - 23) <= 7);
1131 ret <<= ((uint32_t)expValue - 23UL);
1132 }
1133 else
1134 {
1135 ret >>= (23UL - (uint32_t)expValue);
1136 }
1137
1138 /* Set the sign bit. */
1139 if (0U != (floatBits & 0x80000000UL))
1140 {
1141 ret = ((~ret) + 1U) & ~(((uint32_t)-1) << (intBits + fracBits + 1U));
1142 }
1143
1144 return ret;
1145 }
1146
1147 /*!
1148 * brief Initializes the DPU peripheral.
1149 *
1150 * This function ungates the DPU clock.
1151 *
1152 * param base DPU peripheral base address.
1153 *
1154 */
DPU_Init(IRIS_MVPL_Type * base)1155 void DPU_Init(IRIS_MVPL_Type *base)
1156 {
1157 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1158 /* Enable dpu clock */
1159 (void)CLOCK_EnableClock(s_dpuClock[DPU_GetInstance(base)]);
1160 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1161 }
1162
1163 /*!
1164 * brief Deinitializes the DPU peripheral.
1165 *
1166 * This function gates the DPU clock.
1167 *
1168 * param base DPU peripheral base address.
1169 */
DPU_Deinit(IRIS_MVPL_Type * base)1170 void DPU_Deinit(IRIS_MVPL_Type *base)
1171 {
1172 uint8_t i;
1173
1174 /* Disable display output. */
1175 for (i = 0U; i < DPU_DISPLAY_COUNT; i++)
1176 {
1177 DPU_StopDisplay(base, i);
1178 }
1179
1180 /* Power down all pipline. */
1181 DPU_DeinitPipeline(base, kDPU_PipelineExtDst0);
1182 DPU_DeinitPipeline(base, kDPU_PipelineExtDst1);
1183 DPU_DeinitPipeline(base, kDPU_PipelineExtDst4);
1184 DPU_DeinitPipeline(base, kDPU_PipelineExtDst5);
1185 DPU_DeinitPipeline(base, kDPU_PipelineStore9);
1186
1187 /* Clear all pending interrupts. */
1188 for (i = 0U; i < DPU_INT_GROUP_NUM; i++)
1189 {
1190 DPU_DisableInterrupts(base, i, 0xFFFFFFFFU);
1191 DPU_DisableUserInterrupts(base, i, 0xFFFFFFFFU);
1192 DPU_ClearInterruptsPendingFlags(base, i, 0xFFFFFFFFU);
1193 DPU_ClearUserInterruptsPendingFlags(base, i, 0xFFFFFFFFU);
1194 }
1195
1196 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
1197 /* Disable dpu clock */
1198 (void)CLOCK_DisableClock(s_dpuClock[DPU_GetInstance(base)]);
1199 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
1200 }
1201
1202 /*!
1203 * brief Prepare the unit path configuration.
1204 *
1205 * The DPU has a default path configuration. Before changing the configuration,
1206 * this function could be used to break all the original path. This make sure
1207 * one pixel engine unit is not used in multiple pipelines.
1208 *
1209 * param base DPU peripheral base address.
1210 */
DPU_PreparePathConfig(IRIS_MVPL_Type * base)1211 void DPU_PreparePathConfig(IRIS_MVPL_Type *base)
1212 {
1213 const dpu_unit_t dpuPipeLines[] = {
1214 kDPU_PipelineStore9, kDPU_PipelineExtDst0, kDPU_PipelineExtDst1, kDPU_PipelineExtDst4, kDPU_PipelineExtDst5,
1215 };
1216
1217 /* Disable shadow for all pipelines. */
1218 for (uint32_t i = 0; i < ARRAY_SIZE(dpuPipeLines); i++)
1219 {
1220 (void)DPU_EnableShadowLoad(base, dpuPipeLines[i], false);
1221 }
1222
1223 /* Set all pixel engine unit source to NULL. */
1224 const dpu_unit_t dpuUnits[] = {
1225 kDPU_FetchWarp9, kDPU_FetchDecode9, kDPU_Hscaler9, kDPU_Vscaler9, kDPU_Rop9, kDPU_BlitBlend9,
1226 kDPU_Store9, kDPU_ExtDst0, kDPU_ExtDst4, kDPU_ExtDst1, kDPU_ExtDst5, kDPU_FetchWarp2,
1227 kDPU_FetchDecode0, kDPU_FetchDecode1, kDPU_Hscaler4, kDPU_Vscaler4, kDPU_Hscaler5, kDPU_Vscaler5,
1228 kDPU_LayerBlend0, kDPU_LayerBlend1, kDPU_LayerBlend2, kDPU_LayerBlend3,
1229 };
1230
1231 for (uint32_t i = 0; i < ARRAY_SIZE(dpuUnits); i++)
1232 {
1233 DPU_SetUnitSrc(base, dpuUnits[i], 0U);
1234 }
1235 }
1236
1237 /*!
1238 * brief Enable the selected DPU interrupts.
1239 *
1240 * For example, to enable Store9 shadow load interrupt and Store9 frame complete
1241 * interrupt, use like this:
1242 *
1243 * code
1244 DPU_EnableInterrupts(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt |
1245 kDPU_Group0Store9FrameCompleteInterrupt);
1246 endcode
1247 *
1248 * param base DPU peripheral base address.
1249 * param group Interrupt group index.
1250 * param mask The interrupts to enable, this is a logical OR of members in
1251 * ref _dpu_interrupt.
1252 * note Only the members in the same group could be OR'ed, at the same time,
1253 * the parameter p group should be passed in correctly.
1254 */
DPU_EnableInterrupts(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1255 void DPU_EnableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1256 {
1257 assert(group < DPU_INT_GROUP_NUM);
1258
1259 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTENABLE[group] |= mask;
1260 }
1261
1262 /*!
1263 * brief Disable the selected DPU interrupts.
1264 *
1265 * For example, to disable Store9 shadow load interrupt and Store9 frame complete
1266 * interrupt, use like this:
1267 *
1268 * code
1269 DPU_DisableInterrupts(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt |
1270 kDPU_Group0Store9FrameCompleteInterrupt);
1271 endcode
1272 *
1273 * param base DPU peripheral base address.
1274 * param group Interrupt group index.
1275 * param mask The interrupts to disable, this is a logical OR of members in
1276 * ref _dpu_interrupt.
1277 * note Only the members in the same group could be OR'ed, at the same time,
1278 * the parameter p group should be passed in correctly.
1279 */
DPU_DisableInterrupts(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1280 void DPU_DisableInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1281 {
1282 assert(group < DPU_INT_GROUP_NUM);
1283
1284 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTENABLE[group] &= ~mask;
1285 }
1286
1287 /*!
1288 * brief Get the DPU interrupts pending status.
1289 *
1290 * The pending status are returned as mask.
1291 *
1292 * param base DPU peripheral base address.
1293 * param group Interrupt group index.
1294 * return The interrupts pending status mask value, see ref _dpu_interrupt.
1295 */
DPU_GetInterruptsPendingFlags(IRIS_MVPL_Type * base,uint8_t group)1296 uint32_t DPU_GetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group)
1297 {
1298 assert(group < DPU_INT_GROUP_NUM);
1299
1300 return ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTSTATUS[group];
1301 }
1302
1303 /*!
1304 * brief Clear the specified DPU interrupts pending status.
1305 *
1306 * For example, to disable Store9 shadow load interrupt and Store9 frame complete
1307 * interrupt pending status, use like this:
1308 *
1309 * code
1310 DPU_ClearInterruptsPendingFlags(DPU, 0, kDPU_Group0Store9ShadowLoadInterrupt |
1311 kDPU_Group0Store9FrameCompleteInterrupt);
1312 endcode
1313 *
1314 * param base DPU peripheral base address.
1315 * param group Interrupt group index.
1316 * param mask The interrupt pending flags to clear, this is a logical OR of members in
1317 * ref _dpu_interrupt.
1318 * note Only the members in the same group could be OR'ed, at the same time,
1319 * the parameter p group should be passed in correctly.
1320 */
DPU_ClearInterruptsPendingFlags(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1321 void DPU_ClearInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1322 {
1323 assert(group < DPU_INT_GROUP_NUM);
1324
1325 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTCLEAR[group] = mask;
1326 }
1327
1328 /*!
1329 * brief Set the specified DPU interrupts pending status.
1330 *
1331 * This function sets the interrupts pending flags, this is a method to trigger
1332 * interrupts by software.
1333 *
1334 * param base DPU peripheral base address.
1335 * param group Interrupt group index.
1336 * param mask The interrupt pending flags to set, this is a logical OR of members in
1337 * ref _dpu_interrupt.
1338 * note Only the members in the same group could be OR'ed, at the same time,
1339 * the parameter p group should be passed in correctly.
1340 */
DPU_SetInterruptsPendingFlags(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1341 void DPU_SetInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1342 {
1343 assert(group < DPU_INT_GROUP_NUM);
1344
1345 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->INTERRUPTPRESET[group] = mask;
1346 }
1347
1348 /*!
1349 * brief Mask the selected DPU user interrupts.
1350 *
1351 * The only difference between DPU user interrupt and normal interrupt is user
1352 * interrupts could be masked by @ref DPU_MaskUserInterrupts. All other APIs
1353 * useage are the same.
1354 *
1355 * param base DPU peripheral base address.
1356 * param group Interrupt group index.
1357 * param mask The interrupts to mask, this is a logical OR of members in
1358 * _dpu_interrupt.
1359 */
DPU_MaskUserInterrupts(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1360 void DPU_MaskUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1361 {
1362 assert(group < DPU_INT_GROUP_NUM);
1363
1364 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->USERINTERRUPTMASK[group] = mask;
1365 }
1366
1367 /*!
1368 * brief Enable the selected DPU user interrupts.
1369 *
1370 * The only difference between DPU user interrupt and normal interrupt is user
1371 * interrupts could be masked by ref DPU_MaskUserInterrupts.
1372 *
1373 * param base DPU peripheral base address.
1374 * param group Interrupt group index.
1375 * param mask The interrupts to enable, this is a logical OR of members in
1376 * ref _dpu_interrupt.
1377 */
DPU_EnableUserInterrupts(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1378 void DPU_EnableUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1379 {
1380 assert(group < DPU_INT_GROUP_NUM);
1381
1382 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->USERINTERRUPTENABLE[group] |= mask;
1383 }
1384
1385 /*!
1386 * brief Disable the selected DPU user interrupts.
1387 *
1388 * The only difference between DPU user interrupt and normal interrupt is user
1389 * interrupts could be masked by ref DPU_MaskUserInterrupts.
1390 *
1391 * param base DPU peripheral base address.
1392 * param group Interrupt group index.
1393 * param mask The interrupts to disable, this is a logical OR of members in
1394 * ref _dpu_interrupt.
1395 */
DPU_DisableUserInterrupts(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1396 void DPU_DisableUserInterrupts(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1397 {
1398 assert(group < DPU_INT_GROUP_NUM);
1399
1400 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->USERINTERRUPTENABLE[group] &= ~mask;
1401 }
1402
1403 /*!
1404 * brief Get the DPU user interrupts pending status.
1405 *
1406 * The only difference between DPU user interrupt and normal interrupt is user
1407 * interrupts could be masked by ref DPU_MaskUserInterrupts.
1408 *
1409 * param base DPU peripheral base address.
1410 * param group Interrupt group index.
1411 * return The interrupts pending status mask value, see ref _dpu_interrupt.
1412 */
DPU_GetUserInterruptsPendingFlags(IRIS_MVPL_Type * base,uint8_t group)1413 uint32_t DPU_GetUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group)
1414 {
1415 assert(group < DPU_INT_GROUP_NUM);
1416
1417 return ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->USERINTERRUPTSTATUS[group];
1418 }
1419
1420 /*!
1421 * brief Clear the specified DPU user interrupts pending status.
1422 *
1423 * The only difference between DPU user interrupt and normal interrupt is user
1424 * interrupts could be masked by ref DPU_MaskUserInterrupts.
1425 *
1426 * param base DPU peripheral base address.
1427 * param group Interrupt group index.
1428 * param mask The interrupt pending flags to clear, this is a logical OR of members in
1429 * ref _dpu_interrupt.
1430 */
DPU_ClearUserInterruptsPendingFlags(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1431 void DPU_ClearUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1432 {
1433 assert(group < DPU_INT_GROUP_NUM);
1434
1435 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->USERINTERRUPTCLEAR[group] = mask;
1436 }
1437
1438 /*!
1439 * brief Set the specified DPU user interrupts pending status.
1440 *
1441 * The only difference between DPU user interrupt and normal interrupt is user
1442 * interrupts could be masked by ref DPU_MaskUserInterrupts.
1443 *
1444 * param base DPU peripheral base address.
1445 * param group Interrupt group index.
1446 * param mask The interrupt pending flags to set, this is a logical OR of members in
1447 * ref _dpu_interrupt.
1448 */
DPU_SetUserInterruptsPendingFlags(IRIS_MVPL_Type * base,uint8_t group,uint32_t mask)1449 void DPU_SetUserInterruptsPendingFlags(IRIS_MVPL_Type *base, uint8_t group, uint32_t mask)
1450 {
1451 assert(group < DPU_INT_GROUP_NUM);
1452
1453 ((DPU_COMCTRL_Type *)((uint32_t)base + DPU_COMCTRL_OFFSET))->USERINTERRUPTPRESET[group] = mask;
1454 }
1455
1456 /*!
1457 * brief Enable or disable the register shadowing for the DPU process units.
1458 *
1459 * For example, to enable the shadowing of all RWS registers of the pipeline with endpoint Store9.
1460 * code
1461 DPU_EnableShadowLoad(DPU, kDPU_PipelineStore9, true);
1462 endcode
1463 *
1464 * param base DPU peripheral base address.
1465 * param unit The unit whose shadow load to enable or disable, see ref dpu_unit_t.
1466 * param enable True to enable, false to disable.
1467 * retval kStatus_Success The shadow load is enabled or disabled successfully.
1468 * retval kStatus_InvalidArgument The unit does not support shadow load.
1469 */
DPU_EnableShadowLoad(IRIS_MVPL_Type * base,dpu_unit_t unit,bool enable)1470 status_t DPU_EnableShadowLoad(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
1471 {
1472 /* Offset of the static control register to enable/disable shadow load. */
1473 uint32_t staticRegOffset;
1474 status_t status;
1475
1476 if (0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrNoShdow)))
1477 {
1478 status = kStatus_InvalidArgument;
1479 }
1480 else
1481 {
1482 staticRegOffset = DPU_GET_UNIT_OFFSET(unit) + DPU_STATIC_CONTROL_OFFSET;
1483
1484 if (enable)
1485 {
1486 DPU_REG(base, staticRegOffset) |= DPU_UNIT_SHDEN_MASK;
1487 }
1488 else
1489 {
1490 DPU_REG(base, staticRegOffset) &= ~DPU_UNIT_SHDEN_MASK;
1491 }
1492
1493 status = kStatus_Success;
1494 }
1495
1496 return status;
1497 }
1498
1499 /*!
1500 * brief Initialize the pipeline.
1501 *
1502 * param base DPU peripheral base address.
1503 * param unit The DPU pipeline unit.
1504 */
DPU_InitPipeline(IRIS_MVPL_Type * base,dpu_unit_t unit)1505 void DPU_InitPipeline(IRIS_MVPL_Type *base, dpu_unit_t unit)
1506 {
1507 assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));
1508
1509 DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
1510
1511 /* Set pipeline sync mode to single mode, power up, and enable shadow load. */
1512 pipeline->STATIC = DPU_PIPELINE_STATIC_DIV(0x80) | DPU_UNIT_SHDEN_MASK;
1513 }
1514
1515 /*!
1516 * brief Deinitializes the pipeline.
1517 *
1518 * Power down the pipeline and disable the shadow load feature.
1519 *
1520 * param base DPU peripheral base address.
1521 * param unit The DPU pipeline unit.
1522 */
DPU_DeinitPipeline(IRIS_MVPL_Type * base,dpu_unit_t unit)1523 void DPU_DeinitPipeline(IRIS_MVPL_Type *base, dpu_unit_t unit)
1524 {
1525 assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));
1526
1527 DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
1528
1529 /* Disable shadow load and powerdown the pipeline. */
1530 pipeline->STATIC = DPU_PIPELINE_STATIC_POWERDOWN_MASK;
1531 }
1532
1533 /*!
1534 * brief Trigger the pipeline shadow load.
1535 *
1536 * This function triggers the pipeline reconfiguration.
1537 *
1538 * param base DPU peripheral base address.
1539 * param unit The DPU pipeline unit.
1540 */
DPU_TriggerPipelineShadowLoad(IRIS_MVPL_Type * base,dpu_unit_t unit)1541 void DPU_TriggerPipelineShadowLoad(IRIS_MVPL_Type *base, dpu_unit_t unit)
1542 {
1543 assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));
1544
1545 DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
1546
1547 pipeline->TRIGGER = DPU_PIPELINE_TRIGGER_SYNC_TRIGGER_MASK;
1548 }
1549
1550 /*!
1551 * brief Trigger the pipeline.
1552 *
1553 * This function triggers the pipeline sequence complete interrupt. After
1554 * triggered, this interrupt occurs when the pipeline is empty and no more
1555 * operations are pending. It will occur immediately, when this is the case
1556 * already during activation of the trigger. Generally this is used for the
1557 * blit operation, to make sure all operations finished.
1558 *
1559 * param base DPU peripheral base address.
1560 * param unit The DPU pipeline unit.
1561 */
DPU_TriggerPipelineCompleteInterrupt(IRIS_MVPL_Type * base,dpu_unit_t unit)1562 void DPU_TriggerPipelineCompleteInterrupt(IRIS_MVPL_Type *base, dpu_unit_t unit)
1563 {
1564 assert((uint32_t)kDPU_Pipeline == DPU_GET_UNIT_TYPE(unit));
1565
1566 DPU_PIPELINE_Type *pipeline = (DPU_PIPELINE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
1567
1568 pipeline->TRIGGER = DPU_PIPELINE_TRIGGER_SEQ_COMP_MASK;
1569 }
1570
1571 /*!
1572 * brief Set the DPU unit input source selection.
1573 *
1574 * Sets the DPU unit input source, the input source is controlled by the
1575 * register \<unit\>_dynamic in "Pixel Engin Top Level". This function writes
1576 * the register \<unit\>_dynamic directly, please check the reference manual
1577 * for the register details. This function only changes the input source
1578 * control bits in register.
1579 *
1580 * param base DPU peripheral base address.
1581 * param unit The DPU pipeline unit.
1582 * param srcReg The value written to register \<unit\>_dynamic. Could be
1583 * generated using ref DPU_MAKE_SRC_REG1, ref DPU_MAKE_SRC_REG2,
1584 * and ref DPU_MAKE_SRC_REG3.
1585 */
DPU_SetUnitSrc(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t srcReg)1586 void DPU_SetUnitSrc(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
1587 {
1588 assert(0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrHasSrc)));
1589
1590 uint32_t reg;
1591 uint32_t offset = DPU_GetDynamicRegOffset(unit);
1592
1593 reg = DPU_REG(base, offset) & DPU_DYNAMIC_CLKEN_MASK;
1594 DPU_REG(base, offset) = reg | (srcReg & ~DPU_DYNAMIC_CLKEN_MASK);
1595 }
1596
1597 /*!
1598 * brief Set the color palette index width for fetch unit.
1599 *
1600 * The palette index width could be 1 to 8. Note the difference between palette
1601 * index width and the pixel width in framebuffer.
1602 *
1603 * param base DPU peripheral base address.
1604 * param unit DPU unit, see ref dpu_unit_t, must be FetchDecode or FetchLayer here.
1605 * param indexWidth The palette index width.
1606 * retval kStatus_Success Initialization success.
1607 * retval kStatus_InvalidArgument Wrong argument.
1608 */
DPU_SetColorPaletteIndexWidth(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t indexWidth)1609 status_t DPU_SetColorPaletteIndexWidth(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t indexWidth)
1610 {
1611 uint32_t offset;
1612 uint32_t reg;
1613 uint32_t type = DPU_GET_UNIT_TYPE(unit);
1614
1615 if (((uint32_t)kDPU_FetchLayer != type) && ((uint32_t)kDPU_FetchDecode != type))
1616 {
1617 return kStatus_InvalidArgument;
1618 }
1619
1620 offset = ((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit);
1621
1622 /* Set index width. */
1623 if (type == (uint32_t)kDPU_FetchLayer)
1624 {
1625 reg = ((DPU_FETCHLAYER_Type *)offset)->CONTROL;
1626 reg = (reg & ~DPU_FETCH_CONTROL_PALETTEIDXWIDTH_MASK) | DPU_FETCH_CONTROL_PALETTEIDXWIDTH(indexWidth - 1UL);
1627 ((DPU_FETCHLAYER_Type *)offset)->CONTROL = reg;
1628 }
1629 else
1630 {
1631 reg = ((DPU_FETCHDECODER_Type *)offset)->CONTROL;
1632 reg = (reg & ~DPU_FETCH_CONTROL_PALETTEIDXWIDTH_MASK) | DPU_FETCH_CONTROL_PALETTEIDXWIDTH(indexWidth - 1UL);
1633 ((DPU_FETCHDECODER_Type *)offset)->CONTROL = reg;
1634 }
1635
1636 return kStatus_Success;
1637 }
1638
1639 /*!
1640 * brief Updates the color palette for fetch unit.
1641 *
1642 * This function updates the fetch unit color palette, the palette values specified
1643 * by p palette are loaded to fetch unit from p startIndex. The load count is
1644 * specified by p count.
1645 *
1646 * param base DPU peripheral base address.
1647 * param unit DPU unit, see ref dpu_unit_t, must be FetchDecode or FetchLayer here.
1648 * param startIndex The start index of the fetch unit palette to update.
1649 * param palette Pointer to the palette.
1650 * param count Count of p palette.
1651 * retval kStatus_Success Initialization success.
1652 * retval kStatus_InvalidArgument Wrong argument.
1653 */
DPU_UpdateColorPalette(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t startIndex,const uint32_t * palette,uint32_t count)1654 status_t DPU_UpdateColorPalette(
1655 IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t startIndex, const uint32_t *palette, uint32_t count)
1656 {
1657 assert(NULL != palette);
1658 assert(((uint32_t)kDPU_FetchLayer == DPU_GET_UNIT_TYPE(unit)) ||
1659 ((uint32_t)kDPU_FetchDecode == DPU_GET_UNIT_TYPE(unit)));
1660
1661 uint32_t offset;
1662 uint32_t i;
1663
1664 /* Exceed the palette boundary. */
1665 if (startIndex + count > DPU_PALETTE_ENTRY_NUM)
1666 {
1667 return kStatus_InvalidArgument;
1668 }
1669
1670 offset = ((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit);
1671
1672 /* Set palette entery. */
1673 for (i = 0; i < count; i++)
1674 {
1675 ((volatile uint32_t *)(offset + DPU_PALETTE_OFFSET))[i + startIndex] = palette[i];
1676 }
1677
1678 return kStatus_Success;
1679 }
1680
1681 /*!
1682 * brief Enable or disable color palette for some sublayer.
1683 *
1684 * param base DPU peripheral base address.
1685 * param unit DPU unit, see ref dpu_unit_t, must be FetchDecode or FetchLayer here.
1686 * param sublayer Sublayer index, should be 0 to 7.
1687 * param enable True to enable, false to disable.
1688 */
DPU_EnableColorPalette(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,bool enable)1689 void DPU_EnableColorPalette(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)
1690 {
1691 assert(((uint32_t)kDPU_FetchLayer == DPU_GET_UNIT_TYPE(unit)) ||
1692 ((uint32_t)kDPU_FetchDecode == DPU_GET_UNIT_TYPE(unit)));
1693
1694 DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);
1695
1696 if (enable)
1697 {
1698 control->LAYERPROPERTY |= DPU_LAYERPROPERTY_PALETTEENABLE_MASK;
1699 }
1700 else
1701 {
1702 control->LAYERPROPERTY &= ~DPU_LAYERPROPERTY_PALETTEENABLE_MASK;
1703 }
1704 }
1705
1706 /*!
1707 * brief Get the default configuration for fetch unit.
1708 *
1709 * The default value is:
1710 * code
1711 config->srcReg = 0U;
1712 config->frameHeight = 320U;
1713 config->frameWidth = 480U;
1714 endcode
1715 *
1716 * param config Pointer to the configuration structure.
1717 */
DPU_FetchUnitGetDefaultConfig(dpu_fetch_unit_config_t * config)1718 void DPU_FetchUnitGetDefaultConfig(dpu_fetch_unit_config_t *config)
1719 {
1720 assert(NULL != config);
1721
1722 /* Initializes the configure structure to zero. */
1723 (void)memset(config, 0, sizeof(*config));
1724
1725 config->srcReg = 0U;
1726 config->frameHeight = 320U;
1727 config->frameWidth = 480U;
1728 }
1729
1730 /*!
1731 * brief Initialize the fetch unit.
1732 *
1733 * This function initializes the fetch unit for the basic use, for other use
1734 * case such as arbitrary warping, use the functions ref DPU_InitFetchUnitWarp
1735 * and ref DPU_InitWarpCoordinates.
1736 *
1737 * The input source of fetch unit could be:
1738 * - ref kDPU_UnitSrcNone
1739 * - ref kDPU_UnitSrcFetchWarp9
1740 * - ref kDPU_UnitSrcFetchEco2
1741 * - ref kDPU_UnitSrcFetchEco9
1742 * - ref kDPU_UnitSrcFetchEco0
1743 * - ref kDPU_UnitSrcFetchEco1
1744 *
1745 * param base DPU peripheral base address.
1746 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
1747 * param config Pointer to the configuration structure.
1748 */
DPU_InitFetchUnit(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_fetch_unit_config_t * config)1749 void DPU_InitFetchUnit(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_fetch_unit_config_t *config)
1750 {
1751 assert(NULL != config);
1752 assert(0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrIsFetch)));
1753
1754 uint32_t reg;
1755 uint32_t offset;
1756 uint32_t type;
1757 uint32_t dimensionOffset;
1758 uint32_t controlOffset;
1759 uint32_t resamplingOffset;
1760
1761 offset = DPU_GET_UNIT_OFFSET(unit);
1762 type = DPU_GET_UNIT_TYPE(unit);
1763
1764 switch (type)
1765 {
1766 case kDPU_FetchDecode:
1767 dimensionOffset = DPU_FETCHDECODE_FRAMEDIMENSIONS_OFFSET;
1768 controlOffset = DPU_FETCHDECODE_CONTROL_OFFSET;
1769 resamplingOffset = DPU_FETCHDECODE_FRAMERESAMPLING_OFFSET;
1770 break;
1771
1772 case kDPU_FetchEco:
1773 dimensionOffset = DPU_FETCHECO_FRAMEDIMENSIONS_OFFSET;
1774 controlOffset = DPU_FETCHECO_CONTROL_OFFSET;
1775 resamplingOffset = DPU_FETCHECO_FRAMERESAMPLING_OFFSET;
1776 break;
1777
1778 case kDPU_FetchWarp:
1779 dimensionOffset = DPU_FETCHWARP_FRAMEDIMENSIONS_OFFSET;
1780 controlOffset = DPU_FETCHWARP_CONTROL_OFFSET;
1781 resamplingOffset = DPU_FETCHWARP_FRAMERESAMPLING_OFFSET;
1782 break;
1783
1784 default:
1785 dimensionOffset = DPU_FETCHLAYER_FRAMEDIMENSIONS_OFFSET;
1786 controlOffset = DPU_FETCHLAYER_CONTROL_OFFSET;
1787 resamplingOffset = DPU_FETCHLAYER_FRAMERESAMPLING_OFFSET;
1788 break;
1789 }
1790
1791 /*
1792 * Set <unit>_StaticControl
1793 * If the fetch unit supports sublayer, set the ShdLdReqSticky.
1794 */
1795 if (0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrSubLayer)))
1796 {
1797 DPU_REG(base, offset + DPU_STATIC_CONTROL_OFFSET) =
1798 DPU_UNIT_SHDEN_MASK | DPU_FETCH_STATICCONTROL_SHDLDREQSTICKY_MASK;
1799 }
1800 else
1801 {
1802 DPU_REG(base, offset + DPU_STATIC_CONTROL_OFFSET) = DPU_UNIT_SHDEN_MASK;
1803 }
1804
1805 /* Set input source. */
1806 if (0U != ((uint32_t)unit & DPU_MAKE_UNIT_ATTR(kDPU_UnitAttrHasSrc)))
1807 {
1808 DPU_SetUnitSrc(base, unit, config->srcReg);
1809 }
1810
1811 if ((uint32_t)kDPU_FetchDecode == type)
1812 {
1813 /* Disable ring buffer. */
1814 ((DPU_FETCHDECODER_Type *)((uint32_t)base + offset))->RINGBUFSTARTADDR0 = 0U;
1815 ((DPU_FETCHDECODER_Type *)((uint32_t)base + offset))->RINGBUFWRAPADDR0 = 0U;
1816 }
1817
1818 /* AXI burst management. */
1819 DPU_REG(base, offset + DPU_FETCHUNIT_BURSTBUFFERMANAGEMENT_OFFSET) =
1820 DPU_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS(16) |
1821 DPU_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH(DPU_FETCH_UNIT_BURST_LENGTH);
1822
1823 /* Set <unit>_FrameDimensions. */
1824 DPU_REG(base, offset + dimensionOffset) = DPU_MAKE_DIMENSION(config->frameHeight - 1UL, config->frameWidth - 1UL);
1825
1826 /* Set <unit>_Control. */
1827 reg = DPU_REG(base, offset + controlOffset) &
1828 ~(DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE_MASK | DPU_FETCH_CONTROL_RASTERMODE_MASK |
1829 DPU_FETCH_CONTROL_INPUTSELECT_MASK | DPU_FETCH_CONTROL_RAWPIXEL_MASK);
1830
1831 reg |= DPU_FETCH_CONTROL_INPUTSELECT(kDPU_FetchCtrlInputSelInactive) |
1832 DPU_FETCH_CONTROL_RASTERMODE(kDPU_FetchCtrlRasterNormal);
1833
1834 DPU_REG(base, offset + controlOffset) = reg;
1835
1836 /* Set resampling. */
1837 DPU_REG(base, offset + resamplingOffset) = DPU_MAKE_FETCH_RESAMPLING(0, 4, 4, 0, 0);
1838 }
1839
1840 /*!
1841 * brief Get the default warp configuration for FetchWarp unit.
1842 *
1843 * The default value is:
1844 * code
1845 config->srcReg = 0U;
1846 config->frameHeight = 320U;
1847 config->frameWidth = 480U;
1848 config->warpBitsPerPixel = 0U;
1849 config->enableSymmetricOffset = false;
1850 config->coordMode = kDPU_WarpCoordinateModePNT;
1851 config->arbStartX = 0U;
1852 config->arbStartY = 0U;
1853 config->arbDeltaYY = 0U;
1854 config->arbDeltaYX = 0U;
1855 config->arbDeltaXY = 0U;
1856 config->arbDeltaXX = 0U;
1857 endcode
1858 *
1859 * param config Pointer to the configuration structure.
1860 */
DPU_FetcUnitGetDefaultWarpConfig(dpu_warp_config_t * config)1861 void DPU_FetcUnitGetDefaultWarpConfig(dpu_warp_config_t *config)
1862 {
1863 assert(NULL != config);
1864
1865 /* Initializes the configure structure to zero. */
1866 (void)memset(config, 0, sizeof(*config));
1867
1868 config->srcReg = 0U;
1869 config->frameHeight = 320U;
1870 config->frameWidth = 480U;
1871 config->warpBitsPerPixel = 0U;
1872 config->enableSymmetricOffset = false;
1873 config->coordMode = kDPU_WarpCoordinateModePNT;
1874 config->arbStartX = 0U;
1875 config->arbStartY = 0U;
1876 config->arbDeltaYY = 0U;
1877 config->arbDeltaYX = 0U;
1878 config->arbDeltaXY = 0U;
1879 config->arbDeltaXX = 0U;
1880 }
1881
1882 /*!
1883 * brief Initialize the Warp function for FetchWarp unit.
1884 *
1885 * This function initializes the FetchWarp unit for the arbitrary warping.
1886 *
1887 * The valid source of fetch warp unit could be:
1888 * - ref kDPU_UnitSrcNone
1889 * - ref kDPU_UnitSrcFetchEco2
1890 * - ref kDPU_UnitSrcFetchEco9
1891 *
1892 * param base DPU peripheral base address.
1893 * param unit DPU unit, see ref dpu_unit_t, must be FetchWarp unit here.
1894 * param config Pointer to the configuration structure.
1895 * retval kStatus_Success Initialization success.
1896 * retval kStatus_InvalidArgument Wrong argument.
1897 */
DPU_InitFetchUnitWarp(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_warp_config_t * config)1898 status_t DPU_InitFetchUnitWarp(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_warp_config_t *config)
1899 {
1900 assert(NULL != config);
1901
1902 uint32_t reg;
1903 DPU_FETCHWARP_Type *fetchWarp;
1904
1905 if ((uint32_t)kDPU_FetchWarp != DPU_GET_UNIT_TYPE(unit))
1906 {
1907 return kStatus_InvalidArgument;
1908 }
1909
1910 fetchWarp = (DPU_FETCHWARP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
1911
1912 /*
1913 * Set <unit>_StaticControl
1914 * If the fetch unit supports sublayer, set the ShdLdReqSticky.
1915 */
1916 fetchWarp->STATICCONTROL = DPU_UNIT_SHDEN_MASK | DPU_FETCH_STATICCONTROL_SHDLDREQSTICKY_MASK;
1917
1918 /* Set input source. */
1919 DPU_SetUnitSrc(base, unit, config->srcReg);
1920
1921 /* Set <unit>_FrameDimensions. */
1922 fetchWarp->FRAMEDIMENSIONS = DPU_MAKE_DIMENSION(config->frameHeight - 1UL, config->frameWidth - 1UL);
1923
1924 /* Set resampling. */
1925 fetchWarp->FRAMERESAMPLING = DPU_MAKE_FETCH_RESAMPLING(0, 4, 4, 0, 0);
1926
1927 /* Setup warping. */
1928 fetchWarp->WARPCONTROL = DPU_FETCHWARP_WARPCONTROL_WarpBitsPerPixel(config->warpBitsPerPixel) |
1929 DPU_FETCHWARP_WARPCONTROL_WarpCoordinateMode(config->coordMode) |
1930 DPU_FETCHWARP_WARPCONTROL_WarpSymmetricOffset(config->enableSymmetricOffset);
1931
1932 fetchWarp->ARBSTARTX = config->arbStartX;
1933 fetchWarp->ARBSTARTY = config->arbStartY;
1934 fetchWarp->ARBDELTA =
1935 DPU_FETCHWARP_ARBDELTA_ArbDeltaXX(config->arbDeltaXX) | DPU_FETCHWARP_ARBDELTA_ArbDeltaXY(config->arbDeltaXY) |
1936 DPU_FETCHWARP_ARBDELTA_ArbDeltaYX(config->arbDeltaYX) | DPU_FETCHWARP_ARBDELTA_ArbDeltaYY(config->arbDeltaYY);
1937
1938 fetchWarp->BURSTBUFFERMANAGEMENT = DPU_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS(16) |
1939 DPU_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH(DPU_FETCH_UNIT_BURST_LENGTH);
1940
1941 /* Set <unit>_Control. */
1942 reg = fetchWarp->CONTROL & ~(DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE_MASK | DPU_FETCH_CONTROL_RASTERMODE_MASK |
1943 DPU_FETCH_CONTROL_INPUTSELECT_MASK | DPU_FETCH_CONTROL_RAWPIXEL_MASK);
1944 fetchWarp->CONTROL = reg | DPU_FETCH_CONTROL_INPUTSELECT(kDPU_FetchCtrlInputSelCoordinate) |
1945 DPU_FETCH_CONTROL_RASTERMODE(kDPU_FetchCtrlRasterArbitrary) |
1946 DPU_FETCH_CONTROL_FILTERMODE(kDPU_FetchCtrlFilterBilinear);
1947
1948 return kStatus_Success;
1949 }
1950
1951 /*!
1952 * brief Get the default configuration structure for arbitrary warping re-sampling coordinates.
1953 *
1954 * The default value is:
1955 * code
1956 config->bitsPerPixel = 0U;
1957 config->strideBytes = 0x500U;
1958 config->baseAddr = 0U;
1959 config->frameHeight = 320U;
1960 config->frameWidth = 480U;
1961 endcode
1962 *
1963 * param config Pointer to the configuration structure.
1964 */
DPU_CorrdinatesGetDefaultConfig(dpu_coordinates_config_t * config)1965 void DPU_CorrdinatesGetDefaultConfig(dpu_coordinates_config_t *config)
1966 {
1967 assert(NULL != config);
1968
1969 /* Initializes the configure structure to zero. */
1970 (void)memset(config, 0, sizeof(*config));
1971
1972 config->bitsPerPixel = 0U;
1973 config->strideBytes = 0x500U;
1974 config->baseAddr = 0U;
1975 config->frameHeight = 320U;
1976 config->frameWidth = 480U;
1977 }
1978
1979 /*!
1980 * brief Initialize the arbitrary warping coordinates.
1981 *
1982 * This function initializes the FetchEco unit, so that it could
1983 * be used as the arbitrary warping coordinates.
1984 *
1985 * param base DPU peripheral base address.
1986 * param unit DPU unit, see ref dpu_unit_t, must be FetchEco here.
1987 * param config Pointer to the configuration structure.
1988 * retval kStatus_Success Initialization success.
1989 * retval kStatus_InvalidArgument Wrong argument.
1990 */
DPU_InitWarpCoordinates(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_coordinates_config_t * config)1991 status_t DPU_InitWarpCoordinates(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_coordinates_config_t *config)
1992 {
1993 assert(NULL != config);
1994
1995 DPU_FETCHECO_Type *fetchEco;
1996 uint32_t dimension;
1997 uint32_t reg;
1998
1999 if (!DPU_CheckBufferAlignment(config->bitsPerPixel, config->baseAddr, config->strideBytes))
2000 {
2001 return kStatus_InvalidArgument;
2002 }
2003
2004 fetchEco = (DPU_FETCHECO_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2005
2006 dimension = DPU_MAKE_DIMENSION(config->frameHeight - 1UL, config->frameWidth - 1UL);
2007
2008 fetchEco->STATICCONTROL = DPU_UNIT_SHDEN_MASK;
2009
2010 fetchEco->LAYER[0].BASEADDRESS = config->baseAddr;
2011 fetchEco->LAYER[0].SOURCEBUFFERATTRIBUTES =
2012 DPU_MAKE_SOURCEBUFFERATTRIBUTES(config->bitsPerPixel, config->strideBytes);
2013 fetchEco->LAYER[0].SOURCEBUFFERDIMENSION = dimension;
2014 fetchEco->LAYER[0].COLORCOMPONENTBITS = 0U;
2015 fetchEco->LAYER[0].COLORCOMPONENTSHIFT = 0U;
2016 fetchEco->LAYER[0].LAYEROFFSET = 0U;
2017 fetchEco->LAYER[0].LAYERPROPERTY |= DPU_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK;
2018 fetchEco->FRAMEDIMENSIONS = dimension;
2019
2020 fetchEco->BURSTBUFFERMANAGEMENT = DPU_BURSTBUFFERMANAGEMENT_SETNUMBUFFERS(16) |
2021 DPU_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH(DPU_FETCH_UNIT_BURST_LENGTH);
2022
2023 /* Enable Control.RawPixel. */
2024 reg = fetchEco->CONTROL & ~(DPU_FETCH_CONTROL_YUV422UPSAMPLINGMODE_MASK | DPU_FETCH_CONTROL_RASTERMODE_MASK);
2025
2026 fetchEco->CONTROL =
2027 reg | DPU_FETCH_CONTROL_RASTERMODE(kDPU_FetchCtrlRasterNormal) | DPU_FETCH_CONTROL_RAWPIXEL_MASK;
2028
2029 return kStatus_Success;
2030 }
2031
2032 /*!
2033 * brief Get default configuration structure for fetch unit source buffer.
2034 *
2035 * The default value is:
2036 * code
2037 config->baseAddr = 0U;
2038 config->strideBytes = 0x500U;
2039 config->bitsPerPixel = 32U;
2040 config->pixelFormat = kDPU_PixelFormatARGB8888;
2041 config->bufferHeight = 0U;
2042 config->bufferWidth = 0U;
2043 config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0);
2044 endcode
2045 *
2046 * param config Pointer to the configuration structure.
2047 */
DPU_SrcBufferGetDefaultConfig(dpu_src_buffer_config_t * config)2048 void DPU_SrcBufferGetDefaultConfig(dpu_src_buffer_config_t *config)
2049 {
2050 assert(NULL != config);
2051
2052 /* Initializes the configure structure to zero. */
2053 (void)memset(config, 0, sizeof(*config));
2054
2055 config->baseAddr = 0U;
2056 config->strideBytes = 0x500U;
2057 config->bitsPerPixel = 32U;
2058 config->pixelFormat = kDPU_PixelFormatARGB8888;
2059 config->bufferHeight = 0U;
2060 config->bufferWidth = 0U;
2061 config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0);
2062 }
2063
2064 /*!
2065 * brief Set the fetch unit sublayer source buffer.
2066 *
2067 * param base DPU peripheral base address.
2068 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2069 * param sublayer Sublayer index, should be 0 to 7.
2070 * param config Pointer to the configuration structure.
2071 * retval kStatus_Success Initialization success.
2072 * retval kStatus_InvalidArgument Wrong argument.
2073 */
DPU_SetFetchUnitSrcBufferConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,const dpu_src_buffer_config_t * config)2074 status_t DPU_SetFetchUnitSrcBufferConfig(IRIS_MVPL_Type *base,
2075 dpu_unit_t unit,
2076 uint8_t sublayer,
2077 const dpu_src_buffer_config_t *config)
2078 {
2079 assert(NULL != config);
2080
2081 DPU_SUBLAYER_CONTROL_Type *control;
2082
2083 /* Buffer should be aligned. */
2084 if (!(DPU_CheckBufferAlignment(config->bitsPerPixel, config->baseAddr, config->strideBytes)))
2085 {
2086 return kStatus_InvalidArgument;
2087 }
2088
2089 control = DPU_GetSubLayer(base, unit, sublayer);
2090
2091 control->BASEADDRESS = config->baseAddr;
2092 control->SOURCEBUFFERATTRIBUTES = DPU_MAKE_SOURCEBUFFERATTRIBUTES(config->bitsPerPixel, config->strideBytes);
2093 control->SOURCEBUFFERDIMENSION = DPU_MAKE_DIMENSION(config->bufferHeight - 1UL, config->bufferWidth - 1UL);
2094 control->COLORCOMPONENTBITS = s_dpuColorComponentFormats[config->pixelFormat][0];
2095 control->COLORCOMPONENTSHIFT = s_dpuColorComponentFormats[config->pixelFormat][1];
2096 control->CONSTANTCOLOR = config->constColor;
2097
2098 return kStatus_Success;
2099 }
2100
2101 /*!
2102 * brief Set the fetch unit sublayer source buffer base address.
2103 *
2104 * param base DPU peripheral base address.
2105 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2106 * param sublayer Sublayer index, should be 0 to 7.
2107 * param baseAddr Source buffer base address.
2108 */
DPU_SetFetchUnitSrcBufferAddr(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,uint32_t baseAddr)2109 void DPU_SetFetchUnitSrcBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint32_t baseAddr)
2110 {
2111 DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);
2112
2113 control->BASEADDRESS = baseAddr;
2114 }
2115
2116 /*!
2117 * brief Set the fetch unit frame size.
2118 *
2119 * param base DPU peripheral base address.
2120 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2121 * param height Frame height.
2122 * param width Frame width.
2123 */
DPU_SetFetchUnitFrameSize(IRIS_MVPL_Type * base,dpu_unit_t unit,uint16_t height,uint16_t width)2124 void DPU_SetFetchUnitFrameSize(IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t height, uint16_t width)
2125 {
2126 uint32_t offset;
2127 uint32_t type;
2128 uint32_t dimensionOffset;
2129
2130 offset = DPU_GET_UNIT_OFFSET(unit);
2131 type = DPU_GET_UNIT_TYPE(unit);
2132
2133 switch (type)
2134 {
2135 case kDPU_FetchDecode:
2136 dimensionOffset = DPU_FETCHDECODE_FRAMEDIMENSIONS_OFFSET;
2137 break;
2138
2139 case kDPU_FetchEco:
2140 dimensionOffset = DPU_FETCHECO_FRAMEDIMENSIONS_OFFSET;
2141 break;
2142
2143 case kDPU_FetchWarp:
2144 dimensionOffset = DPU_FETCHWARP_FRAMEDIMENSIONS_OFFSET;
2145 break;
2146
2147 default:
2148 dimensionOffset = DPU_FETCHLAYER_FRAMEDIMENSIONS_OFFSET;
2149 break;
2150 }
2151
2152 /* Set <unit>_FrameDimensions. */
2153 DPU_REG(base, offset + dimensionOffset) = DPU_MAKE_DIMENSION(height - 1UL, width - 1UL);
2154 }
2155
2156 /*!
2157 * brief Set the fetch unit sublayer offset.
2158 *
2159 * param base DPU peripheral base address.
2160 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2161 * param sublayer Sublayer index, should be 0 to 7.
2162 * param offsetX Horizontal offset.
2163 * param offsetY Vertical offset.
2164 */
DPU_SetFetchUnitOffset(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,uint16_t offsetX,uint16_t offsetY)2165 void DPU_SetFetchUnitOffset(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, uint16_t offsetX, uint16_t offsetY)
2166 {
2167 DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);
2168
2169 control->LAYEROFFSET = DPU_MAKE_POSITION(offsetY, offsetX);
2170 }
2171
2172 /*!
2173 * brief Enable or disable fetch unit sublayer source buffer.
2174 *
2175 * param base DPU peripheral base address.
2176 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2177 * param sublayer Sublayer index, should be 0 to 7.
2178 * param enable True to enable, false to disable.
2179 */
DPU_EnableFetchUnitSrcBuffer(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,bool enable)2180 void DPU_EnableFetchUnitSrcBuffer(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)
2181 {
2182 DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);
2183
2184 if (enable)
2185 {
2186 control->LAYERPROPERTY |= DPU_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK;
2187 }
2188 else
2189 {
2190 control->LAYERPROPERTY &= ~DPU_LAYERPROPERTY_SOURCEBUFFERENABLE_MASK;
2191 }
2192 }
2193
2194 /*!
2195 * brief Get default configuration structure for clip window.
2196 *
2197 * The default value is:
2198 * code
2199 config->windowOffsetX = 0U;
2200 config->windowOffsetY = 0U;
2201 config->windowHeight = 0U;
2202 config->windowWidth = 0U;
2203 endcode
2204 *
2205 * param config Pointer to the configuration structure.
2206 */
DPU_ClipWindowGetDefaultConfig(dpu_clip_window_config_t * config)2207 void DPU_ClipWindowGetDefaultConfig(dpu_clip_window_config_t *config)
2208 {
2209 assert(NULL != config);
2210
2211 /* Initializes the configure structure to zero. */
2212 (void)memset(config, 0, sizeof(*config));
2213
2214 config->windowOffsetX = 0U;
2215 config->windowOffsetY = 0U;
2216 config->windowHeight = 0U;
2217 config->windowWidth = 0U;
2218 }
2219
2220 /*!
2221 * brief Set the fetch unit sublayer clip window.
2222 *
2223 * param base DPU peripheral base address.
2224 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2225 * param sublayer Sublayer index, should be 0 to 7.
2226 * param config Pointer to the configuration structure.
2227 */
DPU_SetFetchUnitClipWindowConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,const dpu_clip_window_config_t * config)2228 void DPU_SetFetchUnitClipWindowConfig(IRIS_MVPL_Type *base,
2229 dpu_unit_t unit,
2230 uint8_t sublayer,
2231 const dpu_clip_window_config_t *config)
2232 {
2233 assert(NULL != config);
2234
2235 DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);
2236
2237 control->CLIPWINDOWOFFSET = DPU_MAKE_POSITION(config->windowOffsetY, config->windowOffsetX);
2238 control->CLIPWINDOWDIMENSIONS = DPU_MAKE_DIMENSION(config->windowHeight, config->windowWidth);
2239 }
2240
2241 /*!
2242 * brief Enable or disable the fetch unit sublayer clip window.
2243 *
2244 * param base DPU peripheral base address.
2245 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2246 * param sublayer Sublayer index, should be 0 to 7.
2247 * param enable True to enable, false to disable.
2248 */
DPU_EnableFetchUnitClipWindow(IRIS_MVPL_Type * base,dpu_unit_t unit,uint8_t sublayer,bool enable)2249 void DPU_EnableFetchUnitClipWindow(IRIS_MVPL_Type *base, dpu_unit_t unit, uint8_t sublayer, bool enable)
2250 {
2251 DPU_SUBLAYER_CONTROL_Type *control = DPU_GetSubLayer(base, unit, sublayer);
2252
2253 if (enable)
2254 {
2255 control->LAYERPROPERTY |= DPU_LAYERPROPERTY_CLIPWINDOWENABLE_MASK;
2256 }
2257 else
2258 {
2259 control->LAYERPROPERTY &= ~DPU_LAYERPROPERTY_CLIPWINDOWENABLE_MASK;
2260 }
2261 }
2262
2263 /*!
2264 * brief Set the fetch unit clip color mode.
2265 *
2266 * This function selects which color to take for pixels that do not lie inside
2267 * the clip window of any layer.
2268 *
2269 * param base DPU peripheral base address.
2270 * param unit DPU unit, see ref dpu_unit_t, must be fetch unit here.
2271 * param clipColorMode Select null color or use sublayer color.
2272 * param sublayer Select which sublayer's color to use when p clipColorMode
2273 * is ref kDPU_ClipColorSublayer.
2274 */
DPU_SetFetchUnitClipColor(IRIS_MVPL_Type * base,dpu_unit_t unit,dpu_clip_color_mode_t clipColorMode,uint8_t sublayer)2275 void DPU_SetFetchUnitClipColor(IRIS_MVPL_Type *base,
2276 dpu_unit_t unit,
2277 dpu_clip_color_mode_t clipColorMode,
2278 uint8_t sublayer)
2279 {
2280 uint32_t reg;
2281 uint32_t offset;
2282 uint32_t type;
2283 uint32_t controlOffset;
2284
2285 offset = DPU_GET_UNIT_OFFSET(unit);
2286 type = DPU_GET_UNIT_TYPE(unit);
2287
2288 switch (type)
2289 {
2290 case kDPU_FetchDecode:
2291 controlOffset = DPU_FETCHDECODE_CONTROL_OFFSET;
2292 break;
2293
2294 case kDPU_FetchEco:
2295 controlOffset = DPU_FETCHECO_CONTROL_OFFSET;
2296 break;
2297
2298 case kDPU_FetchWarp:
2299 controlOffset = DPU_FETCHWARP_CONTROL_OFFSET;
2300 break;
2301
2302 default:
2303 controlOffset = DPU_FETCHLAYER_CONTROL_OFFSET;
2304 break;
2305 }
2306
2307 /* Set <unit>_Control. */
2308 reg =
2309 DPU_REG(base, offset + controlOffset) & ~(DPU_FETCH_CONTROL_CLIPCOLOR_MASK | DPU_FETCH_CONTROL_CLIPLAYER_MASK);
2310
2311 if (kDPU_ClipColorNull != clipColorMode)
2312 {
2313 reg |= DPU_FETCH_CONTROL_CLIPCOLOR_MASK;
2314 reg |= DPU_FETCH_CONTROL_CLIPLAYER(sublayer);
2315 }
2316
2317 DPU_REG(base, offset + controlOffset) = reg;
2318 }
2319
2320 /*!
2321 * brief Initialize the ExtDst unit.
2322 *
2323 * param base DPU peripheral base address.
2324 * param unit DPU unit, see ref dpu_unit_t, must be ExtDst unit here.
2325 * param srcReg Input source selecte register value, pixencfg_extdstX_dynamic see ref DPU_MAKE_SRC_REG1.
2326 * The valid source:
2327 * - ref kDPU_UnitSrcNone
2328 * - ref kDPU_UnitSrcBlitBlend9
2329 * - ref kDPU_UnitSrcConstFrame0
2330 * - ref kDPU_UnitSrcConstFrame1
2331 * - ref kDPU_UnitSrcConstFrame4
2332 * - ref kDPU_UnitSrcConstFrame5
2333 * - ref kDPU_UnitSrcHScaler4
2334 * - ref kDPU_UnitSrcVScaler4
2335 * - ref kDPU_UnitSrcHScaler5
2336 * - ref kDPU_UnitSrcVScaler5
2337 * - ref kDPU_UnitSrcLayerBlend0
2338 * - ref kDPU_UnitSrcLayerBlend1
2339 * - ref kDPU_UnitSrcLayerBlend2
2340 * - ref kDPU_UnitSrcLayerBlend3
2341 */
DPU_InitExtDst(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t srcReg)2342 void DPU_InitExtDst(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
2343 {
2344 DPU_EXTDST_Type *extDst;
2345
2346 assert((uint32_t)kDPU_ExtDst == DPU_GET_UNIT_TYPE(unit));
2347
2348 extDst = (DPU_EXTDST_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2349
2350 /* Set KICK_MODE to external. */
2351 extDst->STATICCONTROL = DPU_EXTDST_STATICCONTROL_KICKMODE_MASK | DPU_UNIT_SHDEN_MASK;
2352
2353 /* Set input source selection (the register dynamic). */
2354 DPU_SetUnitSrc(base, unit, srcReg);
2355 }
2356
2357 /*!
2358 * brief Initialize the Store unit.
2359 *
2360 * The valid input source of the store unit could be:
2361 * - ref kDPU_UnitSrcNone
2362 * - ref kDPU_UnitSrcHScaler9
2363 * - ref kDPU_UnitSrcVScaler9
2364 * - ref kDPU_UnitSrcVScaler9
2365 * - ref kDPU_UnitSrcFilter9
2366 * - ref kDPU_UnitSrcBlitBlend9
2367 * - ref kDPU_UnitSrcFetchDecode9
2368 * - ref kDPU_UnitSrcFetchWarp9
2369 *
2370 * param base DPU peripheral base address.
2371 * param unit DPU unit, see ref dpu_unit_t, must be Store unit here.
2372 * param srcReg Input source selecte register value, pixencfg_extdstX_dynamic
2373 * see ref DPU_MAKE_SRC_REG1.
2374 */
DPU_InitStore(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t srcReg)2375 void DPU_InitStore(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
2376 {
2377 DPU_STORE_Type *store;
2378
2379 assert((uint32_t)kDPU_Store == DPU_GET_UNIT_TYPE(unit));
2380
2381 store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2382
2383 /* Enable Shadow. */
2384 store->STATICCONTROL = DPU_UNIT_SHDEN_MASK;
2385
2386 /* Disable ring buffer. */
2387 store->RINGBUFSTARTADDR = 0U;
2388 store->RINGBUFWRAPADDR = 0U;
2389
2390 /* Burst management. */
2391 store->BURSTBUFFERMANAGEMENT = DPU_BURSTBUFFERMANAGEMENT_SETBURSTLENGTH(16);
2392
2393 /* Set input source selection (the register dynamic). */
2394 DPU_SetUnitSrc(base, unit, srcReg);
2395 }
2396
2397 /*!
2398 * brief Set the Store unit Destination buffer configuration.
2399 *
2400 * param base DPU peripheral base address.
2401 * param unit DPU unit, see ref dpu_unit_t, must be Store unit here.
2402 * param config Pointer to the configuration.
2403 * retval kStatus_Success Initialization success.
2404 * retval kStatus_InvalidArgument Wrong argument.
2405 */
DPU_SetStoreDstBufferConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_dst_buffer_config_t * config)2406 status_t DPU_SetStoreDstBufferConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_dst_buffer_config_t *config)
2407 {
2408 assert(NULL != config);
2409
2410 /* Buffer should be aligned. */
2411 if (!(DPU_CheckBufferAlignment(config->bitsPerPixel, config->baseAddr, config->strideBytes)))
2412 {
2413 return kStatus_InvalidArgument;
2414 }
2415
2416 DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2417
2418 store->BASEADDRESS = config->baseAddr;
2419 store->DESTINATIONBUFFERATTRIBUTES =
2420 DPU_MAKE_DESTINATIONBUFFERATTRIBUTES(config->bitsPerPixel, config->strideBytes);
2421 store->DESTINATIONBUFFERDIMENSION = DPU_MAKE_DIMENSION(config->bufferHeight - 1UL, config->bufferWidth - 1UL);
2422 store->COLORCOMPONENTBITS = s_dpuColorComponentFormats[config->pixelFormat][0];
2423 store->COLORCOMPONENTSHIFT = s_dpuColorComponentFormats[config->pixelFormat][1];
2424
2425 return kStatus_Success;
2426 }
2427
2428 /*!
2429 * brief Get the default configuration for Store unit.
2430 *
2431 * The default value is:
2432 * code
2433 config->baseAddr = 0U;
2434 config->strideBytes = 0x500U;
2435 config->bitsPerPixel = 32U,
2436 config->pixelFormat = kDPU_PixelFormatARGB8888;
2437 config->bufferHeight = 0U;
2438 config->bufferWidth = 0U;
2439 endcode
2440 * param config Pointer to the configuration.
2441 */
DPU_DstBufferGetDefaultConfig(dpu_dst_buffer_config_t * config)2442 void DPU_DstBufferGetDefaultConfig(dpu_dst_buffer_config_t *config)
2443 {
2444 assert(NULL != config);
2445
2446 /* Initializes the configure structure to zero. */
2447 (void)memset(config, 0, sizeof(*config));
2448
2449 config->baseAddr = 0U;
2450 config->strideBytes = 0x500U;
2451 config->bitsPerPixel = 32U;
2452 config->pixelFormat = kDPU_PixelFormatARGB8888;
2453 config->bufferHeight = 0U;
2454 config->bufferWidth = 0U;
2455 }
2456
2457 /*!
2458 * brief Set the Store unit Destination buffer base address.
2459 *
2460 * This function is run time used for better performance.
2461 *
2462 * param base DPU peripheral base address.
2463 * param unit DPU unit, see ref dpu_unit_t, must be Store unit here.
2464 * param baseAddr Base address of the Destination buffer to set.
2465 */
DPU_SetStoreDstBufferAddr(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t baseAddr)2466 void DPU_SetStoreDstBufferAddr(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t baseAddr)
2467 {
2468 DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2469
2470 store->BASEADDRESS = baseAddr;
2471 }
2472
2473 /*!
2474 * brief Set the Store unit output offset.
2475 *
2476 * param base DPU peripheral base address.
2477 * param unit DPU unit, see ref dpu_unit_t, must be Store unit here.
2478 * param offsetX Horizontal offset.
2479 * param offsetY Vertical offset.
2480 * note The horizontal offset has limitations for some formats. It must be a multiple of
2481 * - 8 for 1 bpp buffers
2482 * - 4 for 2 bpp and 18 bpp buffers
2483 * - 2 for 4 bpp buffers
2484 */
DPU_SetStoreOffset(IRIS_MVPL_Type * base,dpu_unit_t unit,uint16_t offsetX,uint16_t offsetY)2485 void DPU_SetStoreOffset(IRIS_MVPL_Type *base, dpu_unit_t unit, uint16_t offsetX, uint16_t offsetY)
2486 {
2487 DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2488
2489 store->FRAMEOFFSET = DPU_MAKE_POSITION(offsetY, offsetX);
2490 }
2491
2492 /*!
2493 * brief Start the Store unit.
2494 *
2495 * This function starts the Store unit to save the frame to output buffer. When
2496 * the frame store completed, the interrupt flag ref kDPU_Group0Store9FrameCompleteInterrupt
2497 * asserts.
2498 *
2499 * For better performance, it is allowed to set next operation while current is still in progress.
2500 * Upper layer could set next operation immediately after shadow load finished.
2501 *
2502 * param base DPU peripheral base address.
2503 * param unit DPU unit, see ref dpu_unit_t, must be Store unit here.
2504 */
DPU_StartStore(IRIS_MVPL_Type * base,dpu_unit_t unit)2505 void DPU_StartStore(IRIS_MVPL_Type *base, dpu_unit_t unit)
2506 {
2507 DPU_STORE_Type *store = (DPU_STORE_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2508
2509 store->START = DPU_STORE_START_Start_MASK;
2510 }
2511
2512 /*!
2513 * brief Get default configuration structure for LayerBlend.
2514 *
2515 * The default value is:
2516 * code
2517 config->constAlpha = 0U;
2518 config->secAlphaBlendMode = kDPU_BlendOne;
2519 config->primAlphaBlendMode = kDPU_BlendZero;
2520 config->secColorBlendMode = kDPU_BlendOne;
2521 config->primColorBlendMode = kDPU_BlendZero;
2522 config->enableAlphaMask = true;
2523 config->alphaMaskMode = kDPU_AlphaMaskPrim;
2524 endcode
2525 *
2526 * param config Pointer to the configuration structure.
2527 */
DPU_LayerBlendGetDefaultConfig(dpu_layer_blend_config_t * config)2528 void DPU_LayerBlendGetDefaultConfig(dpu_layer_blend_config_t *config)
2529 {
2530 assert(NULL != config);
2531
2532 /* Initializes the configure structure to zero. */
2533 (void)memset(config, 0, sizeof(*config));
2534
2535 config->constAlpha = 0U;
2536 config->secAlphaBlendMode = kDPU_BlendOne;
2537 config->primAlphaBlendMode = kDPU_BlendZero;
2538 config->secColorBlendMode = kDPU_BlendOne;
2539 config->primColorBlendMode = kDPU_BlendZero;
2540 config->enableAlphaMask = false;
2541 config->alphaMaskMode = kDPU_AlphaMaskPrim;
2542 }
2543
2544 /*!
2545 * brief Initialize the LayerBlend.
2546 *
2547 * The valid primary source:
2548 * - ref kDPU_UnitSrcNone
2549 * - ref kDPU_UnitSrcConstFrame0
2550 * - ref kDPU_UnitSrcConstFrame1
2551 * - ref kDPU_UnitSrcConstFrame4
2552 * - ref kDPU_UnitSrcConstFrame5
2553 * - ref kDPU_UnitSrcHScaler4
2554 * - ref kDPU_UnitSrcVScaler4
2555 * - ref kDPU_UnitSrcHScaler5
2556 * - ref kDPU_UnitSrcVScaler5
2557 * - ref kDPU_UnitSrcMatrix4
2558 * - ref kDPU_UnitSrcMatrix5
2559 * - ref kDPU_UnitSrcLayerBlend0
2560 * - ref kDPU_UnitSrcLayerBlend1
2561 * - ref kDPU_UnitSrcLayerBlend2
2562 * - ref kDPU_UnitSrcLayerBlend3
2563 *
2564 * The valid secondary source:
2565 * - ref kDPU_UnitSrcNone
2566 * - ref kDPU_UnitSrcConstFrame0
2567 * - ref kDPU_UnitSrcConstFrame1
2568 * - ref kDPU_UnitSrcConstFrame4
2569 * - ref kDPU_UnitSrcConstFrame5
2570 * - ref kDPU_UnitSrcHScaler4
2571 * - ref kDPU_UnitSrcVScaler4
2572 * - ref kDPU_UnitSrcHScaler5
2573 * - ref kDPU_UnitSrcVScaler5
2574 * - ref kDPU_UnitSrcMatrix4
2575 * - ref kDPU_UnitSrcMatrix5
2576 * - ref kDPU_UnitSrcLayerBlend0
2577 * - ref kDPU_UnitSrcLayerBlend1
2578 * - ref kDPU_UnitSrcLayerBlend2
2579 * - ref kDPU_UnitSrcLayerBlend3
2580 *
2581 * param base DPU peripheral base address.
2582 * param unit DPU unit, see ref dpu_unit_t, must be LayerBlend unit here.
2583 * param srcReg Unit source selection, see ref DPU_MAKE_SRC_REG2.
2584 */
DPU_InitLayerBlend(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t srcReg)2585 void DPU_InitLayerBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
2586 {
2587 DPU_LAYERBLEND_Type *layerBlend;
2588
2589 assert((uint32_t)kDPU_LayerBlend == DPU_GET_UNIT_TYPE(unit));
2590
2591 layerBlend = (DPU_LAYERBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2592
2593 /* Shadow token generate mode: BOTH. Shadow load mode: Both. */
2594 layerBlend->STATICCONTROL = DPU_LAYERBLEND_STATICCONTROL_ShdEn_MASK |
2595 DPU_LAYERBLEND_STATICCONTROL_ShdTokSel(kDPU_LayerBlendShadowTokenBoth) |
2596 DPU_LAYERBLEND_STATICCONTROL_ShdLdSel(kDPU_LayerBlendShadowLoadBoth);
2597
2598 /*
2599 * Disable second frame overlay position. Explaination from the spec:
2600 * Note: Technically the foreground plane can be setup with a smaller dimension
2601 * than the background and placed by the LayerBlend unit itself (Position.XPOS/YPOS),
2602 * however, this must not be done for the following reasons:
2603 * - Layer overlay must be completely inside the background area then, otherwise
2604 * display tearing may result. This would require clip window computations by SW.
2605 * - Timing setup for certain use cases is not valid any longer, because Fetch unit
2606 * starts fetching source buffer data for a layer not at position of first overlay
2607 * pixel, but at first pixel of the background plane already.
2608 * - Layer position is not part of the shadow load domain correlated to the layer,
2609 * but to the stream.
2610 */
2611 layerBlend->POSITION = 0U;
2612
2613 DPU_SetUnitSrc(base, unit, srcReg);
2614 }
2615
2616 /*!
2617 * brief Set the LayerBlend unit configuration.
2618 *
2619 * param base DPU peripheral base address.
2620 * param unit DPU unit, see ref dpu_unit_t, must be LayerBlend unit here.
2621 * param config Pointer to the configuration structure.
2622 */
DPU_SetLayerBlendConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_layer_blend_config_t * config)2623 void DPU_SetLayerBlendConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_layer_blend_config_t *config)
2624 {
2625 assert(NULL != config);
2626
2627 DPU_LAYERBLEND_Type *layerBlend;
2628
2629 layerBlend = (DPU_LAYERBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2630
2631 /* Set layer blend control. */
2632 layerBlend->BLENDCONTROL = DPU_LAYERBLEND_BLENDCONTROL_BlendAlpha(config->constAlpha) |
2633 DPU_LAYERBLEND_BLENDCONTROL_PRIM_C_BLD_FUNC(config->primColorBlendMode) |
2634 DPU_LAYERBLEND_BLENDCONTROL_SEC_C_BLD_FUNC(config->secColorBlendMode) |
2635 DPU_LAYERBLEND_BLENDCONTROL_PRIM_A_BLD_FUNC(config->primAlphaBlendMode) |
2636 DPU_LAYERBLEND_BLENDCONTROL_SEC_A_BLD_FUNC(config->secAlphaBlendMode);
2637
2638 /* Set alpha mask config. */
2639 layerBlend->CONTROL = ((layerBlend->CONTROL & ~(DPU_LAYERBLEND_CONTROL_AlphaMaskEnable_MASK |
2640 DPU_LAYERBLEND_CONTROL_AlphaMaskMode_MASK)) |
2641 DPU_LAYERBLEND_CONTROL_AlphaMaskEnable(config->enableAlphaMask) |
2642 DPU_LAYERBLEND_CONTROL_AlphaMaskMode(config->alphaMaskMode));
2643 }
2644
2645 /*!
2646 * brief Enable or disable the LayerBlend unit.
2647 *
2648 * If enabled, the blend result is output, otherwise, the primary input is output.
2649 *
2650 * param base DPU peripheral base address.
2651 * param unit DPU unit, see ref dpu_unit_t, must be LayerBlend unit here.
2652 * param enable Pass true to enable, false to disable.
2653 */
DPU_EnableLayerBlend(IRIS_MVPL_Type * base,dpu_unit_t unit,bool enable)2654 void DPU_EnableLayerBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
2655 {
2656 DPU_LAYERBLEND_Type *layerBlend = (DPU_LAYERBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2657
2658 if (enable)
2659 {
2660 layerBlend->CONTROL |= DPU_LAYERBLEND_CONTROL_MODE_MASK;
2661 }
2662 else
2663 {
2664 layerBlend->CONTROL &= ~DPU_LAYERBLEND_CONTROL_MODE_MASK;
2665 }
2666 }
2667
2668 /*!
2669 * brief Initialize the ROp unit.
2670 *
2671 * The primary input source of the unit could be:
2672 * - ref kDPU_UnitSrcNone
2673 * - ref kDPU_UnitSrcFetchDecode9
2674 * - ref kDPU_UnitSrcFetchWarp9
2675 *
2676 * The secondary input source of the unit could be:
2677 * - ref kDPU_UnitSrcNone
2678 * - ref kDPU_UnitSrcFetchEco9
2679 *
2680 * The tert input source of the unit could be:
2681 * - ref kDPU_UnitSrcNone
2682 * - ref kDPU_UnitSrcFetchDecode9
2683 * - ref kDPU_UnitSrcFetchWarp9
2684 *
2685 * param base DPU peripheral base address.
2686 * param unit DPU unit, see ref dpu_unit_t, must be Rop unit here.
2687 * param srcReg Unit source selection, see ref DPU_MAKE_SRC_REG3.
2688 */
DPU_InitRop(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t srcReg)2689 void DPU_InitRop(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
2690 {
2691 assert((uint32_t)kDPU_Rop == DPU_GET_UNIT_TYPE(unit));
2692
2693 DPU_ROP_Type *rop = (DPU_ROP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2694
2695 rop->STATICCONTROL = DPU_UNIT_SHDEN_MASK;
2696
2697 DPU_SetUnitSrc(base, unit, srcReg);
2698 }
2699
2700 /*!
2701 * brief Get the default ROp unit configuration.
2702 *
2703 * The default configuration is:
2704 *
2705 * code
2706 config->controlFlags = 0U;
2707 config->alphaIndex = 0U;
2708 config->blueIndex = 0U;
2709 config->greenIndex = 0U;
2710 config->redIndex = 0U;
2711 endcode
2712 * param config Pointer to the configuration structure.
2713 */
DPU_RopGetDefaultConfig(dpu_rop_config_t * config)2714 void DPU_RopGetDefaultConfig(dpu_rop_config_t *config)
2715 {
2716 assert(NULL != config);
2717
2718 /* Initializes the configure structure to zero. */
2719 (void)memset(config, 0, sizeof(*config));
2720
2721 config->controlFlags = 0U;
2722 config->alphaIndex = 0U;
2723 config->blueIndex = 0U;
2724 config->greenIndex = 0U;
2725 config->redIndex = 0U;
2726 }
2727
2728 /*!
2729 * brief Set the ROp unit configuration.
2730 *
2731 * param base DPU peripheral base address.
2732 * param unit DPU unit, see ref dpu_unit_t, must be Rop unit here.
2733 * param config Pointer to the configuration structure.
2734 */
DPU_SetRopConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_rop_config_t * config)2735 void DPU_SetRopConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_rop_config_t *config)
2736 {
2737 assert(NULL != config);
2738
2739 DPU_ROP_Type *rop = (DPU_ROP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2740
2741 rop->RASTEROPERATIONINDICES =
2742 DPU_MAKE_CONST_COLOR(config->redIndex, config->greenIndex, config->blueIndex, config->alphaIndex);
2743 rop->CONTROL = (rop->CONTROL & DPU_ROP_CONTROL_Mode_MASK) | config->controlFlags;
2744 }
2745
2746 /*!
2747 * brief Enable or disable the ROp unit.
2748 *
2749 * If disabled, only the primary input is output.
2750 *
2751 * param base DPU peripheral base address.
2752 * param unit DPU unit, see ref dpu_unit_t, must be Rop unit here.
2753 * param enable Pass true to enable, false to disable.
2754 */
DPU_EnableRop(IRIS_MVPL_Type * base,dpu_unit_t unit,bool enable)2755 void DPU_EnableRop(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
2756 {
2757 DPU_ROP_Type *rop = (DPU_ROP_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2758
2759 if (enable)
2760 {
2761 rop->CONTROL |= DPU_ROP_CONTROL_Mode_MASK;
2762 }
2763 else
2764 {
2765 rop->CONTROL &= ~DPU_ROP_CONTROL_Mode_MASK;
2766 }
2767 }
2768
2769 /*!
2770 * brief Initialize the BlitBlend unit.
2771 *
2772 * The valid input primary source could be:
2773 * - ref kDPU_UnitSrcNone
2774 * - ref kDPU_UnitSrcHScaler9
2775 * - ref kDPU_UnitSrcVScaler9
2776 * - ref kDPU_UnitSrcFilter9
2777 * - ref kDPU_UnitSrcRop9
2778 *
2779 * The valid input secondary source could be:
2780 * - ref kDPU_UnitSrcNone
2781 * - ref kDPU_UnitSrcFetchDecode9
2782 * - ref kDPU_UnitSrcFetchWarp9
2783 *
2784 * param base DPU peripheral base address.
2785 * param unit DPU unit, see ref dpu_unit_t, must be BlitBlend unit here.
2786 * param srcReg Unit source selection, see ref DPU_MAKE_SRC_REG2.
2787 */
DPU_InitBlitBlend(IRIS_MVPL_Type * base,dpu_unit_t unit,uint32_t srcReg)2788 void DPU_InitBlitBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, uint32_t srcReg)
2789 {
2790 assert((uint32_t)kDPU_BlitBlend == DPU_GET_UNIT_TYPE(unit));
2791
2792 DPU_BLITBLEND_Type *blitBlend = (DPU_BLITBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2793
2794 blitBlend->STATICCONTROL = DPU_UNIT_SHDEN_MASK;
2795
2796 DPU_SetUnitSrc(base, unit, srcReg);
2797 }
2798
2799 /*!
2800 * brief Get the default BlitBlend unit configuration.
2801 *
2802 * The default configuration is:
2803 * code
2804 config->neutralBorderRightPixels = 0U;
2805 config->neutralBorderLeftPixels = 0U;
2806 config->neutralBorderMode = kDPU_BlitBlendNeutralBorderPrim;
2807 config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0);
2808 config->redBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2809 config->redBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2810 config->greenBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2811 config->greenBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2812 config->blueBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2813 config->blueBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2814 config->alphaBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2815 config->alphaBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2816 config->redBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2817 config->greenBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2818 config->blueBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2819 config->alphaBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2820 endcode
2821 * param config Pointer to the configuration structure.
2822 */
DPU_BlitBlendGetDefaultConfig(dpu_blit_blend_config_t * config)2823 void DPU_BlitBlendGetDefaultConfig(dpu_blit_blend_config_t *config)
2824 {
2825 assert(NULL != config);
2826
2827 /* Initializes the configure structure to zero. */
2828 (void)memset(config, 0, sizeof(*config));
2829
2830 config->neutralBorderRightPixels = 0U;
2831 config->neutralBorderLeftPixels = 0U;
2832 config->neutralBorderMode = kDPU_BlitBlendNeutralBorderPrim;
2833
2834 config->constColor = DPU_MAKE_CONST_COLOR(0, 0, 0, 0);
2835
2836 config->redBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2837 config->redBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2838 config->greenBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2839 config->greenBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2840 config->blueBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2841 config->blueBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2842 config->alphaBlendFuncSrc = kDPU_BlitBlendFuncGlSrcColor;
2843 config->alphaBlendFuncDst = kDPU_BlitBlendFuncGlSrcColor;
2844 config->redBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2845 config->greenBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2846 config->blueBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2847 config->alphaBlendMode = kDPU_BlitBlendModeGlFuncAdd;
2848 }
2849
2850 /*!
2851 * brief Set the BlitBlend unit configuration.
2852 *
2853 * param base DPU peripheral base address.
2854 * param unit DPU unit, see ref dpu_unit_t, must be BlitBlend unit here.
2855 * param config Pointer to the configuration structure.
2856 */
DPU_SetBlitBlendConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_blit_blend_config_t * config)2857 void DPU_SetBlitBlendConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_blit_blend_config_t *config)
2858 {
2859 assert(NULL != config);
2860
2861 DPU_BLITBLEND_Type *blitBlend = (DPU_BLITBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2862
2863 blitBlend->NEUTRALBORDER = DPU_BLITBLEND_NEUTRALBORDER_NeutralBorderLeft(config->neutralBorderLeftPixels) |
2864 DPU_BLITBLEND_NEUTRALBORDER_NeutralBorderRight(config->neutralBorderRightPixels) |
2865 DPU_BLITBLEND_NEUTRALBORDER_NeutralBorderMode(config->neutralBorderMode);
2866
2867 blitBlend->CONSTANTCOLOR = config->constColor;
2868
2869 blitBlend->COLORREDBLENDFUNCTION =
2870 (((uint32_t)config->redBlendFuncDst) << 16U) | (uint32_t)(config->redBlendFuncSrc);
2871 blitBlend->COLORGREENBLENDFUNCTION =
2872 (((uint32_t)config->greenBlendFuncDst) << 16U) | (uint32_t)(config->greenBlendFuncSrc);
2873 blitBlend->COLORBLUEBLENDFUNCTION =
2874 (((uint32_t)config->blueBlendFuncDst) << 16U) | (uint32_t)(config->blueBlendFuncSrc);
2875 blitBlend->ALPHABLENDFUNCTION =
2876 (((uint32_t)config->alphaBlendFuncDst) << 16U) | (uint32_t)(config->alphaBlendFuncSrc);
2877 blitBlend->BLENDMODE1 = (((uint32_t)config->greenBlendMode) << 16U) | (uint32_t)(config->redBlendMode);
2878 blitBlend->BLENDMODE2 = (((uint32_t)config->alphaBlendMode) << 16U) | (uint32_t)(config->blueBlendMode);
2879 }
2880
2881 /*!
2882 * brief Enable or disable the BlitBlend unit.
2883 *
2884 * The BlitBlend unit could be runtime enabled or disabled, when disabled, the
2885 * primary input is output directly.
2886 *
2887 * param base DPU peripheral base address.
2888 * param unit DPU unit, see ref dpu_unit_t, must be BlitBlend unit here.
2889 * param enable Pass true to enable, false to disable.
2890 */
DPU_EnableBlitBlend(IRIS_MVPL_Type * base,dpu_unit_t unit,bool enable)2891 void DPU_EnableBlitBlend(IRIS_MVPL_Type *base, dpu_unit_t unit, bool enable)
2892 {
2893 DPU_BLITBLEND_Type *blitBlend = (DPU_BLITBLEND_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2894
2895 if (enable)
2896 {
2897 blitBlend->CONTROL = DPU_BLITBLEND_CONTROL_Mode_MASK;
2898 }
2899 else
2900 {
2901 blitBlend->CONTROL = 0U;
2902 }
2903 }
2904
2905 /*!
2906 * brief Initialize the ConstFrame unit.
2907 *
2908 * param base DPU peripheral base address.
2909 * param unit DPU unit, see ref dpu_unit_t, must be ConstFrame unit here.
2910 */
DPU_InitConstFrame(IRIS_MVPL_Type * base,dpu_unit_t unit)2911 void DPU_InitConstFrame(IRIS_MVPL_Type *base, dpu_unit_t unit)
2912 {
2913 assert((uint32_t)kDPU_ConstFrame == DPU_GET_UNIT_TYPE(unit));
2914
2915 DPU_CONSTFRAME_Type *constFrame = (DPU_CONSTFRAME_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2916
2917 constFrame->STATICCONTROL = DPU_UNIT_SHDEN_MASK;
2918 }
2919
2920 /*!
2921 * brief Get default configuration structure for ConstFrame unit.
2922 *
2923 * The default value is:
2924 code
2925 config->frameHeight = 320U;
2926 config->frameWidth = 480U;
2927 config->constColor = DPU_MAKE_CONST_COLOR(0xFF, 0xFF, 0xFF, 0xFF);
2928 endcode
2929 *
2930 * param config Pointer to the configuration structure.
2931 */
DPU_ConstFrameGetDefaultConfig(dpu_const_frame_config_t * config)2932 void DPU_ConstFrameGetDefaultConfig(dpu_const_frame_config_t *config)
2933 {
2934 assert(NULL != config);
2935
2936 /* Initializes the configure structure to zero. */
2937 (void)memset(config, 0, sizeof(*config));
2938
2939 config->frameHeight = 320U;
2940 config->frameWidth = 480U;
2941 config->constColor = DPU_MAKE_CONST_COLOR(0xFF, 0xFF, 0xFF, 0xFF);
2942 }
2943
2944 /*!
2945 * brief Set the ConstFrame unit configuration.
2946 *
2947 * param base DPU peripheral base address.
2948 * param unit DPU unit, see ref dpu_unit_t, must be ConstFrame unit here.
2949 * param config Pointer to the configuration structure.
2950 */
DPU_SetConstFrameConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_const_frame_config_t * config)2951 void DPU_SetConstFrameConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_const_frame_config_t *config)
2952 {
2953 assert(NULL != config);
2954
2955 DPU_CONSTFRAME_Type *constFrame = (DPU_CONSTFRAME_Type *)(((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit));
2956
2957 constFrame->FRAMEDIMENSIONS = DPU_MAKE_DIMENSION(config->frameHeight - 1UL, config->frameWidth - 1UL);
2958 constFrame->CONSTANTCOLOR = config->constColor;
2959 }
2960
2961 /*!
2962 * brief Initialize the VScaler or HScaler unit.
2963 *
2964 * param base DPU peripheral base address.
2965 * param unit DPU unit, see ref dpu_unit_t, must be HScaler or VScaler unit here.
2966 */
DPU_InitScaler(IRIS_MVPL_Type * base,dpu_unit_t unit)2967 void DPU_InitScaler(IRIS_MVPL_Type *base, dpu_unit_t unit)
2968 {
2969 assert(((uint32_t)kDPU_VScaler == DPU_GET_UNIT_TYPE(unit)) ||
2970 (((uint32_t)kDPU_HScaler == DPU_GET_UNIT_TYPE(unit))));
2971
2972 (void)DPU_EnableShadowLoad(base, unit, true);
2973 }
2974
2975 /*!
2976 * brief Get default configuration structure for VScaler and HScaler.
2977 *
2978 * The default value is:
2979 code
2980 config->srcReg = 0U;
2981 config->inputSize = 0U;
2982 config->outputSize = 0U;
2983 endcode
2984 *
2985 * param config Pointer to the configuration structure.
2986 */
DPU_ScalerGetDefaultConfig(dpu_scaler_config_t * config)2987 void DPU_ScalerGetDefaultConfig(dpu_scaler_config_t *config)
2988 {
2989 assert(NULL != config);
2990
2991 /* Initializes the configure structure to zero. */
2992 (void)memset(config, 0, sizeof(*config));
2993
2994 config->srcReg = 0U;
2995 config->inputSize = 0U;
2996 config->outputSize = 0U;
2997 }
2998
2999 /*!
3000 * brief Set the VScaler or HScaler units configuration.
3001 *
3002 * The valid input source could be:
3003 * - ref kDPU_UnitSrcNone
3004 * - ref kDPU_UnitSrcFetchDecode0
3005 * - ref kDPU_UnitSrcMatrix4
3006 * - ref kDPU_UnitSrcVScaler4
3007 * - ref kDPU_UnitSrcHScaler4
3008 * - ref kDPU_UnitSrcFetchDecode1
3009 * - ref kDPU_UnitSrcMatrix5
3010 * - ref kDPU_UnitSrcVScaler5
3011 * - ref kDPU_UnitSrcHScaler5
3012 * - ref kDPU_UnitSrcVScaler9
3013 * - ref kDPU_UnitSrcHScaler9
3014 * - ref kDPU_UnitSrcFilter9
3015 * - ref kDPU_UnitSrcMatrix9
3016 *
3017 * param base DPU peripheral base address.
3018 * param unit DPU unit, see ref dpu_unit_t, must be HScaler or VScaler unit here.
3019 * param config Pointer to the configuration structure.
3020 */
DPU_SetScalerConfig(IRIS_MVPL_Type * base,dpu_unit_t unit,const dpu_scaler_config_t * config)3021 void DPU_SetScalerConfig(IRIS_MVPL_Type *base, dpu_unit_t unit, const dpu_scaler_config_t *config)
3022 {
3023 assert(NULL != config);
3024
3025 float scaleFact;
3026 uint32_t control;
3027 uint32_t setup1;
3028 uint32_t offset = ((uint32_t)base) + DPU_GET_UNIT_OFFSET(unit);
3029
3030 control = DPU_SCALER_CONTROL_OUTPUTSIZE(config->outputSize - 1UL) | DPU_SCALER_CONTROL_FILTERMODE_MASK |
3031 DPU_SCALER_CONTROL_MODE_MASK;
3032
3033 if (config->inputSize > config->outputSize)
3034 {
3035 scaleFact = (float)config->outputSize / (float)config->inputSize;
3036 }
3037 else
3038 {
3039 /* Output size is larger, use up-scaling mode. */
3040 control |= DPU_SCALER_CONTROL_SCALEMODE_MASK;
3041 scaleFact = (float)config->inputSize / (float)config->outputSize;
3042 }
3043
3044 /*
3045 * The scale fact is a float value (0.0 to 1.0], it should be converted to
3046 * fixed 1.19 value and set to register SETUP1.
3047 */
3048 setup1 = DPU_ConvertFloat(scaleFact, 1, 19);
3049
3050 if (0U == setup1)
3051 {
3052 setup1 = 1U;
3053 }
3054 else if (setup1 > 0x80000U)
3055 {
3056 setup1 = 0x80000U;
3057 }
3058 else
3059 {
3060 /* MISRA 15.7 */
3061 }
3062
3063 ((DPU_VSCALER_Type *)offset)->SETUP1 = setup1;
3064
3065 if ((uint32_t)kDPU_VScaler == DPU_GET_UNIT_TYPE(unit))
3066 {
3067 ((DPU_VSCALER_Type *)offset)->CONTROL = control;
3068 }
3069 else
3070 {
3071 ((DPU_HSCALER_Type *)offset)->CONTROL = control;
3072 }
3073
3074 DPU_SetUnitSrc(base, unit, config->srcReg);
3075 }
3076
3077 /*!
3078 * brief Get default configuration structure for display mode.
3079 *
3080 * The default value is:
3081 * code
3082 config->flags = kDPU_DisplayDeActiveHigh;
3083 config->width = 320U;
3084 config->hsw = 32U;
3085 config->hfp = 8U;
3086 config->hbp = 40U;
3087 config->height = 240U;
3088 config->vsw = 4U;
3089 config->vfp = 13U;
3090 config->vbp = 6U;
3091 endcode
3092 *
3093 * param config Pointer to the configuration structure.
3094 */
DPU_DisplayTimingGetDefaultConfig(dpu_display_timing_config_t * config)3095 void DPU_DisplayTimingGetDefaultConfig(dpu_display_timing_config_t *config)
3096 {
3097 assert(NULL != config);
3098
3099 /* Initializes the configure structure to zero. */
3100 (void)memset(config, 0, sizeof(*config));
3101
3102 config->flags = (uint16_t)kDPU_DisplayDataEnableActiveHigh;
3103 config->width = 320U;
3104 config->hsw = 32U;
3105 config->hfp = 8U;
3106 config->hbp = 40U;
3107 config->height = 240U;
3108 config->vsw = 4U;
3109 config->vfp = 13U;
3110 config->vbp = 6U;
3111 }
3112
3113 /*!
3114 * brief Initialize the display timing.
3115 *
3116 * param base DPU peripheral base address.
3117 * param displayIndex Index of the display.
3118 * param config Pointer to the configuration structure.
3119 */
DPU_InitDisplayTiming(IRIS_MVPL_Type * base,uint8_t displayIndex,const dpu_display_timing_config_t * config)3120 void DPU_InitDisplayTiming(IRIS_MVPL_Type *base, uint8_t displayIndex, const dpu_display_timing_config_t *config)
3121 {
3122 assert(displayIndex < DPU_DISPLAY_COUNT);
3123
3124 uint32_t reg;
3125 uint16_t vtotal;
3126 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3127 DPU_DISENGCONF_Type *diseng = (DPU_DISENGCONF_Type *)(((uint32_t)base) + DPU_DISENGCONF_OFFSET);
3128
3129 display->FRAMEGEN.FGSTCTRL |= DPU_UNIT_SHDEN_MASK;
3130
3131 /* Set signal polarity. */
3132 reg = config->flags & ((uint32_t)kDPU_DisplayPixelActiveLow | (uint32_t)kDPU_DisplayDataEnableActiveHigh |
3133 (uint32_t)kDPU_DisplayHsyncActiveHigh | (uint32_t)kDPU_DisplayVsyncActiveHigh);
3134
3135 diseng->DISPLAY[displayIndex].POLARITYCTRL = reg;
3136
3137 /* Set timing. */
3138 vtotal = config->height + config->vfp + config->vbp + config->vsw - 1U;
3139 display->FRAMEGEN.HTCFG1 =
3140 DPU_FRAMEGEN_HTCFG1_Htotal((uint32_t)config->width + config->hfp + config->hbp + config->hsw - 1UL) |
3141 DPU_FRAMEGEN_HTCFG1_Hact(config->width);
3142
3143 display->FRAMEGEN.HTCFG2 = DPU_FRAMEGEN_HTCFG2_Hsync(config->hsw - 1UL) |
3144 DPU_FRAMEGEN_HTCFG2_Hsbp((uint32_t)config->hbp + config->hsw - 1UL) |
3145 DPU_FRAMEGEN_HTCFG2_HsEn_MASK;
3146
3147 display->FRAMEGEN.VTCFG1 = DPU_FRAMEGEN_VTCFG1_Vtotal(vtotal) | DPU_FRAMEGEN_VTCFG1_Vact(config->height);
3148
3149 display->FRAMEGEN.VTCFG2 = DPU_FRAMEGEN_VTCFG2_Vsync(config->vsw - 1UL) |
3150 DPU_FRAMEGEN_VTCFG2_Vsbp((uint32_t)config->vbp + config->vsw - 1UL) |
3151 DPU_FRAMEGEN_VTCFG2_VsEn_MASK;
3152
3153 /* Set TCON for the signal mapping. */
3154 display->TCON.TCON_CTRL = display->TCON.TCON_CTRL & ~DPU_TCON_TCON_CTRL_Bypass_MASK;
3155 display->TCON.MAPBIT3_0 = 0x17161514U;
3156 display->TCON.MAPBIT7_4 = 0x1b1a1918U;
3157 display->TCON.MAPBIT11_8 = 0x0b0a1d1cU;
3158 display->TCON.MAPBIT15_12 = 0x0f0e0d0cU;
3159 display->TCON.MAPBIT19_16 = 0x13121110U;
3160 display->TCON.MAPBIT23_20 = 0x03020100U;
3161 display->TCON.MAPBIT27_24 = 0x07060504U;
3162 display->TCON.MAPBIT31_28 = 0x00000908U;
3163 display->TCON.MAPBIT34_32 = 0x00222120U;
3164
3165 /* Set TCON for the SYNC signals. */
3166 display->TCON.SPG[0].SPGPOSON = DPU_TCON_SPGPOSON_SPGPSON_X((uint32_t)config->width + config->hfp);
3167 display->TCON.SPG[0].SPGMASKON = DPU_TCON_SPGPOSON_SPGPSON_Y_MASK;
3168 display->TCON.SPG[0].SPGPOSOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_X((uint32_t)config->width + config->hfp + config->hsw);
3169 display->TCON.SPG[0].SPGMASKOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_Y_MASK;
3170
3171 display->TCON.SPG[1].SPGPOSON = DPU_TCON_SPGPOSON_SPGPSON_X((uint32_t)config->width + config->hfp) |
3172 DPU_TCON_SPGPOSON_SPGPSON_Y((uint32_t)config->height + config->vfp - 1UL);
3173 display->TCON.SPG[1].SPGMASKON = 0;
3174 display->TCON.SPG[1].SPGPOSOFF =
3175 DPU_TCON_SPGPOSOFF_SPGPSOFF_X((uint32_t)config->width + config->hfp) |
3176 DPU_TCON_SPGPOSOFF_SPGPSOFF_Y((uint32_t)config->height + config->vfp + config->vsw - 1UL);
3177 display->TCON.SPG[1].SPGMASKOFF = 0;
3178
3179 display->TCON.SPG[2].SPGPOSON = DPU_TCON_SPGPOSON_SPGPSON_X(0U);
3180 display->TCON.SPG[2].SPGMASKON = DPU_TCON_SPGPOSON_SPGPSON_Y_MASK;
3181 display->TCON.SPG[2].SPGPOSOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_X(config->width);
3182 display->TCON.SPG[2].SPGMASKOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_Y_MASK;
3183
3184 display->TCON.SPG[3].SPGPOSON = DPU_TCON_SPGPOSON_SPGPSON_Y(0U);
3185 display->TCON.SPG[3].SPGMASKON = DPU_TCON_SPGPOSON_SPGPSON_X_MASK;
3186 display->TCON.SPG[3].SPGPOSOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_Y(config->height);
3187 display->TCON.SPG[3].SPGMASKOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_X_MASK;
3188
3189 display->TCON.SPG[4].SPGPOSON = DPU_TCON_SPGPOSON_SPGPSON_Y(config->height) | DPU_TCON_SPGPOSON_SPGPSON_X(0x0AU);
3190 display->TCON.SPG[4].SPGMASKON = 0U;
3191 display->TCON.SPG[4].SPGPOSOFF = DPU_TCON_SPGPOSOFF_SPGPSOFF_Y(config->height) | DPU_TCON_SPGPOSON_SPGPSON_X(0x2AU);
3192 display->TCON.SPG[4].SPGMASKOFF = 0U;
3193
3194 /* HSYNC. */
3195 display->TCON.SMX[0].SMXSIGS = DPU_TCON_SMXSIGS_SMXSIGS_S0(0x02U);
3196 display->TCON.SMX[0].SMXFCTTABLE = 0x01U;
3197
3198 /* VSYNC. */
3199 display->TCON.SMX[1].SMXSIGS = DPU_TCON_SMXSIGS_SMXSIGS_S0(0x03U);
3200 display->TCON.SMX[1].SMXFCTTABLE = 0x01U;
3201
3202 /* Data output enable. */
3203 display->TCON.SMX[2].SMXSIGS = DPU_TCON_SMXSIGS_SMXSIGS_S0(0x04U) | DPU_TCON_SMXSIGS_SMXSIGS_S1(0x05U);
3204 display->TCON.SMX[2].SMXFCTTABLE = 0x08U;
3205
3206 /* Sync signal to trigger shadow load. This should be at least 32 pixel clock after KICK signal. */
3207 display->TCON.SMX[3].SMXSIGS = DPU_TCON_SMXSIGS_SMXSIGS_S0(0x06U);
3208 display->TCON.SMX[3].SMXFCTTABLE = 0x02U;
3209
3210 /* KICK signal set to start of last vertical blanking line. */
3211 display->FRAMEGEN.PKICKCONFIG = DPU_FRAMEGEN_PKICKCONFIG_PKickRow(config->height) |
3212 DPU_FRAMEGEN_PKICKCONFIG_PKickCol(config->width + 1UL) |
3213 DPU_FRAMEGEN_PKICKCONFIG_PKickEn_MASK;
3214
3215 display->FRAMEGEN.SKICKCONFIG = DPU_FRAMEGEN_SKICKCONFIG_SKickRow(config->height) |
3216 DPU_FRAMEGEN_SKICKCONFIG_SKickCol(config->width + 1UL) |
3217 DPU_FRAMEGEN_SKICKCONFIG_SKickEn_MASK;
3218 }
3219
3220 /*!
3221 * brief Get default configuration structure for display frame mode.
3222 *
3223 * The default value is:
3224 code
3225 config->enablePrimAlpha = false;
3226 config->enableSecAlpha = false;
3227 config->displayMode = kDPU_DisplayTest;
3228 config->enablePrimAlphaInPanic = false;
3229 config->enableSecAlphaInPanic = false;
3230 config->displayModeInPanic = kDPU_DisplayTest;
3231 config->constRed = 0x3FFU;
3232 config->constGreen = 0x3FFU;
3233 config->constBlue = 0x3FFU;
3234 config->constAlpha = 1U;
3235 config->primAreaStartX = 1U;
3236 config->primAreaStartY = 1U;
3237 config->secAreaStartX = 1U;
3238 config->secAreaStartY = 1U;
3239 endcode
3240 *
3241 * param config Pointer to the configuration structure.
3242 */
DPU_DisplayGetDefaultConfig(dpu_display_config_t * config)3243 void DPU_DisplayGetDefaultConfig(dpu_display_config_t *config)
3244 {
3245 assert(NULL != config);
3246
3247 /* Initializes the configure structure to zero. */
3248 (void)memset(config, 0, sizeof(*config));
3249
3250 config->enablePrimAlpha = false;
3251 config->enableSecAlpha = false;
3252 config->displayMode = kDPU_DisplayTest;
3253 config->enablePrimAlphaInPanic = false;
3254 config->enableSecAlphaInPanic = false;
3255 config->displayModeInPanic = kDPU_DisplayTest;
3256 config->constRed = 0x3FFU;
3257 config->constGreen = 0x3FFU;
3258 config->constBlue = 0x3FFU;
3259 config->constAlpha = 1U;
3260 config->primAreaStartX = 1U;
3261 config->primAreaStartY = 1U;
3262 config->secAreaStartX = 1U;
3263 config->secAreaStartY = 1U;
3264 }
3265
3266 /*!
3267 * brief Set the display mode.
3268 *
3269 * param base DPU peripheral base address.
3270 * param displayIndex Index of the display.
3271 * param config Pointer to the configuration structure.
3272 */
DPU_SetDisplayConfig(IRIS_MVPL_Type * base,uint8_t displayIndex,const dpu_display_config_t * config)3273 void DPU_SetDisplayConfig(IRIS_MVPL_Type *base, uint8_t displayIndex, const dpu_display_config_t *config)
3274 {
3275 assert(displayIndex < DPU_DISPLAY_COUNT);
3276
3277 uint32_t reg;
3278 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3279
3280 /* Area configure. */
3281 display->FRAMEGEN.PACFG =
3282 DPU_FRAMEGEN_PACFG_Pstartx(config->primAreaStartX) | DPU_FRAMEGEN_PACFG_Pstarty(config->primAreaStartY);
3283 display->FRAMEGEN.SACFG =
3284 DPU_FRAMEGEN_SACFG_Sstartx(config->secAreaStartX) | DPU_FRAMEGEN_SACFG_Sstarty(config->secAreaStartY);
3285
3286 /* Input control. */
3287 reg = DPU_FRAMEGEN_FGINCTRL_FgDm(config->displayMode);
3288
3289 if (config->enableSecAlpha)
3290 {
3291 reg |= DPU_FRAMEGEN_FGINCTRL_EnSecAlpha_MASK;
3292 }
3293
3294 if (config->enablePrimAlpha)
3295 {
3296 reg |= DPU_FRAMEGEN_FGINCTRL_EnPrimAlpha_MASK;
3297 }
3298
3299 display->FRAMEGEN.FGINCTRL = reg;
3300
3301 reg = DPU_FRAMEGEN_FGINCTRL_FgDm(config->displayModeInPanic);
3302
3303 if (config->enableSecAlphaInPanic)
3304 {
3305 reg |= DPU_FRAMEGEN_FGINCTRL_EnSecAlpha_MASK;
3306 }
3307
3308 if (config->enablePrimAlphaInPanic)
3309 {
3310 reg |= DPU_FRAMEGEN_FGINCTRL_EnPrimAlpha_MASK;
3311 }
3312 display->FRAMEGEN.FGINCTRLPANIC = reg;
3313
3314 /* Configure constant color. */
3315 display->FRAMEGEN.FGCCR =
3316 DPU_FRAMEGEN_FGCCR_CcBlue(config->constBlue) | DPU_FRAMEGEN_FGCCR_CcGreen(config->constGreen) |
3317 DPU_FRAMEGEN_FGCCR_CcRed(config->constRed) | DPU_FRAMEGEN_FGCCR_CcAlpha(config->constAlpha);
3318 }
3319
3320 /*!
3321 * brief Start the display.
3322 *
3323 * param base DPU peripheral base address.
3324 * param displayIndex Index of the display.
3325 */
DPU_StartDisplay(IRIS_MVPL_Type * base,uint8_t displayIndex)3326 void DPU_StartDisplay(IRIS_MVPL_Type *base, uint8_t displayIndex)
3327 {
3328 assert(displayIndex < DPU_DISPLAY_COUNT);
3329
3330 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3331
3332 display->FRAMEGEN.FGENABLE = DPU_FRAMEGEN_FGENABLE_FgEn_MASK;
3333 }
3334
3335 /*!
3336 * brief Stop the display.
3337 *
3338 * This function stops the display and wait the sequence complete.
3339 *
3340 * param base DPU peripheral base address.
3341 * param displayIndex Index of the display.
3342 */
DPU_StopDisplay(IRIS_MVPL_Type * base,uint8_t displayIndex)3343 void DPU_StopDisplay(IRIS_MVPL_Type *base, uint8_t displayIndex)
3344 {
3345 assert(displayIndex < DPU_DISPLAY_COUNT);
3346
3347 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3348
3349 display->FRAMEGEN.FGENABLE = 0U;
3350 }
3351
3352 /*!
3353 * brief Clear the FrameGen unit status flags.
3354 *
3355 * param base DPU peripheral base address.
3356 * param displayIndex Display index.
3357 * param interruptIndex Interrupt index, there could be 4 interrupts for each display.
3358 * param intConfig Interrupt mode, could be one of DPU_FRAME_GEN_INT_DISABLE,
3359 * DPU_FRAME_GEN_INT_PER_LINE, and DPU_FRAME_GEN_INT_PER_FRAME.
3360 */
DPU_SetFrameGenInterruptConfig(IRIS_MVPL_Type * base,uint8_t displayIndex,uint8_t interruptIndex,uint32_t intConfig)3361 void DPU_SetFrameGenInterruptConfig(IRIS_MVPL_Type *base,
3362 uint8_t displayIndex,
3363 uint8_t interruptIndex,
3364 uint32_t intConfig)
3365 {
3366 assert(displayIndex < DPU_DISPLAY_COUNT);
3367
3368 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3369
3370 /* Write the intConfig to INT0CONFIG, INT1CONFIG, INT2CONFIG, or INT3CONFIG. */
3371 display->FRAMEGEN.INTCONFIG[interruptIndex] = intConfig;
3372 }
3373
3374 /*!
3375 * brief Trigger the display stream shadow load token.
3376 *
3377 * Trigger the display stream shadow load token, then the shadow register will
3378 * be loaded at the begining of next frame.
3379 *
3380 * param base DPU peripheral base address.
3381 * param displayIndex Display index.
3382 */
DPU_TriggerDisplayShadowLoad(IRIS_MVPL_Type * base,uint8_t displayIndex)3383 void DPU_TriggerDisplayShadowLoad(IRIS_MVPL_Type *base, uint8_t displayIndex)
3384 {
3385 assert(displayIndex < DPU_DISPLAY_COUNT);
3386
3387 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3388
3389 display->FRAMEGEN.FGSLR = DPU_FRAMEGEN_FGSLR_ShdTokGen_MASK;
3390 }
3391
3392 /*!
3393 * brief Get Signature unit default configuration.
3394 *
3395 * The default configuration is:
3396 *
3397 * code
3398 config->errorThreshold = 0U;
3399 config->errorResetThreshold = 8U;
3400 config->panicRed = 0U;
3401 config->panicGreen = 0U;
3402 config->panicBlue = 0U;
3403 config->panicAlpha = 0U;
3404 endcode
3405 * param config Pointer to the configuration.
3406 */
DPU_SignatureGetDefaultConfig(dpu_signature_config_t * config)3407 void DPU_SignatureGetDefaultConfig(dpu_signature_config_t *config)
3408 {
3409 assert(NULL != config);
3410
3411 /* Initializes the configure structure to zero. */
3412 (void)memset(config, 0, sizeof(*config));
3413
3414 config->errorThreshold = 0U;
3415 config->errorResetThreshold = 8U;
3416 config->panicRed = 0U;
3417 config->panicGreen = 0U;
3418 config->panicBlue = 0U;
3419 config->panicAlpha = 0U;
3420 }
3421
3422 /*!
3423 * brief Initialize the Signature unit.
3424 *
3425 * param base DPU peripheral base address.
3426 * param displayIndex Display index.
3427 * param config Pointer to the configuration.
3428 */
DPU_InitSignature(IRIS_MVPL_Type * base,uint8_t displayIndex,const dpu_signature_config_t * config)3429 void DPU_InitSignature(IRIS_MVPL_Type *base, uint8_t displayIndex, const dpu_signature_config_t *config)
3430 {
3431 assert(displayIndex < DPU_DISPLAY_COUNT);
3432 uint32_t panicColor;
3433
3434 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3435
3436 display->SIG.STATICCONTROL =
3437 (((uint32_t)config->errorThreshold) << DPU_SIG_STATICCONTROL_ErrThres_SHIFT) |
3438 (((uint32_t)config->errorResetThreshold) << DPU_SIG_STATICCONTROL_ErrThresReset_SHIFT) |
3439 DPU_SIG_STATICCONTROL_ShdEn_MASK;
3440 panicColor = ((uint32_t)config->panicRed << DPU_SIG_PANICCOLOR_PanicRed_SHIFT) |
3441 ((uint32_t)config->panicGreen << DPU_SIG_PANICCOLOR_PanicGreen_SHIFT) |
3442 ((uint32_t)config->panicBlue << DPU_SIG_PANICCOLOR_PanicBlue_SHIFT);
3443
3444 if (0U != config->panicAlpha)
3445 {
3446 panicColor |= DPU_SIG_PANICCOLOR_PanicAlpha_MASK;
3447 }
3448
3449 display->SIG.PANICCOLOR = panicColor;
3450 display->SIG.CONTINUOUSMODE = DPU_SIG_CONTINUOUSMODE_EnCont_MASK;
3451 }
3452
3453 /*!
3454 * brief Get Signature unit validate window default configuration.
3455 *
3456 * The default configuration is:
3457 *
3458 * code
3459 config->controlFlags = 0U;
3460 config->upperLeftX = 0U;
3461 config->upperLeftY = 0U;
3462 config->lowerRightX = 0U;
3463 config->lowerRightY = 0U;
3464 endcode
3465 *
3466 * param config Pointer to the configuration.
3467 */
DPU_SignatureWindowGetDefaultConfig(dpu_signature_window_config_t * config)3468 void DPU_SignatureWindowGetDefaultConfig(dpu_signature_window_config_t *config)
3469 {
3470 assert(NULL != config);
3471
3472 /* Initializes the configure structure to zero. */
3473 (void)memset(config, 0, sizeof(*config));
3474
3475 config->controlFlags = 0U;
3476 config->upperLeftX = 0U;
3477 config->upperLeftY = 0U;
3478 config->lowerRightX = 0U;
3479 config->lowerRightY = 0U;
3480 }
3481
3482 /*!
3483 * brief Set the Signature unit evaluation window configuration.
3484 *
3485 * param base DPU peripheral base address.
3486 * param displayIndex Display index.
3487 * param windowIndex Evaluation window index, should be 0 to 7.
3488 * param config Pointer to the configuration.
3489 */
DPU_SetSignatureWindowConfig(IRIS_MVPL_Type * base,uint8_t displayIndex,uint8_t windowIndex,const dpu_signature_window_config_t * config)3490 void DPU_SetSignatureWindowConfig(IRIS_MVPL_Type *base,
3491 uint8_t displayIndex,
3492 uint8_t windowIndex,
3493 const dpu_signature_window_config_t *config)
3494 {
3495 assert(windowIndex < DPU_SIG_EAVL_WINDOW_COUNT);
3496
3497 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3498
3499 display->SIG.WINDOW[windowIndex].EVALCONTROL =
3500 (display->SIG.WINDOW[windowIndex].EVALCONTROL &
3501 (DPU_SIG_EVALCONTROL_EnEvalWin_MASK | DPU_SIG_EVALCONTROL_EnCRC_MASK)) |
3502 config->controlFlags;
3503 display->SIG.WINDOW[windowIndex].EVALUPPERLEFT =
3504 ((uint32_t)config->upperLeftX << DPU_SIG_EVALUPPERLEFT_XEvalUpperLeft_SHIFT) |
3505 ((uint32_t)config->upperLeftY << DPU_SIG_EVALUPPERLEFT_YEvalUpperLeft_SHIFT);
3506 display->SIG.WINDOW[windowIndex].EVALLOWERRIGHT =
3507 ((uint32_t)config->lowerRightX << DPU_SIG_EVALLOWERRIGHT_XEvalLowerRight_SHIFT) |
3508 ((uint32_t)config->lowerRightY << DPU_SIG0_EVALLOWERRIGHT_YEvalLowerRight_SHIFT);
3509 }
3510
3511 /*!
3512 * brief Enable or disable the Signature unit evaluation window CRC value computation.
3513 *
3514 * When enabled, a CRC signature is computed for all pixels inside this evaluation window,
3515 * When disabled, the internal status for this window is reset (StsSigError bit and frame counters)
3516 *
3517 * param base DPU peripheral base address.
3518 * param displayIndex Display index.
3519 * param windowIndex Evaluation window index, should be 0 to 7.
3520 * param enable Pass true to enable, false to disable.
3521 */
DPU_EnableSignatureWindowCompute(IRIS_MVPL_Type * base,uint8_t displayIndex,uint8_t windowIndex,bool enable)3522 void DPU_EnableSignatureWindowCompute(IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, bool enable)
3523 {
3524 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3525
3526 if (enable)
3527 {
3528 display->SIG.WINDOW[windowIndex].EVALCONTROL |= DPU_SIG_EVALCONTROL_EnEvalWin_MASK;
3529 }
3530 else
3531 {
3532 display->SIG.WINDOW[windowIndex].EVALCONTROL &= ~DPU_SIG_EVALCONTROL_EnEvalWin_MASK;
3533 }
3534 }
3535
3536 /*!
3537 * brief Enable or disable the Signature unit evaluation window CRC value check.
3538 *
3539 * When enabled, the measured signature is checked against a reference value.
3540 *
3541 * param base DPU peripheral base address.
3542 * param displayIndex Display index.
3543 * param windowIndex Evaluation window index, should be 0 to 7.
3544 * param enable Pass true to enable, false to disable.
3545 */
DPU_EnableSignatureWindowCheck(IRIS_MVPL_Type * base,uint8_t displayIndex,uint8_t windowIndex,bool enable)3546 void DPU_EnableSignatureWindowCheck(IRIS_MVPL_Type *base, uint8_t displayIndex, uint8_t windowIndex, bool enable)
3547 {
3548 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3549
3550 if (enable)
3551 {
3552 display->SIG.WINDOW[windowIndex].EVALCONTROL |= DPU_SIG_EVALCONTROL_EnCRC_MASK;
3553 }
3554 else
3555 {
3556 display->SIG.WINDOW[windowIndex].EVALCONTROL &= ~DPU_SIG_EVALCONTROL_EnCRC_MASK;
3557 }
3558 }
3559
3560 /*!
3561 * brief Set the reference signature value of the evaluation window.
3562 *
3563 * param base DPU peripheral base address.
3564 * param displayIndex Display index.
3565 * param windowIndex Evaluation window index, should be 0 to 7.
3566 * param redCRC Reference signature value of red.
3567 * param greenCRC Referencesignature value of green.
3568 * param blueCRC Reference signature value of blue.
3569 */
DPU_SetSignatureWindowRefCrc(IRIS_MVPL_Type * base,uint8_t displayIndex,uint8_t windowIndex,uint32_t redCRC,uint32_t greenCRC,uint32_t blueCRC)3570 void DPU_SetSignatureWindowRefCrc(IRIS_MVPL_Type *base,
3571 uint8_t displayIndex,
3572 uint8_t windowIndex,
3573 uint32_t redCRC,
3574 uint32_t greenCRC,
3575 uint32_t blueCRC)
3576 {
3577 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3578
3579 display->SIG.WINDOW[windowIndex].SIGCRCREDREF = redCRC;
3580 display->SIG.WINDOW[windowIndex].SIGCRCGREENREF = greenCRC;
3581 display->SIG.WINDOW[windowIndex].SIGCRCBLUEREF = blueCRC;
3582 }
3583
3584 /*!
3585 * brief Get the measured signature value of the evaluation window.
3586 *
3587 * param base DPU peripheral base address.
3588 * param displayIndex Display index.
3589 * param windowIndex Evaluation window index, should be 0 to 7.
3590 * param redCRC Measured signature value of red.
3591 * param greenCRC Measured signature value of green.
3592 * param blueCRC Measured signature value of blue.
3593 */
DPU_GetSignatureWindowCrc(IRIS_MVPL_Type * base,uint8_t displayIndex,uint8_t windowIndex,uint32_t * redCRC,uint32_t * greenCRC,uint32_t * blueCRC)3594 void DPU_GetSignatureWindowCrc(IRIS_MVPL_Type *base,
3595 uint8_t displayIndex,
3596 uint8_t windowIndex,
3597 uint32_t *redCRC,
3598 uint32_t *greenCRC,
3599 uint32_t *blueCRC)
3600 {
3601 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3602
3603 *redCRC = display->SIG.WINDOW[windowIndex].SIGCRCRED;
3604 *greenCRC = display->SIG.WINDOW[windowIndex].SIGCRCGREEN;
3605 *blueCRC = display->SIG.WINDOW[windowIndex].SIGCRCBLUE;
3606 }
3607
3608 /*!
3609 * brief Get the signature unit status.
3610 *
3611 * This function returns the signature unit status. The return value could be
3612 * compared to check the status defined in ref _dpu_signature_status.
3613 * For example:
3614 *
3615 * code
3616 uint32_t status = DPU_GetSignatureStatus(DPU, 0);
3617
3618 if (kDPU_SignatureValid & status)
3619 {
3620 signature measure finished, could read the value.
3621 DPU_GetSignatureWindowCrc(...);
3622 }
3623 endcode
3624 *
3625 * The error flags are also returned as an mask value, upper layer could get specific
3626 * window status by checking the returned bit accordingly. For example,
3627 *
3628 * code
3629 uint32_t status = DPU_GetSignatureStatus(DPU, 0);
3630
3631 if ((1<<3) & status)
3632 {
3633 Window 3 error detected.
3634 }
3635
3636 if ((1<<5) & status)
3637 {
3638 Window 5 error detected.
3639 }
3640
3641 endcode
3642 *
3643 * param base DPU peripheral base address.
3644 * param displayIndex Display index.
3645 * return Mask value of status.
3646 */
DPU_GetSignatureStatus(IRIS_MVPL_Type * base,uint8_t displayIndex)3647 uint32_t DPU_GetSignatureStatus(IRIS_MVPL_Type *base, uint8_t displayIndex)
3648 {
3649 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3650
3651 return display->SIG.STATUS;
3652 }
3653
3654 /*!
3655 * brief Trigger the Signature unit configuration shadow load.
3656 *
3657 * When new configuration set by ref DPU_SetSignatureWindowConfig,
3658 * ref DPU_EnableSignatureWindowCheck, ref DPU_EnableSignatureWindowCompute,
3659 * and ref DPU_SetSignatureWindowRefCrc, use this function to trigger the
3660 * shadow load, then the new configuration takes effect.
3661 *
3662 * Upper layer should monitor the ref kDPU_Group0Sig0ShadowLoadInterrupt or
3663 * ref kDPU_Group1Sig1ShadowLoadInterrupt to wait shadow load finished. New
3664 * configurations should only be set after shadow load finished.
3665 *
3666 * param base DPU peripheral base address.
3667 * param displayIndex Display index.
3668 */
DPU_TriggerSignatureShadowLoad(IRIS_MVPL_Type * base,uint8_t displayIndex)3669 void DPU_TriggerSignatureShadowLoad(IRIS_MVPL_Type *base, uint8_t displayIndex)
3670 {
3671 DPU_DISPLAY_Type *display = (DPU_DISPLAY_Type *)(((uint32_t)base) + s_displayOffsetArray[displayIndex]);
3672
3673 display->SIG.SHADOWLOAD = DPU_SIG_SHADOWLOAD_ShdLdReq_MASK;
3674 }
3675
