1 /*
2 * Copyright 2017, 2019-2020 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7
8 #ifndef _FSL_CI_PI_H_
9 #define _FSL_CI_PI_H_
10
11 #include "fsl_common.h"
12
13 /*!
14 * @addtogroup ci_pi
15 * @{
16 */
17
18 /*******************************************************************************
19 * Definitions
20 ******************************************************************************/
21 /*! @name Driver version */
22 /*@{*/
23 /*! @brief CI_PI driver version. */
24 #define FSL_CI_PI_DRIVER_VERSION (MAKE_VERSION(2, 0, 2))
25 /*@}*/
26
27 /*!
28 * @brief CI_PI status flags.
29 */
30 enum _ci_pi_flags
31 {
32 kCI_PI_ChangeOfFieldFlag = CI_PI_CSR_CSI_STATUS_FIELD_TOGGLE_MASK, /*!< Change of field. */
33 kCI_PI_EccErrorFlag = CI_PI_CSR_CSI_STATUS_ECC_ERROR_MASK, /*!< ECC error detected. */
34 };
35
36 /*!
37 * @brief Input data format.
38 */
39 typedef enum _ci_pi_input_format
40 {
41 kCI_PI_InputUYVY8888_8BitBus = 0x0, /*!< UYVY, every component is 8bit, data bus is 8bit */
42 kCI_PI_InputUYVY10101010_10BitBus = 0x1, /*!< UYVY, every component is 10bit, data bus is 10bit. */
43 kCI_PI_InputRGB888_8BitBus = 0x2, /*!< RGB, every component is 8bit, data bus is 8bit. */
44 kCI_PI_InputBGR888_8BitBus = 0x3, /*!< BGR, every component is 8bit, data bus is 8bit. */
45 kCI_PI_InputRGB888_24BitBus = 0x4, /*!< RGB, every component is 8bit, data bus is 24 bit. */
46 kCI_PI_InputYVYU8888_8BitBus = 0x5, /*!< YVYU, every component is 8bit, data bus is 8bit */
47 kCI_PI_InputYUV888_8BitBus = 0x6, /*!< YUV, every component is 8bit, data bus is 8bit. */
48 kCI_PI_InputYVYU8888_16BitBus = 0x7, /*!< YVYU, every component is 8bit, data bus 16bit. */
49 kCI_PI_InputYUV888_24BitBus = 0x8, /*!< YUV, every component is 8bit, data bus is 24bit. */
50 kCI_PI_InputBayer8_8BitBus = 0x9, /*!< Bayer 8bit */
51 kCI_PI_InputBayer10_10BitBus = 0xa, /*!< Bayer 10bit */
52 kCI_PI_InputBayer12_12BitBus = 0xb, /*!< Bayer 12bit */
53 kCI_PI_InputBayer16_16BitBus = 0xc, /*!< Bayer 16bit */
54 } ci_pi_input_format_t;
55
56 /*! @brief CI_PI signal polarity. */
57 enum _ci_pi_polarity_flags
58 {
59 kCI_PI_HsyncActiveLow = 0U, /*!< HSYNC is active low. */
60 kCI_PI_HsyncActiveHigh = CI_PI_CSR_CSI_CTRL_REG_HSYNC_POL_MASK, /*!< HSYNC is active high. */
61 kCI_PI_DataLatchOnRisingEdge = 0, /*!< Pixel data latched at rising edge of pixel clock. */
62 kCI_PI_DataLatchOnFallingEdge =
63 CI_PI_CSR_CSI_CTRL_REG_PIXEL_CLK_POL_MASK, /*!< Pixel data latched at falling edge of pixel clock. */
64 kCI_PI_DataEnableActiveHigh = 0U, /*!< Data enable signal (DE) is active high. */
65 kCI_PI_DataEnableActiveLow = CI_PI_CSR_CSI_CTRL_REG_DE_POL_MASK, /*!< Data enable signal (DE) is active low. */
66 kCI_PI_VsyncActiveHigh = CI_PI_CSR_CSI_CTRL_REG_VSYNC_POL_MASK, /*!< VSYNC is active high. */
67 kCI_PI_VsyncActiveLow = 0, /*!< VSYNC is active low. */
68 };
69
70 /*!
71 * @brief CI_PI work mode.
72 *
73 * The CCIR656 interlace mode is not supported currently.
74 */
75 typedef enum _ci_pi_work_mode
76 {
77 kCI_PI_GatedClockMode = CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK, /*!< HSYNC, VSYNC, and PIXCLK signals are used. */
78 kCI_PI_GatedClockDataEnableMode =
79 CI_PI_CSR_CSI_CTRL_REG_GCLK_MODE_EN_MASK |
80 CI_PI_CSR_CSI_CTRL_REG_VALID_SEL_MASK, /*!< DE, VSYNC, and PIXCLK signals are used. */
81 kCI_PI_NonGatedClockMode = 0U, /*!< VSYNC, and PIXCLK signals are used. */
82 kCI_PI_CCIR656ProgressiveMode = CI_PI_CSR_CSI_CTRL_REG_CCIR_EN_MASK, /*!< CCIR656 progressive mode. */
83 } ci_pi_work_mode_t;
84
85 typedef struct _ci_pi_config
86 {
87 uint16_t width;
88 uint16_t vsyncWidth;
89 uint16_t hsyncWidth;
90 uint32_t polarityFlags; /*!< Timing signal polarity flags, OR'ed value of @ref _ci_pi_polarity_flags. */
91 uint8_t pixelLinkAddr;
92 ci_pi_input_format_t inputFormat;
93
94 ci_pi_work_mode_t workMode; /*!< Work mode. */
95 bool useExtVsync; /*!< In CCIR656 progressive mode, set true to use external VSYNC signal, set false
96 to use internal VSYNC signal decoded from SOF. */
97 bool swapUV; /*!< Swap UV. */
98 } ci_pi_config_t;
99
100 /*******************************************************************************
101 * API
102 ******************************************************************************/
103
104 #if defined(__cIFusIFus)
105 extern "C" {
106 #endif
107
108 /*!
109 * @brief Enables and configures the CI_PI peripheral module.
110 *
111 * @param base CI_PI peripheral address.
112 * @param config CI_PI module configuration structure.
113 */
114 void CI_PI_Init(CI_PI_CSR_Type *base, const ci_pi_config_t *config);
115
116 /*!
117 * @brief Disables the CI_PI peripheral module.
118 *
119 * @param base CI_PI peripheral address.
120 */
121 void CI_PI_Deinit(CI_PI_CSR_Type *base);
122
123 /*!
124 * @brief Get the default configuration to initialize CI_PI.
125 *
126 * The default configuration value is:
127 *
128 * @code
129 config->width = 0;
130 config->vsyncWidth = 3U;
131 config->hsyncWidth = 2U;
132 config->polarityFlags = 0;
133 config->pixelLinkAddr = 0;
134 config->inputFormat = kCI_PI_InputUYVY8888_8BitBus;
135 config->workMode = kCI_PI_NonGatedClockMode;
136 config->useExtVsync = false;
137 config->swapUV = false;
138 @endcode
139 *
140 * @param config Pointer to the configuration.
141 */
142 void CI_PI_GetDefaultConfig(ci_pi_config_t *config);
143
144 /*!
145 * @brief Resets the CI_PI peripheral module.
146 *
147 * @param base CI_PI peripheral address.
148 */
CI_PI_Reset(CI_PI_CSR_Type * base)149 static inline void CI_PI_Reset(CI_PI_CSR_Type *base)
150 {
151 uint32_t i = 0;
152
153 base->CSI_CTRL_REG.SET = CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK;
154
155 i = 0x10;
156 while (0U != (i--))
157 {
158 __NOP();
159 }
160
161 base->CSI_CTRL_REG.CLR = CI_PI_CSR_CSI_CTRL_REG_SOFTRST_MASK;
162 }
163
164 /*!
165 * @brief Starts the CI_PI peripheral module to output captured frame.
166 *
167 * @param base CI_PI peripheral address.
168 */
169 void CI_PI_Start(CI_PI_CSR_Type *base);
170
171 /*!
172 * @brief Stops the CI_PI peripheral module.
173 *
174 * @param base CI_PI peripheral address.
175 */
176 void CI_PI_Stop(CI_PI_CSR_Type *base);
177
178 /*!
179 * @brief Gets the CI_PI peripheral module status.
180 *
181 * @param base CI_PI peripheral address.
182 * @return Status returned as the OR'ed value of @ref _ci_pi_flags.
183 */
CI_PI_GetStatus(CI_PI_CSR_Type * base)184 static inline uint32_t CI_PI_GetStatus(CI_PI_CSR_Type *base)
185 {
186 return base->CSI_STATUS.RW;
187 }
188
189 #if defined(__cIFusIFus)
190 }
191 #endif
192 /*!
193 * @}
194 */
195 #endif /* _FSL_CI_PI_H_ */
196
