1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2015-09-23 4 ** Build: b210913 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2015-09-23) 20 ** Initial version. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _MKW41Z4_FEATURES_H_ 26 #define _MKW41Z4_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief ADC16 availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ADC16_COUNT (1) 32 /* @brief CMP availability on the SoC. */ 33 #define FSL_FEATURE_SOC_CMP_COUNT (1) 34 /* @brief CMT availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CMT_COUNT (1) 36 /* @brief DAC availability on the SoC. */ 37 #define FSL_FEATURE_SOC_DAC_COUNT (1) 38 /* @brief DCDC availability on the SoC. */ 39 #define FSL_FEATURE_SOC_DCDC_COUNT (1) 40 /* @brief EDMA availability on the SoC. */ 41 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 42 /* @brief DMAMUX availability on the SoC. */ 43 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 44 /* @brief DSPI availability on the SoC. */ 45 #define FSL_FEATURE_SOC_DSPI_COUNT (2) 46 /* @brief FGPIO availability on the SoC. */ 47 #define FSL_FEATURE_SOC_FGPIO_COUNT (3) 48 /* @brief FTFA availability on the SoC. */ 49 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 50 /* @brief GPIO availability on the SoC. */ 51 #define FSL_FEATURE_SOC_GPIO_COUNT (3) 52 /* @brief I2C availability on the SoC. */ 53 #define FSL_FEATURE_SOC_I2C_COUNT (2) 54 /* @brief LLWU availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 56 /* @brief LPTMR availability on the SoC. */ 57 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 58 /* @brief LPUART availability on the SoC. */ 59 #define FSL_FEATURE_SOC_LPUART_COUNT (1) 60 /* @brief LTC availability on the SoC. */ 61 #define FSL_FEATURE_SOC_LTC_COUNT (1) 62 /* @brief MCG availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MCG_COUNT (1) 64 /* @brief MCM availability on the SoC. */ 65 #define FSL_FEATURE_SOC_MCM_COUNT (1) 66 /* @brief MTB availability on the SoC. */ 67 #define FSL_FEATURE_SOC_MTB_COUNT (1) 68 /* @brief MTBDWT availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 70 /* @brief PIT availability on the SoC. */ 71 #define FSL_FEATURE_SOC_PIT_COUNT (1) 72 /* @brief PMC availability on the SoC. */ 73 #define FSL_FEATURE_SOC_PMC_COUNT (1) 74 /* @brief PORT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_PORT_COUNT (3) 76 /* @brief RCM availability on the SoC. */ 77 #define FSL_FEATURE_SOC_RCM_COUNT (1) 78 /* @brief RFSYS availability on the SoC. */ 79 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 80 /* @brief ROM availability on the SoC. */ 81 #define FSL_FEATURE_SOC_ROM_COUNT (1) 82 /* @brief RSIM availability on the SoC. */ 83 #define FSL_FEATURE_SOC_RSIM_COUNT (1) 84 /* @brief RTC availability on the SoC. */ 85 #define FSL_FEATURE_SOC_RTC_COUNT (1) 86 /* @brief SIM availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SIM_COUNT (1) 88 /* @brief SMC availability on the SoC. */ 89 #define FSL_FEATURE_SOC_SMC_COUNT (1) 90 /* @brief TPM availability on the SoC. */ 91 #define FSL_FEATURE_SOC_TPM_COUNT (3) 92 /* @brief TRNG availability on the SoC. */ 93 #define FSL_FEATURE_SOC_TRNG_COUNT (1) 94 /* @brief TSI availability on the SoC. */ 95 #define FSL_FEATURE_SOC_TSI_COUNT (1) 96 /* @brief VREF availability on the SoC. */ 97 #define FSL_FEATURE_SOC_VREF_COUNT (1) 98 /* @brief XCVR availability on the SoC. */ 99 #define FSL_FEATURE_SOC_XCVR_COUNT (1) 100 /* @brief ZLL availability on the SoC. */ 101 #define FSL_FEATURE_SOC_ZLL_COUNT (1) 102 103 /* ADC16 module features */ 104 105 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 106 #define FSL_FEATURE_ADC16_HAS_PGA (0) 107 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 108 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 109 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 110 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 111 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 112 #define FSL_FEATURE_ADC16_HAS_DMA (1) 113 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 114 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 115 /* @brief Has FIFO (bit SC4[AFDEP]). */ 116 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 117 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 118 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 119 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 120 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 121 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 122 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 123 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 124 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 125 /* @brief Has HW averaging (bit SC3[AVGE]). */ 126 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 127 /* @brief Has offset correction (register OFS). */ 128 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 129 /* @brief Maximum ADC resolution. */ 130 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 131 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 132 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 133 134 /* BTLE_RF module features */ 135 136 /* No feature definitions */ 137 138 /* CMP module features */ 139 140 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 141 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 142 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 143 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (0) 144 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 145 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (0) 146 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 147 #define FSL_FEATURE_CMP_HAS_DMA (1) 148 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 149 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 150 /* @brief Has DAC Test function in CMP (register DACTEST). */ 151 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 152 153 /* COP module features */ 154 155 /* @brief Has the COP Debug Enable bit (COPC[COPDBGEN]) */ 156 #define FSL_FEATURE_COP_HAS_DEBUG_ENABLE (1) 157 /* @brief Has the COP Stop mode Enable bit (COPC[COPSTPEN]) */ 158 #define FSL_FEATURE_COP_HAS_STOP_ENABLE (1) 159 /* @brief Has more clock sources like MCGIRC */ 160 #define FSL_FEATURE_COP_HAS_MORE_CLKSRC (1) 161 /* @brief Has the timeout long and short mode bit (COPC[COPCLKS]) */ 162 #define FSL_FEATURE_COP_HAS_LONGTIME_MODE (1) 163 164 /* DAC module features */ 165 166 /* @brief Define the size of hardware buffer */ 167 #define FSL_FEATURE_DAC_BUFFER_SIZE (2) 168 /* @brief Define whether the buffer supports watermark event detection or not. */ 169 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 170 /* @brief Define whether the buffer supports watermark selection detection or not. */ 171 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 172 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 173 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 174 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 175 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 176 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 177 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 178 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 179 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 180 /* @brief Define whether FIFO buffer mode is available or not. */ 181 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 182 /* @brief Define whether swing buffer mode is available or not.. */ 183 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) 184 185 /* DCDC module features */ 186 187 /* @brief Has VDD1P5 bits in DCDC REG3. */ 188 #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P5_BITS (1) 189 /* @brief Has VDD1P45 bits in DCDC REG3. */ 190 #define FSL_FEATURE_DCDC_REG3_HAS_VDD1P45_BITS (0) 191 /* @brief Has BOOST mode: at least one of the bits DCDC_REG1[POSLIMIT_BOOST_IN], DCDC_REG3[DCDC_VDD1P45CTRL_TRG_BOOST] or DCDC_REG3[DCDC_VDD1P5CTRL_TRG_BOOST]. */ 192 #define FSL_FEATURE_DCDC_HAS_BOOST_MODE (1) 193 194 /* EDMA module features */ 195 196 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 197 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (4) 198 /* @brief Total number of DMA channels on all modules. */ 199 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (4) 200 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 201 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 202 /* @brief Has DMA_Error interrupt vector. */ 203 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (0) 204 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 205 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (4) 206 /* @brief Channel IRQ entry shared offset. */ 207 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 208 /* @brief If 8 bytes transfer supported. */ 209 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 210 /* @brief If 16 bytes transfer supported. */ 211 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 212 213 /* DMAMUX module features */ 214 215 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 216 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (4) 217 /* @brief Total number of DMA channels on all modules. */ 218 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (4) 219 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 220 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 221 /* @brief Register CHCFGn width. */ 222 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 223 224 /* FGPIO module features */ 225 226 /* No feature definitions */ 227 228 /* FLASH module features */ 229 230 #if defined(CPU_MKW41Z256VHT4) 231 /* @brief Is of type FTFA. */ 232 #define FSL_FEATURE_FLASH_IS_FTFA (1) 233 /* @brief Is of type FTFE. */ 234 #define FSL_FEATURE_FLASH_IS_FTFE (0) 235 /* @brief Is of type FTFL. */ 236 #define FSL_FEATURE_FLASH_IS_FTFL (0) 237 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 238 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 239 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 240 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 241 /* @brief Has EEPROM region protection (register FEPROT). */ 242 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 243 /* @brief Has data flash region protection (register FDPROT). */ 244 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 245 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 246 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 247 /* @brief Has flash cache control in FMC module. */ 248 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 249 /* @brief Has flash cache control in MCM module. */ 250 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 251 /* @brief Has flash cache control in MSCM module. */ 252 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 253 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 254 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 255 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 256 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 257 /* @brief P-Flash start address. */ 258 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 259 /* @brief P-Flash block count. */ 260 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 261 /* @brief P-Flash block size. */ 262 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 263 /* @brief P-Flash sector size. */ 264 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 265 /* @brief P-Flash write unit size. */ 266 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 267 /* @brief P-Flash data path width. */ 268 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 269 /* @brief P-Flash block swap feature. */ 270 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 271 /* @brief P-Flash protection region count. */ 272 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 273 /* @brief Has FlexNVM memory. */ 274 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 275 /* @brief Has FlexNVM alias. */ 276 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 277 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 278 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 279 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 280 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 281 /* @brief FlexNVM block count. */ 282 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 283 /* @brief FlexNVM block size. */ 284 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 285 /* @brief FlexNVM sector size. */ 286 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 287 /* @brief FlexNVM write unit size. */ 288 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 289 /* @brief FlexNVM data path width. */ 290 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 291 /* @brief Has FlexRAM memory. */ 292 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 293 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 294 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 295 /* @brief FlexRAM size. */ 296 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 297 /* @brief Has 0x00 Read 1s Block command. */ 298 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 299 /* @brief Has 0x01 Read 1s Section command. */ 300 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 301 /* @brief Has 0x02 Program Check command. */ 302 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 303 /* @brief Has 0x03 Read Resource command. */ 304 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 305 /* @brief Has 0x06 Program Longword command. */ 306 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 307 /* @brief Has 0x07 Program Phrase command. */ 308 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 309 /* @brief Has 0x08 Erase Flash Block command. */ 310 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 311 /* @brief Has 0x09 Erase Flash Sector command. */ 312 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 313 /* @brief Has 0x0B Program Section command. */ 314 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 315 /* @brief Has 0x40 Read 1s All Blocks command. */ 316 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 317 /* @brief Has 0x41 Read Once command. */ 318 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 319 /* @brief Has 0x43 Program Once command. */ 320 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 321 /* @brief Has 0x44 Erase All Blocks command. */ 322 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 323 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 324 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 325 /* @brief Has 0x46 Swap Control command. */ 326 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 327 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 328 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 329 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 330 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 331 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 332 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 333 /* @brief Has 0x80 Program Partition command. */ 334 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 335 /* @brief Has 0x81 Set FlexRAM Function command. */ 336 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 337 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 338 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 339 /* @brief P-Flash Erase sector command address alignment. */ 340 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 341 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 342 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 343 /* @brief P-Flash Read resource command address alignment. */ 344 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 345 /* @brief P-Flash Program check command address alignment. */ 346 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 347 /* @brief P-Flash Program check command address alignment. */ 348 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 349 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 350 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 351 /* @brief FlexNVM Erase sector command address alignment. */ 352 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 353 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 354 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 355 /* @brief FlexNVM Read resource command address alignment. */ 356 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 357 /* @brief FlexNVM Program check command address alignment. */ 358 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 359 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 361 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 363 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 365 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 366 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 367 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 368 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 369 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 370 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 371 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 372 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 373 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 374 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 375 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 376 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 377 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 378 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 379 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 381 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 383 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 385 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 387 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 389 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 391 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 393 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 395 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 397 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 398 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 399 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 400 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 401 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 402 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 403 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 404 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 405 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 406 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 407 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 408 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 409 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 410 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 411 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 412 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 413 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 414 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 415 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 416 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 417 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 418 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 419 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 420 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 421 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 422 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 423 #elif defined(CPU_MKW41Z512CAT4) || defined(CPU_MKW41Z512VHT4) 424 /* @brief Is of type FTFA. */ 425 #define FSL_FEATURE_FLASH_IS_FTFA (1) 426 /* @brief Is of type FTFE. */ 427 #define FSL_FEATURE_FLASH_IS_FTFE (0) 428 /* @brief Is of type FTFL. */ 429 #define FSL_FEATURE_FLASH_IS_FTFL (0) 430 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 431 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 432 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 433 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 434 /* @brief Has EEPROM region protection (register FEPROT). */ 435 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 436 /* @brief Has data flash region protection (register FDPROT). */ 437 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 438 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 439 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 440 /* @brief Has flash cache control in FMC module. */ 441 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 442 /* @brief Has flash cache control in MCM module. */ 443 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 444 /* @brief Has flash cache control in MSCM module. */ 445 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 446 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 447 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 448 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 449 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 450 /* @brief P-Flash start address. */ 451 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 452 /* @brief P-Flash block count. */ 453 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 454 /* @brief P-Flash block size. */ 455 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 456 /* @brief P-Flash sector size. */ 457 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 458 /* @brief P-Flash write unit size. */ 459 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 460 /* @brief P-Flash data path width. */ 461 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 462 /* @brief P-Flash block swap feature. */ 463 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 464 /* @brief P-Flash protection region count. */ 465 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 466 /* @brief Has FlexNVM memory. */ 467 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 468 /* @brief Has FlexNVM alias. */ 469 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 470 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 471 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 472 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 473 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 474 /* @brief FlexNVM block count. */ 475 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 476 /* @brief FlexNVM block size. */ 477 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 478 /* @brief FlexNVM sector size. */ 479 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 480 /* @brief FlexNVM write unit size. */ 481 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 482 /* @brief FlexNVM data path width. */ 483 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 484 /* @brief Has FlexRAM memory. */ 485 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 486 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 487 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 488 /* @brief FlexRAM size. */ 489 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 490 /* @brief Has 0x00 Read 1s Block command. */ 491 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 492 /* @brief Has 0x01 Read 1s Section command. */ 493 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 494 /* @brief Has 0x02 Program Check command. */ 495 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 496 /* @brief Has 0x03 Read Resource command. */ 497 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 498 /* @brief Has 0x06 Program Longword command. */ 499 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 500 /* @brief Has 0x07 Program Phrase command. */ 501 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 502 /* @brief Has 0x08 Erase Flash Block command. */ 503 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 504 /* @brief Has 0x09 Erase Flash Sector command. */ 505 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 506 /* @brief Has 0x0B Program Section command. */ 507 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 508 /* @brief Has 0x40 Read 1s All Blocks command. */ 509 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 510 /* @brief Has 0x41 Read Once command. */ 511 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 512 /* @brief Has 0x43 Program Once command. */ 513 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 514 /* @brief Has 0x44 Erase All Blocks command. */ 515 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 516 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 517 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 518 /* @brief Has 0x46 Swap Control command. */ 519 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 520 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 521 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 522 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 523 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 524 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 525 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 526 /* @brief Has 0x80 Program Partition command. */ 527 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 528 /* @brief Has 0x81 Set FlexRAM Function command. */ 529 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 530 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 531 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 532 /* @brief P-Flash Erase sector command address alignment. */ 533 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 534 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 535 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 536 /* @brief P-Flash Read resource command address alignment. */ 537 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 538 /* @brief P-Flash Program check command address alignment. */ 539 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 540 /* @brief P-Flash Program check command address alignment. */ 541 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 542 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 543 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 544 /* @brief FlexNVM Erase sector command address alignment. */ 545 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 546 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 547 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 548 /* @brief FlexNVM Read resource command address alignment. */ 549 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 550 /* @brief FlexNVM Program check command address alignment. */ 551 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 552 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 553 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 554 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 555 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 556 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 558 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 560 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 562 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 563 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 564 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 565 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 566 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 567 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 568 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 569 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 570 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 571 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 572 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 573 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 574 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 575 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 576 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 577 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 578 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 579 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 580 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 581 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 582 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 583 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 584 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 585 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 586 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 587 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 588 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 590 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 592 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 594 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 595 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 596 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 597 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 598 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 599 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 600 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 601 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 602 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 603 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 604 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 605 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 606 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 607 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 608 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 609 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 610 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 611 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 612 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 613 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 614 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 615 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 616 #endif /* defined(CPU_MKW41Z256VHT4) */ 617 618 /* GENFSK module features */ 619 620 /* No feature definitions */ 621 622 /* GPIO module features */ 623 624 /* @brief Has GPIO attribute checker register (GACR). */ 625 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 626 627 /* I2C module features */ 628 629 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 630 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 631 /* @brief Maximum supported baud rate in kilobit per second. */ 632 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 633 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 634 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 635 /* @brief Has DMA support (register bit C1[DMAEN]). */ 636 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 637 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 638 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 639 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 640 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 641 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 642 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 643 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 644 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 645 /* @brief Has control of the drive capability of the I2C pins. */ 646 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 647 /* @brief Has double buffering support (register S2). */ 648 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (1) 649 /* @brief Has double buffer enable. */ 650 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (1) 651 652 /* LLWU module features */ 653 654 #if defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) 655 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 656 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 657 /* @brief Has pins 8-15 connected to LLWU device. */ 658 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 659 /* @brief Maximum number of internal modules connected to LLWU device. */ 660 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 661 /* @brief Number of digital filters. */ 662 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 663 /* @brief Has MF register. */ 664 #define FSL_FEATURE_LLWU_HAS_MF (0) 665 /* @brief Has PF register. */ 666 #define FSL_FEATURE_LLWU_HAS_PF (0) 667 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 668 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 669 /* @brief Has no internal module wakeup flag register. */ 670 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 671 /* @brief Has external pin 0 connected to LLWU device. */ 672 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 673 /* @brief Index of port of external pin. */ 674 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) 675 /* @brief Number of external pin port on specified port. */ 676 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) 677 /* @brief Has external pin 1 connected to LLWU device. */ 678 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 679 /* @brief Index of port of external pin. */ 680 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) 681 /* @brief Number of external pin port on specified port. */ 682 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) 683 /* @brief Has external pin 2 connected to LLWU device. */ 684 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 685 /* @brief Index of port of external pin. */ 686 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) 687 /* @brief Number of external pin port on specified port. */ 688 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) 689 /* @brief Has external pin 3 connected to LLWU device. */ 690 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 691 /* @brief Index of port of external pin. */ 692 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) 693 /* @brief Number of external pin port on specified port. */ 694 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) 695 /* @brief Has external pin 4 connected to LLWU device. */ 696 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 697 /* @brief Index of port of external pin. */ 698 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 699 /* @brief Number of external pin port on specified port. */ 700 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) 701 /* @brief Has external pin 5 connected to LLWU device. */ 702 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 703 /* @brief Index of port of external pin. */ 704 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) 705 /* @brief Number of external pin port on specified port. */ 706 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) 707 /* @brief Has external pin 6 connected to LLWU device. */ 708 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 709 /* @brief Index of port of external pin. */ 710 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) 711 /* @brief Number of external pin port on specified port. */ 712 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) 713 /* @brief Has external pin 7 connected to LLWU device. */ 714 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 715 /* @brief Index of port of external pin. */ 716 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) 717 /* @brief Number of external pin port on specified port. */ 718 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) 719 /* @brief Has external pin 8 connected to LLWU device. */ 720 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 721 /* @brief Index of port of external pin. */ 722 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) 723 /* @brief Number of external pin port on specified port. */ 724 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) 725 /* @brief Has external pin 9 connected to LLWU device. */ 726 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (0) 727 /* @brief Index of port of external pin. */ 728 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (0) 729 /* @brief Number of external pin port on specified port. */ 730 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) 731 /* @brief Has external pin 10 connected to LLWU device. */ 732 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 733 /* @brief Index of port of external pin. */ 734 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 735 /* @brief Number of external pin port on specified port. */ 736 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) 737 /* @brief Has external pin 11 connected to LLWU device. */ 738 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 739 /* @brief Index of port of external pin. */ 740 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 741 /* @brief Number of external pin port on specified port. */ 742 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) 743 /* @brief Has external pin 12 connected to LLWU device. */ 744 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 745 /* @brief Index of port of external pin. */ 746 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) 747 /* @brief Number of external pin port on specified port. */ 748 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) 749 /* @brief Has external pin 13 connected to LLWU device. */ 750 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 751 /* @brief Index of port of external pin. */ 752 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) 753 /* @brief Number of external pin port on specified port. */ 754 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) 755 /* @brief Has external pin 14 connected to LLWU device. */ 756 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 757 /* @brief Index of port of external pin. */ 758 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) 759 /* @brief Number of external pin port on specified port. */ 760 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) 761 /* @brief Has external pin 15 connected to LLWU device. */ 762 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 763 /* @brief Index of port of external pin. */ 764 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) 765 /* @brief Number of external pin port on specified port. */ 766 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) 767 /* @brief Has external pin 16 connected to LLWU device. */ 768 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 769 /* @brief Index of port of external pin. */ 770 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 771 /* @brief Number of external pin port on specified port. */ 772 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 773 /* @brief Has external pin 17 connected to LLWU device. */ 774 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 775 /* @brief Index of port of external pin. */ 776 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 777 /* @brief Number of external pin port on specified port. */ 778 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 779 /* @brief Has external pin 18 connected to LLWU device. */ 780 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 781 /* @brief Index of port of external pin. */ 782 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 783 /* @brief Number of external pin port on specified port. */ 784 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 785 /* @brief Has external pin 19 connected to LLWU device. */ 786 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 787 /* @brief Index of port of external pin. */ 788 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 789 /* @brief Number of external pin port on specified port. */ 790 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 791 /* @brief Has external pin 20 connected to LLWU device. */ 792 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 793 /* @brief Index of port of external pin. */ 794 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 795 /* @brief Number of external pin port on specified port. */ 796 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 797 /* @brief Has external pin 21 connected to LLWU device. */ 798 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 799 /* @brief Index of port of external pin. */ 800 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 801 /* @brief Number of external pin port on specified port. */ 802 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 803 /* @brief Has external pin 22 connected to LLWU device. */ 804 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 805 /* @brief Index of port of external pin. */ 806 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 807 /* @brief Number of external pin port on specified port. */ 808 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 809 /* @brief Has external pin 23 connected to LLWU device. */ 810 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 811 /* @brief Index of port of external pin. */ 812 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 813 /* @brief Number of external pin port on specified port. */ 814 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 815 /* @brief Has external pin 24 connected to LLWU device. */ 816 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 817 /* @brief Index of port of external pin. */ 818 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 819 /* @brief Number of external pin port on specified port. */ 820 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 821 /* @brief Has external pin 25 connected to LLWU device. */ 822 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 823 /* @brief Index of port of external pin. */ 824 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 825 /* @brief Number of external pin port on specified port. */ 826 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 827 /* @brief Has external pin 26 connected to LLWU device. */ 828 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 829 /* @brief Index of port of external pin. */ 830 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 831 /* @brief Number of external pin port on specified port. */ 832 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 833 /* @brief Has external pin 27 connected to LLWU device. */ 834 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 835 /* @brief Index of port of external pin. */ 836 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 837 /* @brief Number of external pin port on specified port. */ 838 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 839 /* @brief Has external pin 28 connected to LLWU device. */ 840 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 841 /* @brief Index of port of external pin. */ 842 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 843 /* @brief Number of external pin port on specified port. */ 844 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 845 /* @brief Has external pin 29 connected to LLWU device. */ 846 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 847 /* @brief Index of port of external pin. */ 848 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 849 /* @brief Number of external pin port on specified port. */ 850 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 851 /* @brief Has external pin 30 connected to LLWU device. */ 852 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 853 /* @brief Index of port of external pin. */ 854 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 855 /* @brief Number of external pin port on specified port. */ 856 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 857 /* @brief Has external pin 31 connected to LLWU device. */ 858 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 859 /* @brief Index of port of external pin. */ 860 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 861 /* @brief Number of external pin port on specified port. */ 862 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 863 /* @brief Has internal module 0 connected to LLWU device. */ 864 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 865 /* @brief Has internal module 1 connected to LLWU device. */ 866 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 867 /* @brief Has internal module 2 connected to LLWU device. */ 868 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 869 /* @brief Has internal module 3 connected to LLWU device. */ 870 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 871 /* @brief Has internal module 4 connected to LLWU device. */ 872 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 873 /* @brief Has internal module 5 connected to LLWU device. */ 874 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 875 /* @brief Has internal module 6 connected to LLWU device. */ 876 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 877 /* @brief Has internal module 7 connected to LLWU device. */ 878 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 879 /* @brief Has Version ID Register (LLWU_VERID). */ 880 #define FSL_FEATURE_LLWU_HAS_VERID (0) 881 /* @brief Has Parameter Register (LLWU_PARAM). */ 882 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 883 /* @brief Width of registers of the LLWU. */ 884 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 885 /* @brief Has DMA Enable register (LLWU_DE). */ 886 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 887 #elif defined(CPU_MKW41Z512CAT4) 888 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 889 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 890 /* @brief Has pins 8-15 connected to LLWU device. */ 891 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 892 /* @brief Maximum number of internal modules connected to LLWU device. */ 893 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 894 /* @brief Number of digital filters. */ 895 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 896 /* @brief Has MF register. */ 897 #define FSL_FEATURE_LLWU_HAS_MF (0) 898 /* @brief Has PF register. */ 899 #define FSL_FEATURE_LLWU_HAS_PF (0) 900 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 901 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 902 /* @brief Has no internal module wakeup flag register. */ 903 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 904 /* @brief Has external pin 0 connected to LLWU device. */ 905 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 906 /* @brief Index of port of external pin. */ 907 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOC_IDX) 908 /* @brief Number of external pin port on specified port. */ 909 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (16) 910 /* @brief Has external pin 1 connected to LLWU device. */ 911 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 912 /* @brief Index of port of external pin. */ 913 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOC_IDX) 914 /* @brief Number of external pin port on specified port. */ 915 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (17) 916 /* @brief Has external pin 2 connected to LLWU device. */ 917 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 918 /* @brief Index of port of external pin. */ 919 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOC_IDX) 920 /* @brief Number of external pin port on specified port. */ 921 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (18) 922 /* @brief Has external pin 3 connected to LLWU device. */ 923 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 924 /* @brief Index of port of external pin. */ 925 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOC_IDX) 926 /* @brief Number of external pin port on specified port. */ 927 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (19) 928 /* @brief Has external pin 4 connected to LLWU device. */ 929 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 930 /* @brief Index of port of external pin. */ 931 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 932 /* @brief Number of external pin port on specified port. */ 933 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (16) 934 /* @brief Has external pin 5 connected to LLWU device. */ 935 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 936 /* @brief Index of port of external pin. */ 937 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOA_IDX) 938 /* @brief Number of external pin port on specified port. */ 939 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (17) 940 /* @brief Has external pin 6 connected to LLWU device. */ 941 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 942 /* @brief Index of port of external pin. */ 943 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOA_IDX) 944 /* @brief Number of external pin port on specified port. */ 945 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (18) 946 /* @brief Has external pin 7 connected to LLWU device. */ 947 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 948 /* @brief Index of port of external pin. */ 949 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOA_IDX) 950 /* @brief Number of external pin port on specified port. */ 951 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (19) 952 /* @brief Has external pin 8 connected to LLWU device. */ 953 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 954 /* @brief Index of port of external pin. */ 955 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOB_IDX) 956 /* @brief Number of external pin port on specified port. */ 957 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (0) 958 /* @brief Has external pin 9 connected to LLWU device. */ 959 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 960 /* @brief Index of port of external pin. */ 961 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 962 /* @brief Number of external pin port on specified port. */ 963 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (0) 964 /* @brief Has external pin 10 connected to LLWU device. */ 965 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 966 /* @brief Index of port of external pin. */ 967 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 968 /* @brief Number of external pin port on specified port. */ 969 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (2) 970 /* @brief Has external pin 11 connected to LLWU device. */ 971 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 972 /* @brief Index of port of external pin. */ 973 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 974 /* @brief Number of external pin port on specified port. */ 975 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (3) 976 /* @brief Has external pin 12 connected to LLWU device. */ 977 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 978 /* @brief Index of port of external pin. */ 979 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOC_IDX) 980 /* @brief Number of external pin port on specified port. */ 981 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (4) 982 /* @brief Has external pin 13 connected to LLWU device. */ 983 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 984 /* @brief Index of port of external pin. */ 985 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOC_IDX) 986 /* @brief Number of external pin port on specified port. */ 987 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (5) 988 /* @brief Has external pin 14 connected to LLWU device. */ 989 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 990 /* @brief Index of port of external pin. */ 991 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOC_IDX) 992 /* @brief Number of external pin port on specified port. */ 993 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (6) 994 /* @brief Has external pin 15 connected to LLWU device. */ 995 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 996 /* @brief Index of port of external pin. */ 997 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOC_IDX) 998 /* @brief Number of external pin port on specified port. */ 999 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (7) 1000 /* @brief Has external pin 16 connected to LLWU device. */ 1001 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1002 /* @brief Index of port of external pin. */ 1003 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1004 /* @brief Number of external pin port on specified port. */ 1005 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1006 /* @brief Has external pin 17 connected to LLWU device. */ 1007 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1008 /* @brief Index of port of external pin. */ 1009 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1010 /* @brief Number of external pin port on specified port. */ 1011 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1012 /* @brief Has external pin 18 connected to LLWU device. */ 1013 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1014 /* @brief Index of port of external pin. */ 1015 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1016 /* @brief Number of external pin port on specified port. */ 1017 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1018 /* @brief Has external pin 19 connected to LLWU device. */ 1019 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 1020 /* @brief Index of port of external pin. */ 1021 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 1022 /* @brief Number of external pin port on specified port. */ 1023 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 1024 /* @brief Has external pin 20 connected to LLWU device. */ 1025 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 1026 /* @brief Index of port of external pin. */ 1027 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 1028 /* @brief Number of external pin port on specified port. */ 1029 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 1030 /* @brief Has external pin 21 connected to LLWU device. */ 1031 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 1032 /* @brief Index of port of external pin. */ 1033 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 1034 /* @brief Number of external pin port on specified port. */ 1035 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 1036 /* @brief Has external pin 22 connected to LLWU device. */ 1037 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1038 /* @brief Index of port of external pin. */ 1039 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1040 /* @brief Number of external pin port on specified port. */ 1041 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1042 /* @brief Has external pin 23 connected to LLWU device. */ 1043 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1044 /* @brief Index of port of external pin. */ 1045 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1046 /* @brief Number of external pin port on specified port. */ 1047 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1048 /* @brief Has external pin 24 connected to LLWU device. */ 1049 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1050 /* @brief Index of port of external pin. */ 1051 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1052 /* @brief Number of external pin port on specified port. */ 1053 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1054 /* @brief Has external pin 25 connected to LLWU device. */ 1055 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1056 /* @brief Index of port of external pin. */ 1057 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1058 /* @brief Number of external pin port on specified port. */ 1059 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1060 /* @brief Has external pin 26 connected to LLWU device. */ 1061 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1062 /* @brief Index of port of external pin. */ 1063 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1064 /* @brief Number of external pin port on specified port. */ 1065 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1066 /* @brief Has external pin 27 connected to LLWU device. */ 1067 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1068 /* @brief Index of port of external pin. */ 1069 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1070 /* @brief Number of external pin port on specified port. */ 1071 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1072 /* @brief Has external pin 28 connected to LLWU device. */ 1073 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1074 /* @brief Index of port of external pin. */ 1075 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1076 /* @brief Number of external pin port on specified port. */ 1077 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1078 /* @brief Has external pin 29 connected to LLWU device. */ 1079 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1080 /* @brief Index of port of external pin. */ 1081 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1082 /* @brief Number of external pin port on specified port. */ 1083 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1084 /* @brief Has external pin 30 connected to LLWU device. */ 1085 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1086 /* @brief Index of port of external pin. */ 1087 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1088 /* @brief Number of external pin port on specified port. */ 1089 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1090 /* @brief Has external pin 31 connected to LLWU device. */ 1091 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1092 /* @brief Index of port of external pin. */ 1093 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1094 /* @brief Number of external pin port on specified port. */ 1095 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1096 /* @brief Has internal module 0 connected to LLWU device. */ 1097 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1098 /* @brief Has internal module 1 connected to LLWU device. */ 1099 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1100 /* @brief Has internal module 2 connected to LLWU device. */ 1101 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1102 /* @brief Has internal module 3 connected to LLWU device. */ 1103 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1104 /* @brief Has internal module 4 connected to LLWU device. */ 1105 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 1106 /* @brief Has internal module 5 connected to LLWU device. */ 1107 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1108 /* @brief Has internal module 6 connected to LLWU device. */ 1109 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1110 /* @brief Has internal module 7 connected to LLWU device. */ 1111 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1112 /* @brief Has Version ID Register (LLWU_VERID). */ 1113 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1114 /* @brief Has Parameter Register (LLWU_PARAM). */ 1115 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1116 /* @brief Width of registers of the LLWU. */ 1117 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1118 /* @brief Has DMA Enable register (LLWU_DE). */ 1119 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1120 #endif /* defined(CPU_MKW41Z256VHT4) || defined(CPU_MKW41Z512VHT4) */ 1121 1122 /* LPTMR module features */ 1123 1124 /* @brief Has shared interrupt handler with another LPTMR module. */ 1125 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1126 /* @brief Whether LPTMR counter is 32 bits width. */ 1127 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1128 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1129 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1130 1131 /* LPUART module features */ 1132 1133 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 1134 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 1135 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1136 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 1137 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1138 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 1139 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1140 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1141 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1142 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 1143 /* @brief Has 32-bit register MODIR */ 1144 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 1145 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1146 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 1147 /* @brief Infrared (modulation) is supported. */ 1148 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 1149 /* @brief 2 bits long stop bit is available. */ 1150 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1151 /* @brief If 10-bit mode is supported. */ 1152 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 1153 /* @brief If 7-bit mode is supported. */ 1154 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 1155 /* @brief Baud rate fine adjustment is available. */ 1156 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 1157 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1158 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 1159 /* @brief Baud rate oversampling is available. */ 1160 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 1161 /* @brief Baud rate oversampling is available. */ 1162 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 1163 /* @brief Peripheral type. */ 1164 #define FSL_FEATURE_LPUART_IS_SCI (1) 1165 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1166 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 1167 /* @brief Supports two match addresses to filter incoming frames. */ 1168 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 1169 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1170 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 1171 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1172 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 1173 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1174 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 1175 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1176 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 1177 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1178 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1179 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1180 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1181 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1182 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1183 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1184 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1185 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1186 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1187 /* @brief Has separate DMA RX and TX requests. */ 1188 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1189 /* @brief Has separate RX and TX interrupts. */ 1190 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1191 /* @brief Has LPAURT_PARAM. */ 1192 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 1193 /* @brief Has LPUART_VERID. */ 1194 #define FSL_FEATURE_LPUART_HAS_VERID (0) 1195 /* @brief Has LPUART_GLOBAL. */ 1196 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 1197 /* @brief Has LPUART_PINCFG. */ 1198 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 1199 1200 /* LTC module features */ 1201 1202 /* @brief LTC module supports DES algorithm. */ 1203 #define FSL_FEATURE_LTC_HAS_DES (0) 1204 /* @brief LTC module supports PKHA algorithm. */ 1205 #define FSL_FEATURE_LTC_HAS_PKHA (0) 1206 /* @brief LTC module supports SHA algorithm. */ 1207 #define FSL_FEATURE_LTC_HAS_SHA (0) 1208 /* @brief LTC module supports AES GCM mode. */ 1209 #define FSL_FEATURE_LTC_HAS_GCM (0) 1210 /* @brief LTC module supports DPAMS registers. */ 1211 #define FSL_FEATURE_LTC_HAS_DPAMS (0) 1212 /* @brief LTC module supports AES with 24 bytes key. */ 1213 #define FSL_FEATURE_LTC_HAS_AES192 (0) 1214 /* @brief LTC module supports AES with 32 bytes key. */ 1215 #define FSL_FEATURE_LTC_HAS_AES256 (0) 1216 1217 /* MCG module features */ 1218 1219 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1220 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) 1221 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1222 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) 1223 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1224 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) 1225 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1226 #define FSL_FEATURE_MCG_PLL_REF_MIN (0) 1227 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1228 #define FSL_FEATURE_MCG_PLL_REF_MAX (0) 1229 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1230 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1231 /* @brief FRDIV supports 1280. */ 1232 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1233 /* @brief FRDIV supports 1536. */ 1234 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1235 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1236 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1237 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1238 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 1239 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1240 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1241 /* @brief Has 48MHz internal oscillator. */ 1242 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1243 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1244 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1245 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1246 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1247 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1248 #define FSL_FEATURE_MCG_HAS_LOLRE (0) 1249 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1250 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1251 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1252 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1253 /* @brief TBD */ 1254 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1255 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1256 #define FSL_FEATURE_MCG_HAS_PLL (0) 1257 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1258 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (0) 1259 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1260 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (0) 1261 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1262 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1263 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1264 #define FSL_FEATURE_MCG_HAS_FLL (1) 1265 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1266 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1267 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1268 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1269 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1270 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) 1271 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1272 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1273 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1274 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1275 /* @brief Has external clock monitor (register bit C6[CME]). */ 1276 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1277 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1278 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1279 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1280 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1281 /* @brief Has PEI mode or PBI mode. */ 1282 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1283 /* @brief Reset clock mode is BLPI. */ 1284 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1285 1286 /* interrupt module features */ 1287 1288 /* @brief Lowest interrupt request number. */ 1289 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1290 /* @brief Highest interrupt request number. */ 1291 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 1292 1293 /* PIT module features */ 1294 1295 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1296 #define FSL_FEATURE_PIT_TIMER_COUNT (2) 1297 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1298 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1299 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1300 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1301 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1302 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (1) 1303 /* @brief Has timer enable control. */ 1304 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1305 1306 /* PMC module features */ 1307 1308 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1309 #define FSL_FEATURE_PMC_HAS_BGEN (0) 1310 /* @brief Has Bandgap Buffer Enable. */ 1311 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1312 /* @brief Has Bandgap Buffer Drive Select. */ 1313 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1314 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1315 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1316 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1317 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1318 /* @brief Has LPO. */ 1319 #define FSL_FEATURE_PMC_HAS_LPO (0) 1320 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1321 #define FSL_FEATURE_PMC_HAS_VLPO (1) 1322 /* @brief Has acknowledge isolation support. */ 1323 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1324 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1325 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1326 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1327 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1328 /* @brief Has PMC_HVDSC1. */ 1329 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1330 /* @brief Has PMC_PARAM. */ 1331 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1332 /* @brief Has PMC_VERID. */ 1333 #define FSL_FEATURE_PMC_HAS_VERID (0) 1334 1335 /* PORT module features */ 1336 1337 /* @brief Has control lock (register bit PCR[LK]). */ 1338 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 1339 /* @brief Has open drain control (register bit PCR[ODE]). */ 1340 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 1341 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1342 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 1343 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1344 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1345 /* @brief Has pull resistor selection available. */ 1346 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1347 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1348 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1349 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1350 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1351 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1352 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1353 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1354 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1355 /* @brief Has separate drive strength register (HDRVE). */ 1356 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1357 /* @brief Has glitch filter (register IOFLT). */ 1358 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1359 /* @brief Defines width of PCR[MUX] field. */ 1360 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1361 /* @brief Has dedicated interrupt vector. */ 1362 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1363 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1364 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1365 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1366 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1367 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1368 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1369 1370 /* RADIO module features */ 1371 1372 /* @brief Zigbee availability. */ 1373 #define FSL_FEATURE_RADIO_HAS_ZIGBEE (1) 1374 /* @brief Bluetooth availability. */ 1375 #define FSL_FEATURE_RADIO_HAS_BLE (1) 1376 /* @brief ANT availability */ 1377 #define FSL_FEATURE_RADIO_HAS_ANT (1) 1378 /* @brief Generic FSK module availability */ 1379 #define FSL_FEATURE_RADIO_HAS_GENFSK (1) 1380 /* @brief Major version of the radio submodule */ 1381 #define FSL_FEATURE_RADIO_VERSION_MAJOR (2) 1382 /* @brief Minor version of the radio submodule */ 1383 #define FSL_FEATURE_RADIO_VERSION_MINOR (0) 1384 1385 /* RCM module features */ 1386 1387 /* @brief Has Loss-of-Lock Reset support. */ 1388 #define FSL_FEATURE_RCM_HAS_LOL (0) 1389 /* @brief Has Loss-of-Clock Reset support. */ 1390 #define FSL_FEATURE_RCM_HAS_LOC (1) 1391 /* @brief Has JTAG generated Reset support. */ 1392 #define FSL_FEATURE_RCM_HAS_JTAG (0) 1393 /* @brief Has EzPort generated Reset support. */ 1394 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1395 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1396 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1397 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1398 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1399 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1400 #define FSL_FEATURE_RCM_HAS_SSRS (0) 1401 /* @brief Has Version ID Register (RCM_VERID). */ 1402 #define FSL_FEATURE_RCM_HAS_VERID (0) 1403 /* @brief Has Parameter Register (RCM_PARAM). */ 1404 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1405 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1406 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1407 /* @brief Width of registers of the RCM. */ 1408 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1409 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1410 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1411 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1412 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1413 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1414 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1415 1416 /* RSIM module features */ 1417 1418 /* No feature definitions */ 1419 1420 /* RTC module features */ 1421 1422 /* @brief Has wakeup pin. */ 1423 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1424 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1425 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1426 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1427 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1428 /* @brief Has read/write access control (registers WAR and RAR). */ 1429 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (0) 1430 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1431 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 1432 /* @brief Has RTC_CLKIN available. */ 1433 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1434 /* @brief Has prescaler adjust for LPO. */ 1435 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1436 /* @brief Has Clock Pin Enable field. */ 1437 #define FSL_FEATURE_RTC_HAS_CPE (0) 1438 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1439 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1440 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1441 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1442 /* @brief Has Tamper Interrupt Register (register TIR). */ 1443 #define FSL_FEATURE_RTC_HAS_TIR (0) 1444 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1445 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1446 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1447 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1448 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1449 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1450 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1451 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1452 /* @brief Has Tamper Detect Register (register TDR). */ 1453 #define FSL_FEATURE_RTC_HAS_TDR (0) 1454 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1455 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1456 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1457 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1458 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1459 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1460 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1461 #define FSL_FEATURE_RTC_HAS_TTSR (0) 1462 /* @brief Has Pin Configuration Register (register PCR). */ 1463 #define FSL_FEATURE_RTC_HAS_PCR (0) 1464 1465 /* SIM module features */ 1466 1467 /* @brief Has USB FS divider. */ 1468 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1469 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1470 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1471 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1472 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1473 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1474 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (1) 1475 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1476 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1477 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1478 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1479 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1480 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1481 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1482 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1483 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1484 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1485 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1486 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1487 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1488 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1489 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1490 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1491 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1492 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1493 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1494 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1495 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1496 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) 1497 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1498 #define FSL_FEATURE_SIM_OPT_UART_COUNT (0) 1499 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1500 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1501 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1502 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1503 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1504 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1505 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1506 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (1) 1507 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1508 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1509 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1510 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1511 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1512 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) 1513 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1514 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1515 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1516 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1517 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1518 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1519 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1520 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (0) 1521 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1522 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (0) 1523 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1524 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (0) 1525 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1526 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (0) 1527 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1528 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (0) 1529 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1530 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (0) 1531 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1532 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (0) 1533 /* @brief Has FTM module(s) configuration. */ 1534 #define FSL_FEATURE_SIM_OPT_HAS_FTM (0) 1535 /* @brief Number of FTM modules. */ 1536 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (0) 1537 /* @brief Number of FTM triggers with selectable source. */ 1538 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (0) 1539 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1540 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (0) 1541 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1542 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1543 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1544 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (0) 1545 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1546 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (0) 1547 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1548 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1549 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1550 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1551 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1552 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (0) 1553 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1554 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (0) 1555 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1556 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (0) 1557 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1558 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1559 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1560 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1561 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1562 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1563 /* @brief Has TPM module(s) configuration. */ 1564 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1565 /* @brief The highest TPM module index. */ 1566 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1567 /* @brief Has TPM module with index 0. */ 1568 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (1) 1569 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1570 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (1) 1571 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1572 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (1) 1573 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1574 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1575 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1576 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (1) 1577 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1578 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) 1579 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1580 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (1) 1581 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1582 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (1) 1583 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1584 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1585 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1586 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1587 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1588 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1589 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1590 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1591 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1592 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1593 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1594 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1595 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1596 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1597 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1598 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1599 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1600 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1601 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1602 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1603 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1604 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1605 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1606 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1607 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1608 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (1) 1609 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1610 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1611 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1612 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1613 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1614 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1615 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1616 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1617 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1618 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1619 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1620 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (1) 1621 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1622 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1623 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1624 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (0) 1625 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1626 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1627 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1628 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1629 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1630 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1631 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1632 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1633 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1634 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1635 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1636 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1637 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1638 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1639 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1640 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1641 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1642 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1643 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1644 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1645 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1646 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1647 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1648 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 1649 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1650 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1651 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1652 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1653 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1654 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1655 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1656 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1657 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1658 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1659 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1660 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1661 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1662 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1663 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1664 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1665 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1666 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1667 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1668 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1669 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1670 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1671 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1672 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1673 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1674 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1675 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1676 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1677 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1678 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1679 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1680 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1681 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1682 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1683 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1684 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) 1685 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1686 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1687 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1688 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1689 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1690 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1691 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1692 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1693 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1694 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1695 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1696 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1697 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1698 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) 1699 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1700 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) 1701 /* @brief Has miscellanious control register (register MCR). */ 1702 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1703 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1704 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (1) 1705 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1706 #define FSL_FEATURE_SIM_HAS_COP_STOP (1) 1707 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1708 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1709 /* @brief Has UIDH registers. */ 1710 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1711 /* @brief Has UIDM registers. */ 1712 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1713 1714 /* SMC module features */ 1715 1716 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1717 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1718 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1719 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1720 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1721 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1722 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1723 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1724 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1725 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1726 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1727 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1728 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1729 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1730 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1731 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) 1732 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1733 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1734 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1735 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1736 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1737 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1738 /* @brief Has stop submode. */ 1739 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1740 /* @brief Has stop submode 0(VLLS0). */ 1741 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1742 /* @brief Has stop submode 1(VLLS1). */ 1743 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1744 /* @brief Has stop submode 2(VLLS2). */ 1745 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1746 /* @brief Has SMC_PARAM. */ 1747 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1748 /* @brief Has SMC_VERID. */ 1749 #define FSL_FEATURE_SMC_HAS_VERID (0) 1750 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1751 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1752 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1753 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1754 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1755 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1756 /* @brief Width of SMC registers. */ 1757 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1758 1759 /* DSPI module features */ 1760 1761 /* @brief Receive/transmit FIFO size in number of items. */ 1762 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1763 /* @brief Maximum transfer data width in bits. */ 1764 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1765 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1766 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (4) 1767 /* @brief Number of chip select pins. */ 1768 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (3) 1769 /* @brief Number of CTAR registers. */ 1770 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1771 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1772 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 1773 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1774 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1775 /* @brief Has 16-bit data transfer support. */ 1776 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1777 /* @brief Has separate DMA RX and TX requests. */ 1778 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1779 1780 /* SysTick module features */ 1781 1782 /* @brief Systick has external reference clock. */ 1783 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1784 /* @brief Systick external reference clock is core clock divided by this value. */ 1785 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1786 1787 /* TPM module features */ 1788 1789 /* @brief Bus clock is the source clock for the module. */ 1790 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1791 /* @brief Number of channels. */ 1792 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) \ 1793 (((x) == TPM0) ? (4) : \ 1794 (((x) == TPM1) ? (2) : \ 1795 (((x) == TPM2) ? (2) : (-1)))) 1796 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1797 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1798 /* @brief Has TPM_PARAM. */ 1799 #define FSL_FEATURE_TPM_HAS_PARAM (0) 1800 /* @brief Has TPM_VERID. */ 1801 #define FSL_FEATURE_TPM_HAS_VERID (0) 1802 /* @brief Has TPM_GLOBAL. */ 1803 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 1804 /* @brief Has TPM_TRIG. */ 1805 #define FSL_FEATURE_TPM_HAS_TRIG (0) 1806 /* @brief Whether TRIG register has effect. */ 1807 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) 1808 /* @brief Has counter pause on trigger. */ 1809 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1810 /* @brief Has external trigger selection. */ 1811 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1812 /* @brief Has TPM_COMBINE register. */ 1813 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 1814 /* @brief Whether COMBINE register has effect. */ 1815 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) \ 1816 (((x) == TPM0) ? (0) : \ 1817 (((x) == TPM1) ? (1) : \ 1818 (((x) == TPM2) ? (1) : (-1)))) 1819 /* @brief Has TPM_POL. */ 1820 #define FSL_FEATURE_TPM_HAS_POL (1) 1821 /* @brief Whether POL register has effect. */ 1822 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 1823 /* @brief Has TPM_FILTER register. */ 1824 #define FSL_FEATURE_TPM_HAS_FILTER (1) 1825 /* @brief Whether FILTER register has effect. */ 1826 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) \ 1827 (((x) == TPM0) ? (0) : \ 1828 (((x) == TPM1) ? (1) : \ 1829 (((x) == TPM2) ? (1) : (-1)))) 1830 /* @brief Has TPM_QDCTRL register. */ 1831 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 1832 /* @brief Whether QDCTRL register has effect. */ 1833 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) \ 1834 (((x) == TPM0) ? (0) : \ 1835 (((x) == TPM1) ? (1) : \ 1836 (((x) == TPM2) ? (1) : (-1)))) 1837 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 1838 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 1839 /* @brief Whether 32 bits counter has effect. */ 1840 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 1841 1842 /* TRNG module features */ 1843 1844 /* No feature definitions */ 1845 1846 /* TSI module features */ 1847 1848 /* @brief TSI module version. */ 1849 #define FSL_FEATURE_TSI_VERSION (4) 1850 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 1851 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (0) 1852 /* @brief Number of TSI channels. */ 1853 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 1854 1855 /* VREF module features */ 1856 1857 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1858 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1859 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1860 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1861 /* @brief If high/low buffer mode supported */ 1862 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1863 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1864 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1865 /* @brief Has VREF_TRM4. */ 1866 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1867 1868 /* XCVR_ANALOG module features */ 1869 1870 /* No feature definitions */ 1871 1872 /* XCVR_PHY module features */ 1873 1874 /* No feature definitions */ 1875 1876 /* ZLL module features */ 1877 1878 /* No feature definitions */ 1879 1880 #endif /* _MKW41Z4_FEATURES_H_ */ 1881 1882
