1 /* 2 ** ################################################################### 3 ** Version: rev. 1.3, 2015-06-08 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2014-12-14) 20 ** Initial version. 21 ** - rev. 1.1 (2015-01-21) 22 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 23 ** - rev. 1.2 (2015-05-25) 24 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 25 ** - rev. 1.3 (2015-06-08) 26 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 27 ** 28 ** ################################################################### 29 */ 30 31 #ifndef _MKV11Z7_FEATURES_H_ 32 #define _MKV11Z7_FEATURES_H_ 33 34 /* SOC module features */ 35 36 /* @brief ADC16 availability on the SoC. */ 37 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 38 /* @brief FLEXCAN availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) 40 /* @brief CMP availability on the SoC. */ 41 #define FSL_FEATURE_SOC_CMP_COUNT (2) 42 /* @brief CRC availability on the SoC. */ 43 #define FSL_FEATURE_SOC_CRC_COUNT (1) 44 /* @brief DAC availability on the SoC. */ 45 #define FSL_FEATURE_SOC_DAC_COUNT (1) 46 /* @brief EDMA availability on the SoC. */ 47 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 48 /* @brief DMAMUX availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 50 /* @brief DSPI availability on the SoC. */ 51 #define FSL_FEATURE_SOC_DSPI_COUNT (1) 52 /* @brief EWM availability on the SoC. */ 53 #define FSL_FEATURE_SOC_EWM_COUNT (1) 54 /* @brief FGPIO availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 56 /* @brief FTFA availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 58 /* @brief FTM availability on the SoC. */ 59 #define FSL_FEATURE_SOC_FTM_COUNT (6) 60 /* @brief GPIO availability on the SoC. */ 61 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 62 /* @brief I2C availability on the SoC. */ 63 #define FSL_FEATURE_SOC_I2C_COUNT (1) 64 /* @brief LLWU availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 66 /* @brief LPTMR availability on the SoC. */ 67 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 68 /* @brief MCG availability on the SoC. */ 69 #define FSL_FEATURE_SOC_MCG_COUNT (1) 70 /* @brief MCM availability on the SoC. */ 71 #define FSL_FEATURE_SOC_MCM_COUNT (1) 72 /* @brief MMDVSQ availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) 74 /* @brief MTB availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MTB_COUNT (1) 76 /* @brief MTBDWT availability on the SoC. */ 77 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 78 /* @brief OSC availability on the SoC. */ 79 #define FSL_FEATURE_SOC_OSC_COUNT (1) 80 /* @brief PDB availability on the SoC. */ 81 #define FSL_FEATURE_SOC_PDB_COUNT (2) 82 /* @brief PMC availability on the SoC. */ 83 #define FSL_FEATURE_SOC_PMC_COUNT (1) 84 /* @brief PORT availability on the SoC. */ 85 #define FSL_FEATURE_SOC_PORT_COUNT (5) 86 /* @brief RCM availability on the SoC. */ 87 #define FSL_FEATURE_SOC_RCM_COUNT (1) 88 /* @brief ROM availability on the SoC. */ 89 #define FSL_FEATURE_SOC_ROM_COUNT (1) 90 /* @brief SIM availability on the SoC. */ 91 #define FSL_FEATURE_SOC_SIM_COUNT (1) 92 /* @brief SMC availability on the SoC. */ 93 #define FSL_FEATURE_SOC_SMC_COUNT (1) 94 /* @brief UART availability on the SoC. */ 95 #define FSL_FEATURE_SOC_UART_COUNT (2) 96 /* @brief WDOG availability on the SoC. */ 97 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 98 99 /* ADC16 module features */ 100 101 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 102 #define FSL_FEATURE_ADC16_HAS_PGA (0) 103 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 104 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 105 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 106 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 107 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 108 #define FSL_FEATURE_ADC16_HAS_DMA (1) 109 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 110 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 111 /* @brief Has FIFO (bit SC4[AFDEP]). */ 112 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 113 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 114 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 115 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 116 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (0) 117 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 118 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 119 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 120 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 121 /* @brief Has HW averaging (bit SC3[AVGE]). */ 122 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 123 /* @brief Has offset correction (register OFS). */ 124 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 125 /* @brief Maximum ADC resolution. */ 126 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 127 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 128 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 129 130 /* FLEXCAN module features */ 131 132 /* @brief Message buffer size */ 133 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 134 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 135 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (1) 136 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 137 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (1) 138 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 139 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 140 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 141 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 142 /* @brief Instance has extended bit timing register (register CBT). */ 143 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (1) 144 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 145 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (1) 146 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 147 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (1) 148 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 149 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 150 /* @brief Has bitfield name BUF31TO0M. */ 151 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (1) 152 /* @brief Number of interrupt vectors. */ 153 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 154 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 155 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 156 157 /* CMP module features */ 158 159 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 160 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 161 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 162 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 163 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 164 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 165 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 166 #define FSL_FEATURE_CMP_HAS_DMA (1) 167 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 168 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (0) 169 /* @brief Has DAC Test function in CMP (register DACTEST). */ 170 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 171 172 /* CRC module features */ 173 174 /* @brief Has data register with name CRC */ 175 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 176 177 /* DAC module features */ 178 179 /* @brief Define the size of hardware buffer */ 180 #define FSL_FEATURE_DAC_BUFFER_SIZE (2) 181 /* @brief Define whether the buffer supports watermark event detection or not. */ 182 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 183 /* @brief Define whether the buffer supports watermark selection detection or not. */ 184 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (0) 185 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 186 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (0) 187 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 188 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (0) 189 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 190 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (0) 191 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 192 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (0) 193 /* @brief Define whether FIFO buffer mode is available or not. */ 194 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 195 /* @brief Define whether swing buffer mode is available or not.. */ 196 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (0) 197 198 /* EDMA module features */ 199 200 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 201 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) 202 /* @brief Total number of DMA channels on all modules. */ 203 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8) 204 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 205 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 206 /* @brief Has DMA_Error interrupt vector. */ 207 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 208 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 209 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8) 210 /* @brief Channel IRQ entry shared offset. */ 211 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4) 212 /* @brief If 8 bytes transfer supported. */ 213 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 214 /* @brief If 16 bytes transfer supported. */ 215 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 216 217 /* DMAMUX module features */ 218 219 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 220 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8) 221 /* @brief Total number of DMA channels on all modules. */ 222 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (8) 223 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 224 #define FSL_FEATURE_DMAMUX_HAS_TRIG (0) 225 /* @brief Register CHCFGn width. */ 226 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 227 228 /* EWM module features */ 229 230 /* @brief Has clock select (register CLKCTRL). */ 231 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (1) 232 /* @brief Has clock prescaler (register CLKPRESCALER). */ 233 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 234 235 /* FGPIO module features */ 236 237 /* No feature definitions */ 238 239 /* FLASH module features */ 240 241 #if defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || defined(CPU_MKV11Z128VLH7) 242 /* @brief Is of type FTFA. */ 243 #define FSL_FEATURE_FLASH_IS_FTFA (1) 244 /* @brief Is of type FTFE. */ 245 #define FSL_FEATURE_FLASH_IS_FTFE (0) 246 /* @brief Is of type FTFL. */ 247 #define FSL_FEATURE_FLASH_IS_FTFL (0) 248 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 249 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 250 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 251 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 252 /* @brief Has EEPROM region protection (register FEPROT). */ 253 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 254 /* @brief Has data flash region protection (register FDPROT). */ 255 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 256 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 257 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 258 /* @brief Has flash cache control in FMC module. */ 259 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 260 /* @brief Has flash cache control in MCM module. */ 261 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 262 /* @brief Has flash cache control in MSCM module. */ 263 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 264 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 265 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 266 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 267 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 268 /* @brief P-Flash start address. */ 269 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 270 /* @brief P-Flash block count. */ 271 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 272 /* @brief P-Flash block size. */ 273 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 274 /* @brief P-Flash sector size. */ 275 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 276 /* @brief P-Flash write unit size. */ 277 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 278 /* @brief P-Flash data path width. */ 279 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 280 /* @brief P-Flash block swap feature. */ 281 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 282 /* @brief P-Flash protection region count. */ 283 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 284 /* @brief Has FlexNVM memory. */ 285 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 286 /* @brief Has FlexNVM alias. */ 287 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 288 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 289 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 290 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 291 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 292 /* @brief FlexNVM block count. */ 293 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 294 /* @brief FlexNVM block size. */ 295 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 296 /* @brief FlexNVM sector size. */ 297 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 298 /* @brief FlexNVM write unit size. */ 299 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 300 /* @brief FlexNVM data path width. */ 301 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 302 /* @brief Has FlexRAM memory. */ 303 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 304 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 305 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 306 /* @brief FlexRAM size. */ 307 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 308 /* @brief Has 0x00 Read 1s Block command. */ 309 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 310 /* @brief Has 0x01 Read 1s Section command. */ 311 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 312 /* @brief Has 0x02 Program Check command. */ 313 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 314 /* @brief Has 0x03 Read Resource command. */ 315 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 316 /* @brief Has 0x06 Program Longword command. */ 317 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 318 /* @brief Has 0x07 Program Phrase command. */ 319 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 320 /* @brief Has 0x08 Erase Flash Block command. */ 321 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 322 /* @brief Has 0x09 Erase Flash Sector command. */ 323 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 324 /* @brief Has 0x0B Program Section command. */ 325 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 326 /* @brief Has 0x40 Read 1s All Blocks command. */ 327 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 328 /* @brief Has 0x41 Read Once command. */ 329 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 330 /* @brief Has 0x43 Program Once command. */ 331 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 332 /* @brief Has 0x44 Erase All Blocks command. */ 333 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 334 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 335 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 336 /* @brief Has 0x46 Swap Control command. */ 337 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 338 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 339 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 340 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 341 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 342 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 343 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 344 /* @brief Has 0x80 Program Partition command. */ 345 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 346 /* @brief Has 0x81 Set FlexRAM Function command. */ 347 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 348 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 349 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 350 /* @brief P-Flash Erase sector command address alignment. */ 351 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 352 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 353 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 354 /* @brief P-Flash Read resource command address alignment. */ 355 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 356 /* @brief P-Flash Program check command address alignment. */ 357 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 358 /* @brief P-Flash Program check command address alignment. */ 359 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 360 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 361 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 362 /* @brief FlexNVM Erase sector command address alignment. */ 363 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 364 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 365 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 366 /* @brief FlexNVM Read resource command address alignment. */ 367 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 368 /* @brief FlexNVM Program check command address alignment. */ 369 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 370 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 371 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 372 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 373 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 374 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 375 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 376 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 377 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 378 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 379 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 380 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 381 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 382 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 383 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 384 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 385 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 386 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 387 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 388 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 390 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 392 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 394 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 396 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 398 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 400 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 401 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 402 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 403 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 404 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 405 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 406 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 407 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 408 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 409 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 410 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 411 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 412 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 413 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 414 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 415 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 416 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 417 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 418 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 419 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 420 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 421 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 422 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 423 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 424 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 425 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 426 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 427 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 428 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 429 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 430 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 431 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 432 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 433 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 434 #elif defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) || defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7) 435 /* @brief Is of type FTFA. */ 436 #define FSL_FEATURE_FLASH_IS_FTFA (1) 437 /* @brief Is of type FTFE. */ 438 #define FSL_FEATURE_FLASH_IS_FTFE (0) 439 /* @brief Is of type FTFL. */ 440 #define FSL_FEATURE_FLASH_IS_FTFL (0) 441 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 442 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 443 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 444 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 445 /* @brief Has EEPROM region protection (register FEPROT). */ 446 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 447 /* @brief Has data flash region protection (register FDPROT). */ 448 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 449 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 450 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 451 /* @brief Has flash cache control in FMC module. */ 452 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 453 /* @brief Has flash cache control in MCM module. */ 454 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 455 /* @brief Has flash cache control in MSCM module. */ 456 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 457 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 458 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 459 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 460 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 461 /* @brief P-Flash start address. */ 462 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 463 /* @brief P-Flash block count. */ 464 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 465 /* @brief P-Flash block size. */ 466 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 467 /* @brief P-Flash sector size. */ 468 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 469 /* @brief P-Flash write unit size. */ 470 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 471 /* @brief P-Flash data path width. */ 472 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 473 /* @brief P-Flash block swap feature. */ 474 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 475 /* @brief P-Flash protection region count. */ 476 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 477 /* @brief Has FlexNVM memory. */ 478 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 479 /* @brief Has FlexNVM alias. */ 480 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 481 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 482 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 483 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 484 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 485 /* @brief FlexNVM block count. */ 486 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 487 /* @brief FlexNVM block size. */ 488 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 489 /* @brief FlexNVM sector size. */ 490 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 491 /* @brief FlexNVM write unit size. */ 492 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 493 /* @brief FlexNVM data path width. */ 494 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 495 /* @brief Has FlexRAM memory. */ 496 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 497 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 498 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 499 /* @brief FlexRAM size. */ 500 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 501 /* @brief Has 0x00 Read 1s Block command. */ 502 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 503 /* @brief Has 0x01 Read 1s Section command. */ 504 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 505 /* @brief Has 0x02 Program Check command. */ 506 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 507 /* @brief Has 0x03 Read Resource command. */ 508 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 509 /* @brief Has 0x06 Program Longword command. */ 510 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 511 /* @brief Has 0x07 Program Phrase command. */ 512 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 513 /* @brief Has 0x08 Erase Flash Block command. */ 514 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 515 /* @brief Has 0x09 Erase Flash Sector command. */ 516 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 517 /* @brief Has 0x0B Program Section command. */ 518 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 519 /* @brief Has 0x40 Read 1s All Blocks command. */ 520 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 521 /* @brief Has 0x41 Read Once command. */ 522 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 523 /* @brief Has 0x43 Program Once command. */ 524 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 525 /* @brief Has 0x44 Erase All Blocks command. */ 526 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 527 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 528 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 529 /* @brief Has 0x46 Swap Control command. */ 530 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 531 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 532 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 533 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 534 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 535 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 536 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 537 /* @brief Has 0x80 Program Partition command. */ 538 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 539 /* @brief Has 0x81 Set FlexRAM Function command. */ 540 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 541 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 542 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 543 /* @brief P-Flash Erase sector command address alignment. */ 544 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 545 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 546 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 547 /* @brief P-Flash Read resource command address alignment. */ 548 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 549 /* @brief P-Flash Program check command address alignment. */ 550 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 551 /* @brief P-Flash Program check command address alignment. */ 552 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 553 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 554 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 555 /* @brief FlexNVM Erase sector command address alignment. */ 556 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 557 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 558 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 559 /* @brief FlexNVM Read resource command address alignment. */ 560 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 561 /* @brief FlexNVM Program check command address alignment. */ 562 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 563 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 564 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 565 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 566 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 567 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 568 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 569 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 570 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 571 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 572 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 573 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 574 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 575 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 576 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 577 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 578 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 579 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 580 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 581 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 582 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 583 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 584 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 585 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 586 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 587 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 588 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 589 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 590 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 591 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 592 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 593 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 594 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 595 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 596 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 597 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 598 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 599 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 600 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 601 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 602 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 603 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 604 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 605 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 606 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 607 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 608 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 609 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 610 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 611 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 612 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 613 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 614 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 615 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 616 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 617 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 618 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 619 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 620 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 621 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 622 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 623 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 624 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 625 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 626 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 627 #endif /* defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z128VLF7) || defined(CPU_MKV11Z128VLH7) */ 628 629 /* FTM module features */ 630 631 /* @brief Number of channels. */ 632 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 633 (((x) == FTM0) ? (6) : \ 634 (((x) == FTM1) ? (2) : \ 635 (((x) == FTM2) ? (2) : \ 636 (((x) == FTM3) ? (6) : \ 637 (((x) == FTM4) ? (2) : \ 638 (((x) == FTM5) ? (2) : (-1))))))) 639 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 640 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 641 /* @brief Has extended deadtime value. */ 642 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 643 /* @brief Enable pwm output for the module. */ 644 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 645 /* @brief Has half-cycle reload for the module. */ 646 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 647 /* @brief Has reload interrupt. */ 648 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 649 /* @brief Has reload initialization trigger. */ 650 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 651 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 652 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 653 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 654 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 655 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 656 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 657 /* @brief Has no QDCTRL. */ 658 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 659 /* @brief If instance has only TPM function. */ 660 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 661 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 662 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (0) 663 664 /* GPIO module features */ 665 666 /* @brief Has GPIO attribute checker register (GACR). */ 667 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 668 669 /* I2C module features */ 670 671 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 672 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 673 /* @brief Maximum supported baud rate in kilobit per second. */ 674 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 675 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 676 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 677 /* @brief Has DMA support (register bit C1[DMAEN]). */ 678 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 679 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 680 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 681 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 682 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 683 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 684 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 685 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 686 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 687 /* @brief Has control of the drive capability of the I2C pins. */ 688 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 689 /* @brief Has double buffering support (register S2). */ 690 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 691 /* @brief Has double buffer enable. */ 692 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 693 694 /* LLWU module features */ 695 696 #if defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) 697 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 698 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 699 /* @brief Has pins 8-15 connected to LLWU device. */ 700 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 701 /* @brief Maximum number of internal modules connected to LLWU device. */ 702 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 703 /* @brief Number of digital filters. */ 704 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 705 /* @brief Has MF register. */ 706 #define FSL_FEATURE_LLWU_HAS_MF (1) 707 /* @brief Has PF register. */ 708 #define FSL_FEATURE_LLWU_HAS_PF (1) 709 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 710 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 711 /* @brief Has no internal module wakeup flag register. */ 712 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 713 /* @brief Has external pin 0 connected to LLWU device. */ 714 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 715 /* @brief Index of port of external pin. */ 716 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 717 /* @brief Number of external pin port on specified port. */ 718 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 719 /* @brief Has external pin 1 connected to LLWU device. */ 720 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 721 /* @brief Index of port of external pin. */ 722 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 723 /* @brief Number of external pin port on specified port. */ 724 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 725 /* @brief Has external pin 2 connected to LLWU device. */ 726 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 727 /* @brief Index of port of external pin. */ 728 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 729 /* @brief Number of external pin port on specified port. */ 730 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 731 /* @brief Has external pin 3 connected to LLWU device. */ 732 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 733 /* @brief Index of port of external pin. */ 734 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 735 /* @brief Number of external pin port on specified port. */ 736 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 737 /* @brief Has external pin 4 connected to LLWU device. */ 738 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 739 /* @brief Index of port of external pin. */ 740 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 741 /* @brief Number of external pin port on specified port. */ 742 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 743 /* @brief Has external pin 5 connected to LLWU device. */ 744 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 745 /* @brief Index of port of external pin. */ 746 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 747 /* @brief Number of external pin port on specified port. */ 748 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 749 /* @brief Has external pin 6 connected to LLWU device. */ 750 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 751 /* @brief Index of port of external pin. */ 752 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 753 /* @brief Number of external pin port on specified port. */ 754 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 755 /* @brief Has external pin 7 connected to LLWU device. */ 756 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 757 /* @brief Index of port of external pin. */ 758 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 759 /* @brief Number of external pin port on specified port. */ 760 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 761 /* @brief Has external pin 8 connected to LLWU device. */ 762 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 763 /* @brief Index of port of external pin. */ 764 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 765 /* @brief Number of external pin port on specified port. */ 766 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 767 /* @brief Has external pin 9 connected to LLWU device. */ 768 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 769 /* @brief Index of port of external pin. */ 770 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 771 /* @brief Number of external pin port on specified port. */ 772 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 773 /* @brief Has external pin 10 connected to LLWU device. */ 774 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 775 /* @brief Index of port of external pin. */ 776 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 777 /* @brief Number of external pin port on specified port. */ 778 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 779 /* @brief Has external pin 11 connected to LLWU device. */ 780 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 781 /* @brief Index of port of external pin. */ 782 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 783 /* @brief Number of external pin port on specified port. */ 784 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 785 /* @brief Has external pin 12 connected to LLWU device. */ 786 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (0) 787 /* @brief Index of port of external pin. */ 788 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (0) 789 /* @brief Number of external pin port on specified port. */ 790 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 791 /* @brief Has external pin 13 connected to LLWU device. */ 792 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (0) 793 /* @brief Index of port of external pin. */ 794 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (0) 795 /* @brief Number of external pin port on specified port. */ 796 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (0) 797 /* @brief Has external pin 14 connected to LLWU device. */ 798 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 799 /* @brief Index of port of external pin. */ 800 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 801 /* @brief Number of external pin port on specified port. */ 802 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 803 /* @brief Has external pin 15 connected to LLWU device. */ 804 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 805 /* @brief Index of port of external pin. */ 806 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 807 /* @brief Number of external pin port on specified port. */ 808 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 809 /* @brief Has external pin 16 connected to LLWU device. */ 810 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 811 /* @brief Index of port of external pin. */ 812 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 813 /* @brief Number of external pin port on specified port. */ 814 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 815 /* @brief Has external pin 17 connected to LLWU device. */ 816 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 817 /* @brief Index of port of external pin. */ 818 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 819 /* @brief Number of external pin port on specified port. */ 820 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 821 /* @brief Has external pin 18 connected to LLWU device. */ 822 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 823 /* @brief Index of port of external pin. */ 824 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 825 /* @brief Number of external pin port on specified port. */ 826 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 827 /* @brief Has external pin 19 connected to LLWU device. */ 828 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 829 /* @brief Index of port of external pin. */ 830 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 831 /* @brief Number of external pin port on specified port. */ 832 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 833 /* @brief Has external pin 20 connected to LLWU device. */ 834 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 835 /* @brief Index of port of external pin. */ 836 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 837 /* @brief Number of external pin port on specified port. */ 838 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 839 /* @brief Has external pin 21 connected to LLWU device. */ 840 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 841 /* @brief Index of port of external pin. */ 842 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 843 /* @brief Number of external pin port on specified port. */ 844 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 845 /* @brief Has external pin 22 connected to LLWU device. */ 846 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 847 /* @brief Index of port of external pin. */ 848 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 849 /* @brief Number of external pin port on specified port. */ 850 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 851 /* @brief Has external pin 23 connected to LLWU device. */ 852 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 853 /* @brief Index of port of external pin. */ 854 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 855 /* @brief Number of external pin port on specified port. */ 856 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 857 /* @brief Has external pin 24 connected to LLWU device. */ 858 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 859 /* @brief Index of port of external pin. */ 860 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 861 /* @brief Number of external pin port on specified port. */ 862 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 863 /* @brief Has external pin 25 connected to LLWU device. */ 864 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 865 /* @brief Index of port of external pin. */ 866 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 867 /* @brief Number of external pin port on specified port. */ 868 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 869 /* @brief Has external pin 26 connected to LLWU device. */ 870 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 871 /* @brief Index of port of external pin. */ 872 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 873 /* @brief Number of external pin port on specified port. */ 874 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 875 /* @brief Has external pin 27 connected to LLWU device. */ 876 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 877 /* @brief Index of port of external pin. */ 878 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 879 /* @brief Number of external pin port on specified port. */ 880 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 881 /* @brief Has external pin 28 connected to LLWU device. */ 882 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 883 /* @brief Index of port of external pin. */ 884 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 885 /* @brief Number of external pin port on specified port. */ 886 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 887 /* @brief Has external pin 29 connected to LLWU device. */ 888 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 889 /* @brief Index of port of external pin. */ 890 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 891 /* @brief Number of external pin port on specified port. */ 892 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 893 /* @brief Has external pin 30 connected to LLWU device. */ 894 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 895 /* @brief Index of port of external pin. */ 896 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 897 /* @brief Number of external pin port on specified port. */ 898 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 899 /* @brief Has external pin 31 connected to LLWU device. */ 900 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 901 /* @brief Index of port of external pin. */ 902 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 903 /* @brief Number of external pin port on specified port. */ 904 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 905 /* @brief Has internal module 0 connected to LLWU device. */ 906 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 907 /* @brief Has internal module 1 connected to LLWU device. */ 908 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 909 /* @brief Has internal module 2 connected to LLWU device. */ 910 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 911 /* @brief Has internal module 3 connected to LLWU device. */ 912 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 913 /* @brief Has internal module 4 connected to LLWU device. */ 914 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 915 /* @brief Has internal module 5 connected to LLWU device. */ 916 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 917 /* @brief Has internal module 6 connected to LLWU device. */ 918 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 919 /* @brief Has internal module 7 connected to LLWU device. */ 920 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 921 /* @brief Has Version ID Register (LLWU_VERID). */ 922 #define FSL_FEATURE_LLWU_HAS_VERID (0) 923 /* @brief Has Parameter Register (LLWU_PARAM). */ 924 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 925 /* @brief Width of registers of the LLWU. */ 926 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 927 /* @brief Has DMA Enable register (LLWU_DE). */ 928 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 929 #elif defined(CPU_MKV11Z128VLF7) || defined(CPU_MKV11Z64VLF7) 930 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 931 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 932 /* @brief Has pins 8-15 connected to LLWU device. */ 933 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 934 /* @brief Maximum number of internal modules connected to LLWU device. */ 935 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 936 /* @brief Number of digital filters. */ 937 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 938 /* @brief Has MF register. */ 939 #define FSL_FEATURE_LLWU_HAS_MF (1) 940 /* @brief Has PF register. */ 941 #define FSL_FEATURE_LLWU_HAS_PF (1) 942 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 943 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 944 /* @brief Has no internal module wakeup flag register. */ 945 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 946 /* @brief Has external pin 0 connected to LLWU device. */ 947 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (0) 948 /* @brief Index of port of external pin. */ 949 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (0) 950 /* @brief Number of external pin port on specified port. */ 951 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (0) 952 /* @brief Has external pin 1 connected to LLWU device. */ 953 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 954 /* @brief Index of port of external pin. */ 955 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 956 /* @brief Number of external pin port on specified port. */ 957 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 958 /* @brief Has external pin 2 connected to LLWU device. */ 959 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 960 /* @brief Index of port of external pin. */ 961 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 962 /* @brief Number of external pin port on specified port. */ 963 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 964 /* @brief Has external pin 3 connected to LLWU device. */ 965 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 966 /* @brief Index of port of external pin. */ 967 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 968 /* @brief Number of external pin port on specified port. */ 969 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 970 /* @brief Has external pin 4 connected to LLWU device. */ 971 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (0) 972 /* @brief Index of port of external pin. */ 973 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (0) 974 /* @brief Number of external pin port on specified port. */ 975 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (0) 976 /* @brief Has external pin 5 connected to LLWU device. */ 977 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 978 /* @brief Index of port of external pin. */ 979 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 980 /* @brief Number of external pin port on specified port. */ 981 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 982 /* @brief Has external pin 6 connected to LLWU device. */ 983 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 984 /* @brief Index of port of external pin. */ 985 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 986 /* @brief Number of external pin port on specified port. */ 987 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 988 /* @brief Has external pin 7 connected to LLWU device. */ 989 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 990 /* @brief Index of port of external pin. */ 991 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 992 /* @brief Number of external pin port on specified port. */ 993 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 994 /* @brief Has external pin 8 connected to LLWU device. */ 995 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 996 /* @brief Index of port of external pin. */ 997 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 998 /* @brief Number of external pin port on specified port. */ 999 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1000 /* @brief Has external pin 9 connected to LLWU device. */ 1001 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1002 /* @brief Index of port of external pin. */ 1003 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1004 /* @brief Number of external pin port on specified port. */ 1005 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1006 /* @brief Has external pin 10 connected to LLWU device. */ 1007 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1008 /* @brief Index of port of external pin. */ 1009 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1010 /* @brief Number of external pin port on specified port. */ 1011 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1012 /* @brief Has external pin 11 connected to LLWU device. */ 1013 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (0) 1014 /* @brief Index of port of external pin. */ 1015 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (0) 1016 /* @brief Number of external pin port on specified port. */ 1017 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (0) 1018 /* @brief Has external pin 12 connected to LLWU device. */ 1019 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1020 /* @brief Index of port of external pin. */ 1021 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1022 /* @brief Number of external pin port on specified port. */ 1023 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1024 /* @brief Has external pin 13 connected to LLWU device. */ 1025 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1026 /* @brief Index of port of external pin. */ 1027 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1028 /* @brief Number of external pin port on specified port. */ 1029 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1030 /* @brief Has external pin 14 connected to LLWU device. */ 1031 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1032 /* @brief Index of port of external pin. */ 1033 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1034 /* @brief Number of external pin port on specified port. */ 1035 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1036 /* @brief Has external pin 15 connected to LLWU device. */ 1037 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1038 /* @brief Index of port of external pin. */ 1039 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1040 /* @brief Number of external pin port on specified port. */ 1041 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1042 /* @brief Has external pin 16 connected to LLWU device. */ 1043 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1044 /* @brief Index of port of external pin. */ 1045 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1046 /* @brief Number of external pin port on specified port. */ 1047 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1048 /* @brief Has external pin 17 connected to LLWU device. */ 1049 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1050 /* @brief Index of port of external pin. */ 1051 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1052 /* @brief Number of external pin port on specified port. */ 1053 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1054 /* @brief Has external pin 18 connected to LLWU device. */ 1055 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1056 /* @brief Index of port of external pin. */ 1057 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1058 /* @brief Number of external pin port on specified port. */ 1059 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1060 /* @brief Has external pin 19 connected to LLWU device. */ 1061 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1062 /* @brief Index of port of external pin. */ 1063 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1064 /* @brief Number of external pin port on specified port. */ 1065 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1066 /* @brief Has external pin 20 connected to LLWU device. */ 1067 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1068 /* @brief Index of port of external pin. */ 1069 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1070 /* @brief Number of external pin port on specified port. */ 1071 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1072 /* @brief Has external pin 21 connected to LLWU device. */ 1073 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1074 /* @brief Index of port of external pin. */ 1075 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1076 /* @brief Number of external pin port on specified port. */ 1077 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1078 /* @brief Has external pin 22 connected to LLWU device. */ 1079 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1080 /* @brief Index of port of external pin. */ 1081 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1082 /* @brief Number of external pin port on specified port. */ 1083 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1084 /* @brief Has external pin 23 connected to LLWU device. */ 1085 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1086 /* @brief Index of port of external pin. */ 1087 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1088 /* @brief Number of external pin port on specified port. */ 1089 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1090 /* @brief Has external pin 24 connected to LLWU device. */ 1091 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1092 /* @brief Index of port of external pin. */ 1093 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1094 /* @brief Number of external pin port on specified port. */ 1095 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1096 /* @brief Has external pin 25 connected to LLWU device. */ 1097 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1098 /* @brief Index of port of external pin. */ 1099 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1100 /* @brief Number of external pin port on specified port. */ 1101 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1102 /* @brief Has external pin 26 connected to LLWU device. */ 1103 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1104 /* @brief Index of port of external pin. */ 1105 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1106 /* @brief Number of external pin port on specified port. */ 1107 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1108 /* @brief Has external pin 27 connected to LLWU device. */ 1109 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1110 /* @brief Index of port of external pin. */ 1111 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1112 /* @brief Number of external pin port on specified port. */ 1113 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1114 /* @brief Has external pin 28 connected to LLWU device. */ 1115 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1116 /* @brief Index of port of external pin. */ 1117 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1118 /* @brief Number of external pin port on specified port. */ 1119 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1120 /* @brief Has external pin 29 connected to LLWU device. */ 1121 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1122 /* @brief Index of port of external pin. */ 1123 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1124 /* @brief Number of external pin port on specified port. */ 1125 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1126 /* @brief Has external pin 30 connected to LLWU device. */ 1127 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1128 /* @brief Index of port of external pin. */ 1129 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1130 /* @brief Number of external pin port on specified port. */ 1131 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1132 /* @brief Has external pin 31 connected to LLWU device. */ 1133 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1134 /* @brief Index of port of external pin. */ 1135 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1136 /* @brief Number of external pin port on specified port. */ 1137 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1138 /* @brief Has internal module 0 connected to LLWU device. */ 1139 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1140 /* @brief Has internal module 1 connected to LLWU device. */ 1141 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1142 /* @brief Has internal module 2 connected to LLWU device. */ 1143 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1144 /* @brief Has internal module 3 connected to LLWU device. */ 1145 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1146 /* @brief Has internal module 4 connected to LLWU device. */ 1147 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1148 /* @brief Has internal module 5 connected to LLWU device. */ 1149 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1150 /* @brief Has internal module 6 connected to LLWU device. */ 1151 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1152 /* @brief Has internal module 7 connected to LLWU device. */ 1153 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1154 /* @brief Has Version ID Register (LLWU_VERID). */ 1155 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1156 /* @brief Has Parameter Register (LLWU_PARAM). */ 1157 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1158 /* @brief Width of registers of the LLWU. */ 1159 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1160 /* @brief Has DMA Enable register (LLWU_DE). */ 1161 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1162 #elif defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VLH7) 1163 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 1164 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (22) 1165 /* @brief Has pins 8-15 connected to LLWU device. */ 1166 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 1167 /* @brief Maximum number of internal modules connected to LLWU device. */ 1168 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (3) 1169 /* @brief Number of digital filters. */ 1170 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 1171 /* @brief Has MF register. */ 1172 #define FSL_FEATURE_LLWU_HAS_MF (1) 1173 /* @brief Has PF register. */ 1174 #define FSL_FEATURE_LLWU_HAS_PF (1) 1175 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 1176 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 1177 /* @brief Has no internal module wakeup flag register. */ 1178 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 1179 /* @brief Has external pin 0 connected to LLWU device. */ 1180 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 1181 /* @brief Index of port of external pin. */ 1182 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 1183 /* @brief Number of external pin port on specified port. */ 1184 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 1185 /* @brief Has external pin 1 connected to LLWU device. */ 1186 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (0) 1187 /* @brief Index of port of external pin. */ 1188 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (0) 1189 /* @brief Number of external pin port on specified port. */ 1190 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (0) 1191 /* @brief Has external pin 2 connected to LLWU device. */ 1192 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (0) 1193 /* @brief Index of port of external pin. */ 1194 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (0) 1195 /* @brief Number of external pin port on specified port. */ 1196 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (0) 1197 /* @brief Has external pin 3 connected to LLWU device. */ 1198 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 1199 /* @brief Index of port of external pin. */ 1200 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 1201 /* @brief Number of external pin port on specified port. */ 1202 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 1203 /* @brief Has external pin 4 connected to LLWU device. */ 1204 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 1205 /* @brief Index of port of external pin. */ 1206 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 1207 /* @brief Number of external pin port on specified port. */ 1208 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 1209 /* @brief Has external pin 5 connected to LLWU device. */ 1210 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 1211 /* @brief Index of port of external pin. */ 1212 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 1213 /* @brief Number of external pin port on specified port. */ 1214 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 1215 /* @brief Has external pin 6 connected to LLWU device. */ 1216 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 1217 /* @brief Index of port of external pin. */ 1218 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 1219 /* @brief Number of external pin port on specified port. */ 1220 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 1221 /* @brief Has external pin 7 connected to LLWU device. */ 1222 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 1223 /* @brief Index of port of external pin. */ 1224 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 1225 /* @brief Number of external pin port on specified port. */ 1226 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 1227 /* @brief Has external pin 8 connected to LLWU device. */ 1228 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 1229 /* @brief Index of port of external pin. */ 1230 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 1231 /* @brief Number of external pin port on specified port. */ 1232 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 1233 /* @brief Has external pin 9 connected to LLWU device. */ 1234 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 1235 /* @brief Index of port of external pin. */ 1236 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 1237 /* @brief Number of external pin port on specified port. */ 1238 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 1239 /* @brief Has external pin 10 connected to LLWU device. */ 1240 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 1241 /* @brief Index of port of external pin. */ 1242 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 1243 /* @brief Number of external pin port on specified port. */ 1244 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 1245 /* @brief Has external pin 11 connected to LLWU device. */ 1246 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1247 /* @brief Index of port of external pin. */ 1248 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1249 /* @brief Number of external pin port on specified port. */ 1250 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1251 /* @brief Has external pin 12 connected to LLWU device. */ 1252 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1253 /* @brief Index of port of external pin. */ 1254 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1255 /* @brief Number of external pin port on specified port. */ 1256 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1257 /* @brief Has external pin 13 connected to LLWU device. */ 1258 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1259 /* @brief Index of port of external pin. */ 1260 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1261 /* @brief Number of external pin port on specified port. */ 1262 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1263 /* @brief Has external pin 14 connected to LLWU device. */ 1264 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1265 /* @brief Index of port of external pin. */ 1266 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1267 /* @brief Number of external pin port on specified port. */ 1268 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1269 /* @brief Has external pin 15 connected to LLWU device. */ 1270 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1271 /* @brief Index of port of external pin. */ 1272 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1273 /* @brief Number of external pin port on specified port. */ 1274 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1275 /* @brief Has external pin 16 connected to LLWU device. */ 1276 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1277 /* @brief Index of port of external pin. */ 1278 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1279 /* @brief Number of external pin port on specified port. */ 1280 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1281 /* @brief Has external pin 17 connected to LLWU device. */ 1282 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1283 /* @brief Index of port of external pin. */ 1284 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1285 /* @brief Number of external pin port on specified port. */ 1286 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1287 /* @brief Has external pin 18 connected to LLWU device. */ 1288 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1289 /* @brief Index of port of external pin. */ 1290 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1291 /* @brief Number of external pin port on specified port. */ 1292 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1293 /* @brief Has external pin 19 connected to LLWU device. */ 1294 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 1295 /* @brief Index of port of external pin. */ 1296 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 1297 /* @brief Number of external pin port on specified port. */ 1298 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 1299 /* @brief Has external pin 20 connected to LLWU device. */ 1300 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 1301 /* @brief Index of port of external pin. */ 1302 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 1303 /* @brief Number of external pin port on specified port. */ 1304 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 1305 /* @brief Has external pin 21 connected to LLWU device. */ 1306 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 1307 /* @brief Index of port of external pin. */ 1308 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 1309 /* @brief Number of external pin port on specified port. */ 1310 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 1311 /* @brief Has external pin 22 connected to LLWU device. */ 1312 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1313 /* @brief Index of port of external pin. */ 1314 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1315 /* @brief Number of external pin port on specified port. */ 1316 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1317 /* @brief Has external pin 23 connected to LLWU device. */ 1318 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1319 /* @brief Index of port of external pin. */ 1320 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1321 /* @brief Number of external pin port on specified port. */ 1322 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1323 /* @brief Has external pin 24 connected to LLWU device. */ 1324 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1325 /* @brief Index of port of external pin. */ 1326 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1327 /* @brief Number of external pin port on specified port. */ 1328 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1329 /* @brief Has external pin 25 connected to LLWU device. */ 1330 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1331 /* @brief Index of port of external pin. */ 1332 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1333 /* @brief Number of external pin port on specified port. */ 1334 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1335 /* @brief Has external pin 26 connected to LLWU device. */ 1336 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1337 /* @brief Index of port of external pin. */ 1338 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1339 /* @brief Number of external pin port on specified port. */ 1340 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1341 /* @brief Has external pin 27 connected to LLWU device. */ 1342 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1343 /* @brief Index of port of external pin. */ 1344 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1345 /* @brief Number of external pin port on specified port. */ 1346 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1347 /* @brief Has external pin 28 connected to LLWU device. */ 1348 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1349 /* @brief Index of port of external pin. */ 1350 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1351 /* @brief Number of external pin port on specified port. */ 1352 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1353 /* @brief Has external pin 29 connected to LLWU device. */ 1354 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1355 /* @brief Index of port of external pin. */ 1356 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1357 /* @brief Number of external pin port on specified port. */ 1358 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1359 /* @brief Has external pin 30 connected to LLWU device. */ 1360 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1361 /* @brief Index of port of external pin. */ 1362 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1363 /* @brief Number of external pin port on specified port. */ 1364 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1365 /* @brief Has external pin 31 connected to LLWU device. */ 1366 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1367 /* @brief Index of port of external pin. */ 1368 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1369 /* @brief Number of external pin port on specified port. */ 1370 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1371 /* @brief Has internal module 0 connected to LLWU device. */ 1372 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1373 /* @brief Has internal module 1 connected to LLWU device. */ 1374 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1375 /* @brief Has internal module 2 connected to LLWU device. */ 1376 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1377 /* @brief Has internal module 3 connected to LLWU device. */ 1378 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (0) 1379 /* @brief Has internal module 4 connected to LLWU device. */ 1380 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1381 /* @brief Has internal module 5 connected to LLWU device. */ 1382 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (0) 1383 /* @brief Has internal module 6 connected to LLWU device. */ 1384 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1385 /* @brief Has internal module 7 connected to LLWU device. */ 1386 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (0) 1387 /* @brief Has Version ID Register (LLWU_VERID). */ 1388 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1389 /* @brief Has Parameter Register (LLWU_PARAM). */ 1390 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1391 /* @brief Width of registers of the LLWU. */ 1392 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1393 /* @brief Has DMA Enable register (LLWU_DE). */ 1394 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1395 #endif /* defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) */ 1396 1397 /* LPTMR module features */ 1398 1399 /* @brief Has shared interrupt handler with another LPTMR module. */ 1400 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1401 /* @brief Whether LPTMR counter is 32 bits width. */ 1402 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1403 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1404 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1405 1406 /* MCG module features */ 1407 1408 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1409 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (0) 1410 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1411 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (0) 1412 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1413 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (0) 1414 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1415 #define FSL_FEATURE_MCG_PLL_REF_MIN (0) 1416 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1417 #define FSL_FEATURE_MCG_PLL_REF_MAX (0) 1418 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1419 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1420 /* @brief FRDIV supports 1280. */ 1421 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1422 /* @brief FRDIV supports 1536. */ 1423 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1424 /* @brief MCGFFCLK divider. */ 1425 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1426 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1427 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (1) 1428 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1429 #define FSL_FEATURE_MCG_HAS_RTC_32K (0) 1430 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1431 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1432 /* @brief Has 48MHz internal oscillator. */ 1433 #define FSL_FEATURE_MCG_HAS_IRC_48M (0) 1434 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1435 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1436 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1437 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1438 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1439 #define FSL_FEATURE_MCG_HAS_LOLRE (0) 1440 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1441 #define FSL_FEATURE_MCG_USE_OSCSEL (0) 1442 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1443 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1444 /* @brief TBD */ 1445 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1446 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS]). */ 1447 #define FSL_FEATURE_MCG_HAS_PLL (0) 1448 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1449 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (1) 1450 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1451 #define FSL_FEATURE_MCG_HAS_FLL (1) 1452 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1453 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1454 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1455 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1456 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1457 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (0) 1458 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1459 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1460 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1461 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1462 /* @brief Has external clock monitor (register bit C6[CME]). */ 1463 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1464 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1465 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1466 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1467 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1468 /* @brief Has PEI mode or PBI mode. */ 1469 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1470 /* @brief Reset clock mode is BLPI. */ 1471 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1472 1473 /* MMDVSQ module features */ 1474 1475 /* No feature definitions */ 1476 1477 /* interrupt module features */ 1478 1479 /* @brief Lowest interrupt request number. */ 1480 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1481 /* @brief Highest interrupt request number. */ 1482 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 1483 1484 /* OSC module features */ 1485 1486 /* @brief Has OSC1 external oscillator. */ 1487 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1488 /* @brief Has OSC0 external oscillator. */ 1489 #define FSL_FEATURE_OSC_HAS_OSC0 (1) 1490 /* @brief Has OSC external oscillator (without index). */ 1491 #define FSL_FEATURE_OSC_HAS_OSC (0) 1492 /* @brief Number of OSC external oscillators. */ 1493 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1494 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1495 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 1496 1497 /* PDB module features */ 1498 1499 /* @brief Has DAC support. */ 1500 #define FSL_FEATURE_PDB_HAS_DAC (1) 1501 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1502 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (1) 1503 /* @brief PDB channel number). */ 1504 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1505 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1506 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1507 /* @brief DAC interval trigger number). */ 1508 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (1) 1509 /* @brief Pulse out number). */ 1510 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 1511 1512 /* PMC module features */ 1513 1514 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1515 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1516 /* @brief Has Bandgap Buffer Enable. */ 1517 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1518 /* @brief Has Bandgap Buffer Drive Select. */ 1519 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1520 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1521 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1522 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1523 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1524 /* @brief Has LPO. */ 1525 #define FSL_FEATURE_PMC_HAS_LPO (0) 1526 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1527 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1528 /* @brief Has acknowledge isolation support. */ 1529 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1530 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1531 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1532 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1533 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1534 /* @brief Has PMC_HVDSC1. */ 1535 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1536 /* @brief Has PMC_PARAM. */ 1537 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1538 /* @brief Has PMC_VERID. */ 1539 #define FSL_FEATURE_PMC_HAS_VERID (0) 1540 1541 /* PORT module features */ 1542 1543 /* @brief Has control lock (register bit PCR[LK]). */ 1544 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (0) 1545 /* @brief Has open drain control (register bit PCR[ODE]). */ 1546 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 1547 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1548 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (0) 1549 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1550 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1551 /* @brief Has pull resistor selection available. */ 1552 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1553 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1554 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1555 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1556 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1557 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1558 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1559 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1560 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1561 /* @brief Has separate drive strength register (HDRVE). */ 1562 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1563 /* @brief Has glitch filter (register IOFLT). */ 1564 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1565 /* @brief Defines width of PCR[MUX] field. */ 1566 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1567 /* @brief Has dedicated interrupt vector. */ 1568 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1569 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1570 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1571 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1572 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1573 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1574 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1575 1576 /* RCM module features */ 1577 1578 /* @brief Has Loss-of-Lock Reset support. */ 1579 #define FSL_FEATURE_RCM_HAS_LOL (0) 1580 /* @brief Has Loss-of-Clock Reset support. */ 1581 #define FSL_FEATURE_RCM_HAS_LOC (1) 1582 /* @brief Has JTAG generated Reset support. */ 1583 #define FSL_FEATURE_RCM_HAS_JTAG (0) 1584 /* @brief Has EzPort generated Reset support. */ 1585 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 1586 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1587 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 1588 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1589 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1590 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1591 #define FSL_FEATURE_RCM_HAS_SSRS (0) 1592 /* @brief Has Version ID Register (RCM_VERID). */ 1593 #define FSL_FEATURE_RCM_HAS_VERID (0) 1594 /* @brief Has Parameter Register (RCM_PARAM). */ 1595 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1596 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1597 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1598 /* @brief Width of registers of the RCM. */ 1599 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1600 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1601 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1602 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1603 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1604 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1605 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1606 1607 /* SIM module features */ 1608 1609 /* @brief Has USB FS divider. */ 1610 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1611 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1612 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1613 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1614 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (0) 1615 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1616 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1617 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1618 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1619 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1620 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1621 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1622 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (0) 1623 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1624 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (0) 1625 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1626 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1627 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1628 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1629 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1630 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (0) 1631 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1632 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1633 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1634 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1635 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1636 #define FSL_FEATURE_SIM_OPT_HAS_ODE (1) 1637 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1638 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1639 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1640 #define FSL_FEATURE_SIM_OPT_UART_COUNT (2) 1641 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1642 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (1) 1643 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1644 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (1) 1645 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1646 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1647 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1648 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1649 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1650 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1651 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1652 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1653 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1654 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1655 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1656 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1657 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1658 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1659 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1660 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1661 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1662 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1663 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1664 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1665 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1666 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1667 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1668 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1669 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1670 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1671 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1672 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1673 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1674 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1675 /* @brief Has FTM module(s) configuration. */ 1676 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1677 /* @brief Number of FTM modules. */ 1678 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1679 /* @brief Number of FTM triggers with selectable source. */ 1680 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1681 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1682 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1683 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1684 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (0) 1685 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1686 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1687 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1688 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1689 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1690 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1691 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1692 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1693 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1694 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (2) 1695 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1696 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1697 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1698 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1699 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1700 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (0) 1701 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1702 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1703 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1704 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1705 /* @brief Has TPM module(s) configuration. */ 1706 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1707 /* @brief The highest TPM module index. */ 1708 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1709 /* @brief Has TPM module with index 0. */ 1710 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1711 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1712 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1713 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1714 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1715 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1716 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1717 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1718 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1719 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1720 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1721 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1722 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1723 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1724 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1725 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1726 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (0) 1727 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1728 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (0) 1729 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1730 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1731 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1732 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1733 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1734 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (0) 1735 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1736 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1737 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1738 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (0) 1739 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1740 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (0) 1741 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1742 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (0) 1743 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1744 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1745 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1746 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1747 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1748 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1749 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1750 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1751 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1752 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1753 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1754 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1755 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1756 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1757 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1758 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1759 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1760 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (0) 1761 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1762 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1763 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1764 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (2) 1765 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1766 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (2) 1767 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1768 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1769 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1770 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1771 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1772 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1773 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1774 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1775 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1776 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1777 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1778 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1779 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1780 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1781 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1782 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1783 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1784 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (0) 1785 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1786 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (0) 1787 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1788 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1789 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1790 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (3) 1791 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1792 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (1) 1793 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1794 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (0) 1795 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1796 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1797 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1798 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1799 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1800 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1801 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1802 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1803 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1804 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1805 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1806 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1807 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1808 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (0) 1809 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1810 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1811 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1812 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1813 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1814 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (0) 1815 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1816 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1817 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1818 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (1) 1819 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1820 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1821 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1822 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1823 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1824 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1825 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1826 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (0) 1827 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1828 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (0) 1829 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1830 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (0) 1831 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1832 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (0) 1833 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1834 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (0) 1835 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1836 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1837 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1838 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1839 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1840 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (0) 1841 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1842 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1843 /* @brief Has miscellanious control register (register MCR). */ 1844 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1845 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1846 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1847 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1848 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1849 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1850 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1851 /* @brief Has UIDH registers. */ 1852 #define FSL_FEATURE_SIM_HAS_UIDH (0) 1853 /* @brief Has UIDM registers. */ 1854 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1855 1856 /* SMC module features */ 1857 1858 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1859 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1860 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1861 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1862 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1863 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1864 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1865 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1866 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1867 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1868 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1869 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1870 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1871 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (1) 1872 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1873 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1874 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1875 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1876 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1877 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1878 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1879 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1880 /* @brief Has stop submode. */ 1881 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1882 /* @brief Has stop submode 0(VLLS0). */ 1883 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1884 /* @brief Has stop submode 1(VLLS1). */ 1885 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1886 /* @brief Has stop submode 2(VLLS2). */ 1887 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1888 /* @brief Has SMC_PARAM. */ 1889 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1890 /* @brief Has SMC_VERID. */ 1891 #define FSL_FEATURE_SMC_HAS_VERID (0) 1892 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1893 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1894 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1895 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1896 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1897 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1898 /* @brief Width of SMC registers. */ 1899 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1900 1901 /* DSPI module features */ 1902 1903 #if defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) 1904 /* @brief Receive/transmit FIFO size in number of items. */ 1905 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1906 /* @brief Maximum transfer data width in bits. */ 1907 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1908 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1909 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (5) 1910 /* @brief Number of chip select pins. */ 1911 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (4) 1912 /* @brief Number of CTAR registers. */ 1913 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1914 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1915 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 1916 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1917 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (1) 1918 /* @brief Has 16-bit data transfer support. */ 1919 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1920 /* @brief Has separate DMA RX and TX requests. */ 1921 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1922 #elif defined(CPU_MKV11Z128VLF7) || defined(CPU_MKV11Z128VLH7) || defined(CPU_MKV11Z64VLF7) || defined(CPU_MKV11Z64VLH7) 1923 /* @brief Receive/transmit FIFO size in number of items. */ 1924 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) (4) 1925 /* @brief Maximum transfer data width in bits. */ 1926 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1927 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1928 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (5) 1929 /* @brief Number of chip select pins. */ 1930 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (5) 1931 /* @brief Number of CTAR registers. */ 1932 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1933 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1934 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (0) 1935 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1936 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (1) 1937 /* @brief Has 16-bit data transfer support. */ 1938 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1939 /* @brief Has separate DMA RX and TX requests. */ 1940 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1941 #endif /* defined(CPU_MKV11Z128VFM7) || defined(CPU_MKV11Z128VLC7) || defined(CPU_MKV11Z64VFM7) || defined(CPU_MKV11Z64VLC7) */ 1942 1943 /* SysTick module features */ 1944 1945 /* @brief Systick has external reference clock. */ 1946 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (1) 1947 /* @brief Systick external reference clock is core clock divided by this value. */ 1948 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (16) 1949 1950 /* UART module features */ 1951 1952 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1953 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1954 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1955 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1956 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1957 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1958 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1959 #define FSL_FEATURE_UART_HAS_FIFO (1) 1960 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1961 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1962 /* @brief Infrared (modulation) is supported. */ 1963 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (0) 1964 /* @brief 2 bits long stop bit is available. */ 1965 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1966 /* @brief If 10-bit mode is supported. */ 1967 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1968 /* @brief Baud rate fine adjustment is available. */ 1969 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1970 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1971 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1972 /* @brief Baud rate oversampling is available. */ 1973 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1974 /* @brief Baud rate oversampling is available. */ 1975 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1976 /* @brief Peripheral type. */ 1977 #define FSL_FEATURE_UART_IS_SCI (0) 1978 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1979 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1980 (((x) == UART0) ? (8) : \ 1981 (((x) == UART1) ? (1) : (-1))) 1982 /* @brief Supports two match addresses to filter incoming frames. */ 1983 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1984 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1985 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1986 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1987 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1988 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1989 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1990 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1991 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (0) 1992 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1993 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1994 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1995 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1996 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1997 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1998 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1999 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 2000 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 2001 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 2002 /* @brief Has separate DMA RX and TX requests. */ 2003 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 2004 2005 /* WDOG module features */ 2006 2007 /* @brief Watchdog is available. */ 2008 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 2009 /* @brief Has Wait mode support. */ 2010 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 2011 2012 #endif /* _MKV11Z7_FEATURES_H_ */ 2013 2014
