1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* UART Select, UART0 - UART1. */ 16 /* User needs to provide the implementation of UARTX_GetFreq/UARTX_InitPins/UARTX_DeinitPins for the enabled UART 17 * instance. */ 18 #define RTE_USART0 0 19 #define RTE_USART0_DMA_EN 0 20 #define RTE_USART1 0 21 #define RTE_USART1_DMA_EN 0 22 23 /* UART configuration. */ 24 #define USART_RX_BUFFER_LEN 64 25 #define USART0_RX_BUFFER_ENABLE 0 26 #define USART1_RX_BUFFER_ENABLE 0 27 28 #define RTE_USART0_PIN_INIT UART0_InitPins 29 #define RTE_USART0_PIN_DEINIT UART0_DeinitPins 30 #define RTE_USART0_DMA_TX_CH 0 31 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 32 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 33 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 34 #define RTE_USART0_DMA_RX_CH 1 35 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 36 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 37 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 38 39 #define RTE_USART1_PIN_INIT UART1_InitPins 40 #define RTE_USART1_PIN_DEINIT UART1_DeinitPins 41 #define RTE_USART1_DMA_TX_CH 0 42 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 43 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 44 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 45 #define RTE_USART1_DMA_RX_CH 1 46 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 47 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 48 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 49 50 /* I2C Select, I2C0. */ 51 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 52 */ 53 #define RTE_I2C0 1 54 #define RTE_I2C0_DMA_EN 0 55 56 /*I2C configuration*/ 57 #define RTE_I2C0_Master_DMA_BASE DMA0 58 #define RTE_I2C0_Master_DMA_CH 0 59 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 60 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 61 62 /* SPI Select, DSPI0.*/ 63 /* User needs to provide the implementation of DSPIX_GetFreq/DSPIX_InitPins/DSPIX_DeinitPins for the enabled DSPI 64 * instance. */ 65 #define RTE_SPI0 1 66 #define RTE_SPI0_DMA_EN 0 67 68 /* SPI configuration. */ 69 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 70 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 71 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 72 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 73 #define RTE_SPI0_PIN_INIT DSPI0_InitPins 74 #define RTE_SPI0_PIN_DEINIT DSPI0_DeinitPins 75 #define RTE_SPI0_DMA_TX_CH 0 76 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 77 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 78 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 79 #define RTE_SPI0_DMA_RX_CH 1 80 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 81 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 82 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 83 84 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 85 #define RTE_SPI0_DMA_LINK_CH 2 86 87 #endif /* _RTE_DEVICE_H */ 88
