1 /*
2 ** ###################################################################
3 **     Processors:          MKM14Z128ACHH5
4 **                          MKM14Z64ACHH5
5 **
6 **     Compilers:           Freescale C/C++ for Embedded ARM
7 **                          GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          Keil ARM C/C++ Compiler
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    MKMxxZxxACxx5RM, Rev. 2, 10/2017
13 **     Version:             rev. 1.0, 2014-07-22
14 **     Build:               b201216
15 **
16 **     Abstract:
17 **         Provides a system configuration function and a global variable that
18 **         contains the system frequency. It configures the device and initializes
19 **         the oscillator (PLL) that is part of the microcontroller device.
20 **
21 **     Copyright 2016 Freescale Semiconductor, Inc.
22 **     Copyright 2016-2020 NXP
23 **     All rights reserved.
24 **
25 **     SPDX-License-Identifier: BSD-3-Clause
26 **
27 **     http:                 www.nxp.com
28 **     mail:                 support@nxp.com
29 **
30 **     Revisions:
31 **     - rev. 1.0 (2014-07-22)
32 **         Initial version.
33 **
34 ** ###################################################################
35 */
36 
37 /*!
38  * @file MKM14ZA5
39  * @version 1.0
40  * @date 2014-07-22
41  * @brief Device specific configuration file for MKM14ZA5 (implementation file)
42  *
43  * Provides a system configuration function and a global variable that contains
44  * the system frequency. It configures the device and initializes the oscillator
45  * (PLL) that is part of the microcontroller device.
46  */
47 
48 #include <stdint.h>
49 #include "fsl_device_registers.h"
50 
51 
52 
53 /* ----------------------------------------------------------------------------
54    -- Core clock
55    ---------------------------------------------------------------------------- */
56 
57 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
58 
59 /* ----------------------------------------------------------------------------
60    -- SystemInit()
61    ---------------------------------------------------------------------------- */
62 
SystemInit(void)63 void SystemInit (void) {
64 
65 #if (DISABLE_WDOG)
66   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
67   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
68   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
69   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
70   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
71   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
72                  WDOG_STCTRLH_STOPEN_MASK |
73                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
74                  WDOG_STCTRLH_CLKSRC_MASK |
75                  0x0100U;
76 #endif /* (DISABLE_WDOG) */
77 
78   SystemInitHook();
79 }
80 
81 /* ----------------------------------------------------------------------------
82    -- SystemCoreClockUpdate()
83    ---------------------------------------------------------------------------- */
84 
SystemCoreClockUpdate(void)85 void SystemCoreClockUpdate (void) {
86 
87   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
88   uint16_t Divider;
89 
90   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
91     /* Output of FLL or PLL is selected */
92     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
93       /* FLL is selected */
94       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
95         /* External reference clock is selected */
96         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
97           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
98         } else {
99           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
100         }
101         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
102           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
103           case 0x38U:
104             Divider = 1536U;
105             break;
106           case 0x30U:
107             Divider = 1280U;
108             break;
109           default:
110             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
111             break;
112           }
113         } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
114           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
115         }
116         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
117       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
118         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
119       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
120       /* Select correct multiplier to calculate the MCG output clock  */
121       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
122         case 0x00U:
123           MCGOUTClock *= 640U;
124           break;
125         case 0x20U:
126           MCGOUTClock *= 1280U;
127           break;
128         case 0x40U:
129           MCGOUTClock *= 1920U;
130           break;
131         case 0x60U:
132           MCGOUTClock *= 2560U;
133           break;
134         case 0x80U:
135           MCGOUTClock *= 732U;
136           break;
137         case 0xA0U:
138           MCGOUTClock *= 1464U;
139           break;
140         case 0xC0U:
141           MCGOUTClock *= 2197U;
142           break;
143         case 0xE0U:
144           MCGOUTClock *= 2929U;
145           break;
146         default:
147           MCGOUTClock *= 640U;
148           break;
149       }
150     }
151     else {/* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
152       /* PLL is selected */
153       if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x00U) {
154         /* RTC 32 kHz oscillator selected */
155         MCGOUTClock = CPU_XTAL32k_CLK_HZ;
156       } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x40U) {
157         /* 32kHz IRC selected */
158         MCGOUTClock = CPU_INT_SLOW_CLK_HZ;
159       } else if ((MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0x80U) {
160         /* FLL FRDIV selected */
161         if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
162           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
163         } else {
164           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
165         }
166         if (((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) && ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
167           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
168           case 0x38U:
169             Divider = 1536U;
170             break;
171           case 0x30U:
172             Divider = 1280U;
173             break;
174           default:
175             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
176             break;
177           }
178         } else {/* ((MCG->C2 & MCG_C2_RANGE0_MASK) != 0x00U) */
179           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
180         }
181         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
182       } else { /* (MCG->C7 & MCG_C7_PLL32KREFSEL_MASK) == 0xB0U */
183         /* Reserved value */
184         return;
185       }
186       MCGOUTClock *= 375U; /* Calculate the MCG output clock */
187     }
188   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
189     /* Internal reference clock is selected */
190     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
191       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
192     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
193       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
194       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
195     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
196   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
197     /* External reference clock is selected */
198     if ((MCG->C7 & MCG_C7_OSCSEL_MASK) != 0x00U) {
199       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
200     } else {
201       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
202     }
203   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
204     /* Reserved value */
205     return;
206   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
207   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_SYSDIV_MASK) >> SIM_CLKDIV1_SYSDIV_SHIFT)));
208 }
209 
210 /* ----------------------------------------------------------------------------
211    -- SystemInitHook()
212    ---------------------------------------------------------------------------- */
213 
SystemInitHook(void)214 __attribute__ ((weak)) void SystemInitHook (void) {
215   /* Void implementation of the weak function. */
216 }
217