1 /*
2 ** ###################################################################
3 ** Processors: MKL27Z32VDA4
4 ** MKL27Z32VFM4
5 ** MKL27Z32VFT4
6 ** MKL27Z32VLH4
7 ** MKL27Z32VMP4
8 ** MKL27Z64VDA4
9 ** MKL27Z64VFM4
10 ** MKL27Z64VFT4
11 ** MKL27Z64VLH4
12 ** MKL27Z64VMP4
13 **
14 ** Compilers: Keil ARM C/C++ Compiler
15 ** Freescale C/C++ for Embedded ARM
16 ** GNU C Compiler
17 ** IAR ANSI C/C++ Compiler for ARM
18 ** MCUXpresso Compiler
19 **
20 ** Reference manual: KL27P64M48SF2RM, Rev. 1, Sep 2014
21 ** Version: rev. 1.6, 2016-06-24
22 ** Build: b180801
23 **
24 ** Abstract:
25 ** Provides a system configuration function and a global variable that
26 ** contains the system frequency. It configures the device and initializes
27 ** the oscillator (PLL) that is part of the microcontroller device.
28 **
29 ** Copyright 2016 Freescale Semiconductor, Inc.
30 ** Copyright 2016-2018 NXP
31 **
32 ** SPDX-License-Identifier: BSD-3-Clause
33 **
34 ** http: www.nxp.com
35 ** mail: support@nxp.com
36 **
37 ** Revisions:
38 ** - rev. 1.0 (2014-05-12)
39 ** Initial version.
40 ** - rev. 1.1 (2014-07-10)
41 ** UART0 - UART0 module renamed to UART2.
42 ** - rev. 1.2 (2014-08-12)
43 ** CRC - CRC register renamed to DATA.
44 ** - rev. 1.3 (2014-09-02)
45 ** USB - USB0_CTL0 was renamed to USB0_OTGCTL register.
46 ** USB - USB0_CTL1 was renamed to USB0_CTL register.
47 ** USB - Two new bitfields (STOP_ACK_DLY_EN, AHB_DLY_EN) was added to the USB0_KEEP_ALIVE_CTRL register.
48 ** - rev. 1.4 (2014-09-22)
49 ** FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
50 ** SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
51 ** SIM - Removed bitfield DIEID in SDID register.
52 ** UART2 - Removed ED register.
53 ** UART2 - Removed MODEM register.
54 ** UART2 - Removed IR register.
55 ** UART2 - Removed PFIFO register.
56 ** UART2 - Removed CFIFO register.
57 ** UART2 - Removed SFIFO register.
58 ** UART2 - Removed TWFIFO register.
59 ** UART2 - Removed TCFIFO register.
60 ** UART2 - Removed RWFIFO register.
61 ** UART2 - Removed RCFIFO register.
62 ** USB - Removed bitfield REG_EN in CLK_RECOVER_IRC_EN register.
63 ** USB - Renamed USBEN bitfield of USB0_CTL was renamed to USBENSOFEN.
64 ** - rev. 1.5 (2016-02-02)
65 ** FGPIO - Add FGPIO registers.
66 ** - rev. 1.6 (2016-06-24)
67 ** USB - OTGCTL register was removed.
68 ** USB - Bit RESUME was added in CTL register.
69 **
70 ** ###################################################################
71 */
72
73 /*!
74 * @file MKL27Z644
75 * @version 1.6
76 * @date 2016-06-24
77 * @brief Device specific configuration file for MKL27Z644 (implementation file)
78 *
79 * Provides a system configuration function and a global variable that contains
80 * the system frequency. It configures the device and initializes the oscillator
81 * (PLL) that is part of the microcontroller device.
82 */
83
84 #include <stdint.h>
85 #include "fsl_device_registers.h"
86
87
88
89 /* ----------------------------------------------------------------------------
90 -- Core clock
91 ---------------------------------------------------------------------------- */
92
93 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
94
95 /* ----------------------------------------------------------------------------
96 -- SystemInit()
97 ---------------------------------------------------------------------------- */
98
SystemInit(void)99 void SystemInit (void) {
100
101 #if (ACK_ISOLATION)
102 if((PMC->REGSC & PMC_REGSC_ACKISO_MASK) != 0U) {
103 PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
104 }
105 #endif
106 #if (DISABLE_WDOG)
107 /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
108 SIM->COPC = (uint32_t)0x00u;
109 #endif /* (DISABLE_WDOG) */
110
111 SystemInitHook();
112 }
113
114 /* ----------------------------------------------------------------------------
115 -- SystemCoreClockUpdate()
116 ---------------------------------------------------------------------------- */
117
SystemCoreClockUpdate(void)118 void SystemCoreClockUpdate (void) {
119
120 uint32_t MCGOUTClock; /* Variable to store output clock frequency of the MCG module */
121 uint16_t Divider;
122
123 if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
124 /* High internal reference clock is selected */
125 MCGOUTClock = CPU_INT_FAST_CLK_HZ; /* Fast internal reference clock selected */
126 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
127 /* Internal reference clock is selected */
128 Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
129 MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider); /* Slow internal reference clock 8MHz selected */
130 } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
131 /* External reference clock is selected */
132 MCGOUTClock = CPU_XTAL_CLK_HZ;
133 } else {
134 /* Reserved value */
135 return;
136 } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
137 SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
138
139 }
140
141 /* ----------------------------------------------------------------------------
142 -- SystemInitHook()
143 ---------------------------------------------------------------------------- */
144
SystemInitHook(void)145 __attribute__ ((weak)) void SystemInitHook (void) {
146 /* Void implementation of the weak function. */
147 }
148
