1 /*
2 ** ###################################################################
3 **     Processors:          MKL17Z32VDA4
4 **                          MKL17Z32VFM4
5 **                          MKL17Z32VFT4
6 **                          MKL17Z32VLH4
7 **                          MKL17Z32VMP4
8 **                          MKL17Z64VDA4
9 **                          MKL17Z64VFM4
10 **                          MKL17Z64VFT4
11 **                          MKL17Z64VLH4
12 **                          MKL17Z64VMP4
13 **
14 **     Compilers:           Keil ARM C/C++ Compiler
15 **                          Freescale C/C++ for Embedded ARM
16 **                          GNU C Compiler
17 **                          IAR ANSI C/C++ Compiler for ARM
18 **                          MCUXpresso Compiler
19 **
20 **     Reference manual:    KL17P64M48SF2RM, Rev. 1, Sep 2014
21 **     Version:             rev. 1.4, 2016-02-02
22 **     Build:               b180801
23 **
24 **     Abstract:
25 **         Provides a system configuration function and a global variable that
26 **         contains the system frequency. It configures the device and initializes
27 **         the oscillator (PLL) that is part of the microcontroller device.
28 **
29 **     Copyright 2016 Freescale Semiconductor, Inc.
30 **     Copyright 2016-2018 NXP
31 **
32 **     SPDX-License-Identifier: BSD-3-Clause
33 **
34 **     http:                 www.nxp.com
35 **     mail:                 support@nxp.com
36 **
37 **     Revisions:
38 **     - rev. 1.0 (2014-05-12)
39 **         Initial version.
40 **     - rev. 1.1 (2014-07-10)
41 **         UART0 - UART0 module renamed to UART2.
42 **     - rev. 1.2 (2014-08-12)
43 **         CRC - CRC register renamed to DATA.
44 **     - rev. 1.3 (2014-09-22)
45 **         FLEXIO - Offsets of the SHIFTBUFBIS registers were interchanged with offsets of the SHIFTBUFBBS registers.
46 **         SIM - Changed bitfield value MCGIRCLK to LIRC_CLK of bitfield CLKOUTSEL in SOPT2 register.
47 **         SIM - Removed bitfield DIEID in SDID register.
48 **         UART2 - Removed ED register.
49 **         UART2 - Removed MODEM register.
50 **         UART2 - Removed IR register.
51 **         UART2 - Removed PFIFO register.
52 **         UART2 - Removed CFIFO register.
53 **         UART2 - Removed SFIFO register.
54 **         UART2 - Removed TWFIFO register.
55 **         UART2 - Removed TCFIFO register.
56 **         UART2 - Removed RWFIFO register.
57 **         UART2 - Removed RCFIFO register.
58 **     - rev. 1.4 (2016-02-02)
59 **         FGPIO - Add FGPIO registers.
60 **
61 ** ###################################################################
62 */
63 
64 /*!
65  * @file MKL17Z644
66  * @version 1.4
67  * @date 2016-02-02
68  * @brief Device specific configuration file for MKL17Z644 (implementation file)
69  *
70  * Provides a system configuration function and a global variable that contains
71  * the system frequency. It configures the device and initializes the oscillator
72  * (PLL) that is part of the microcontroller device.
73  */
74 
75 #include <stdint.h>
76 #include "fsl_device_registers.h"
77 
78 
79 
80 /* ----------------------------------------------------------------------------
81    -- Core clock
82    ---------------------------------------------------------------------------- */
83 
84 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
85 
86 /* ----------------------------------------------------------------------------
87    -- SystemInit()
88    ---------------------------------------------------------------------------- */
89 
SystemInit(void)90 void SystemInit (void) {
91 
92 #if (ACK_ISOLATION)
93   if((PMC->REGSC &  PMC_REGSC_ACKISO_MASK) != 0U) {
94     PMC->REGSC |= PMC_REGSC_ACKISO_MASK; /* VLLSx recovery */
95   }
96 #endif
97 #if (DISABLE_WDOG)
98   /* SIM->COPC: ?=0,COPCLKSEL=0,COPDBGEN=0,COPSTPEN=0,COPT=0,COPCLKS=0,COPW=0 */
99   SIM->COPC = (uint32_t)0x00u;
100 #endif /* (DISABLE_WDOG) */
101 
102   SystemInitHook();
103 }
104 
105 /* ----------------------------------------------------------------------------
106    -- SystemCoreClockUpdate()
107    ---------------------------------------------------------------------------- */
108 
SystemCoreClockUpdate(void)109 void SystemCoreClockUpdate (void) {
110 
111   uint32_t MCGOUTClock;                                 /* Variable to store output clock frequency of the MCG module */
112   uint16_t Divider;
113 
114   if ((MCG->S & MCG_S_CLKST_MASK) == 0x00U) {
115     /* High internal reference clock is selected */
116     MCGOUTClock = CPU_INT_FAST_CLK_HZ;                                  /* Fast internal reference clock selected */
117   } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x04U) {
118     /* Internal reference clock is selected */
119     Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
120     MCGOUTClock = (uint32_t) (CPU_INT_SLOW_CLK_HZ / Divider);           /* Slow internal reference clock 8MHz selected */
121   } else if ((MCG->S & MCG_S_CLKST_MASK) == 0x08U) {
122     /* External reference clock is selected */
123     MCGOUTClock = CPU_XTAL_CLK_HZ;
124   } else {
125     /* Reserved value */
126     return;
127   } /* (!((MCG->S & MCG_S_CLKST_MASK) == 0x08U)) */
128   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
129 
130 }
131 
132 /* ----------------------------------------------------------------------------
133    -- SystemInitHook()
134    ---------------------------------------------------------------------------- */
135 
SystemInitHook(void)136 __attribute__ ((weak)) void SystemInitHook (void) {
137   /* Void implementation of the weak function. */
138 }
139