1 /*
2 ** ###################################################################
3 **     Processors:          MKE17Z128VLF7
4 **                          MKE17Z128VLH7
5 **                          MKE17Z128VLL7
6 **                          MKE17Z256VLF7
7 **                          MKE17Z256VLH7
8 **                          MKE17Z256VLL7
9 **
10 **     Compilers:           Freescale C/C++ for Embedded ARM
11 **                          GNU C Compiler
12 **                          IAR ANSI C/C++ Compiler for ARM
13 **                          Keil ARM C/C++ Compiler
14 **                          MCUXpresso Compiler
15 **
16 **     Reference manual:    KE1xZP100M72SF1RM, Rev. 1, Jun. 2021
17 **     Version:             rev. 3.0, 2021-10-08
18 **     Build:               b211108
19 **
20 **     Abstract:
21 **         Provides a system configuration function and a global variable that
22 **         contains the system frequency. It configures the device and initializes
23 **         the oscillator (PLL) that is part of the microcontroller device.
24 **
25 **     Copyright 2016 Freescale Semiconductor, Inc.
26 **     Copyright 2016-2021 NXP
27 **     All rights reserved.
28 **
29 **     SPDX-License-Identifier: BSD-3-Clause
30 **
31 **     http:                 www.nxp.com
32 **     mail:                 support@nxp.com
33 **
34 **     Revisions:
35 **     - rev. 1.0 (2020-12-10)
36 **         Initial version.
37 **     - rev. 2.0 (2021-06-25)
38 **         Based on Rev.1 RM.
39 **     - rev. 3.0 (2021-10-08)
40 **         Add 48LQFP parts.
41 **
42 ** ###################################################################
43 */
44 
45 /*!
46  * @file MKE17Z7
47  * @version 3.0
48  * @date 2021-10-08
49  * @brief Device specific configuration file for MKE17Z7 (implementation file)
50  *
51  * Provides a system configuration function and a global variable that contains
52  * the system frequency. It configures the device and initializes the oscillator
53  * (PLL) that is part of the microcontroller device.
54  */
55 
56 #include <stdint.h>
57 #include "fsl_device_registers.h"
58 
59 
60 
61 /* ----------------------------------------------------------------------------
62    -- Core clock
63    ---------------------------------------------------------------------------- */
64 
65 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
66 
67 /* ----------------------------------------------------------------------------
68    -- SystemInit()
69    ---------------------------------------------------------------------------- */
70 
SystemInit(void)71 void SystemInit (void) {
72 
73 #if (DISABLE_WDOG)
74   if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U)
75   {
76       WDOG->CNT = WDOG_UPDATE_KEY;
77   }
78   else
79   {
80       WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
81       WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
82   }
83   WDOG->TOVAL = 0xFFFFU;
84   WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
85 #endif /* (DISABLE_WDOG) */
86 
87   SystemInitHook();
88 }
89 
90 /* ----------------------------------------------------------------------------
91    -- SystemCoreClockUpdate()
92    ---------------------------------------------------------------------------- */
93 
SystemCoreClockUpdate(void)94 void SystemCoreClockUpdate (void) {
95 
96   uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
97   uint16_t Divider;
98   Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U);
99 
100   switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
101     case 0x1:
102       /* System OSC */
103       SCGOUTClock = CPU_XTAL_CLK_HZ;
104       break;
105     case 0x2:
106       /* Slow IRC */
107       SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U);
108       break;
109     case 0x3:
110       /* Fast IRC */
111       SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
112       break;
113     case 0x5:
114       /* Low Power FLL */
115       SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U;
116       break;
117     default:
118       SCGOUTClock = 0U;
119       break;
120   }
121   SystemCoreClock = (SCGOUTClock / Divider);
122 }
123 
124 /* ----------------------------------------------------------------------------
125    -- SystemInitHook()
126    ---------------------------------------------------------------------------- */
127 
SystemInitHook(void)128 __attribute__ ((weak)) void SystemInitHook (void) {
129   /* Void implementation of the weak function. */
130 }
131