1 /*
2 ** ###################################################################
3 **     Processors:          MKE16Z32VLD4
4 **                          MKE16Z32VLF4
5 **                          MKE16Z64VLD4
6 **                          MKE16Z64VLF4
7 **
8 **     Compilers:           Freescale C/C++ for Embedded ARM
9 **                          GNU C Compiler
10 **                          IAR ANSI C/C++ Compiler for ARM
11 **                          Keil ARM C/C++ Compiler
12 **                          MCUXpresso Compiler
13 **
14 **     Reference manual:    KE1xZP48M48SF0RM, Rev. 1, Sep. 2018
15 **     Version:             rev. 3.0, 2020-01-22
16 **     Build:               b201012
17 **
18 **     Abstract:
19 **         Provides a system configuration function and a global variable that
20 **         contains the system frequency. It configures the device and initializes
21 **         the oscillator (PLL) that is part of the microcontroller device.
22 **
23 **     Copyright 2016 Freescale Semiconductor, Inc.
24 **     Copyright 2016-2020 NXP
25 **     All rights reserved.
26 **
27 **     SPDX-License-Identifier: BSD-3-Clause
28 **
29 **     http:                 www.nxp.com
30 **     mail:                 support@nxp.com
31 **
32 **     Revisions:
33 **     - rev. 1.0 (2018-05-09)
34 **         Initial version.
35 **     - rev. 2.0 (2018-09-17)
36 **         Based on rev1 RM.
37 **     - rev. 3.0 (2020-01-22)
38 **         Add 40 pins part numbers.
39 **
40 ** ###################################################################
41 */
42 
43 /*!
44  * @file MKE16Z4
45  * @version 3.0
46  * @date 2020-01-22
47  * @brief Device specific configuration file for MKE16Z4 (implementation file)
48  *
49  * Provides a system configuration function and a global variable that contains
50  * the system frequency. It configures the device and initializes the oscillator
51  * (PLL) that is part of the microcontroller device.
52  */
53 
54 #include <stdint.h>
55 #include "fsl_device_registers.h"
56 
57 
58 
59 /* ----------------------------------------------------------------------------
60    -- Core clock
61    ---------------------------------------------------------------------------- */
62 
63 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
64 
65 /* ----------------------------------------------------------------------------
66    -- SystemInit()
67    ---------------------------------------------------------------------------- */
68 
SystemInit(void)69 void SystemInit (void) {
70 
71 #if (DISABLE_WDOG)
72   if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U)
73   {
74       WDOG->CNT = WDOG_UPDATE_KEY;
75   }
76   else
77   {
78       WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
79       WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
80   }
81   WDOG->TOVAL = 0xFFFFU;
82   WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
83 #endif /* (DISABLE_WDOG) */
84 
85   SystemInitHook();
86 }
87 
88 /* ----------------------------------------------------------------------------
89    -- SystemCoreClockUpdate()
90    ---------------------------------------------------------------------------- */
91 
SystemCoreClockUpdate(void)92 void SystemCoreClockUpdate (void) {
93 
94   uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
95   uint16_t Divider;
96   Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U);
97 
98   switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
99     case 0x1:
100       /* System OSC */
101       SCGOUTClock = CPU_XTAL_CLK_HZ;
102       break;
103     case 0x2:
104       /* Slow IRC */
105       SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U);
106       break;
107     case 0x3:
108       /* Fast IRC */
109       SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
110       break;
111     case 0x5:
112       /* Low Power FLL */
113       SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U;
114       break;
115     default:
116       SCGOUTClock = 0U;
117       break;
118   }
119   SystemCoreClock = (SCGOUTClock / Divider);
120 
121 }
122 
123 /* ----------------------------------------------------------------------------
124    -- SystemInitHook()
125    ---------------------------------------------------------------------------- */
126 
SystemInitHook(void)127 __attribute__ ((weak)) void SystemInitHook (void) {
128   /* Void implementation of the weak function. */
129 }
130