1 /* 2 ** ################################################################### 3 ** Version: rev. 1.0, 2018-05-09 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2018-05-09) 20 ** Initial version. 21 ** 22 ** ################################################################### 23 */ 24 25 #ifndef _MKE16Z4_FEATURES_H_ 26 #define _MKE16Z4_FEATURES_H_ 27 28 /* SOC module features */ 29 30 /* @brief ACMP availability on the SoC. */ 31 #define FSL_FEATURE_SOC_ACMP_COUNT (1) 32 /* @brief ADC12 availability on the SoC. */ 33 #define FSL_FEATURE_SOC_ADC12_COUNT (1) 34 /* @brief CRC availability on the SoC. */ 35 #define FSL_FEATURE_SOC_CRC_COUNT (1) 36 /* @brief EWM availability on the SoC. */ 37 #define FSL_FEATURE_SOC_EWM_COUNT (1) 38 /* @brief FGPIO availability on the SoC. */ 39 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 40 /* @brief FTFA availability on the SoC. */ 41 #define FSL_FEATURE_SOC_FTFA_COUNT (1) 42 /* @brief FTM availability on the SoC. */ 43 #define FSL_FEATURE_SOC_FTM_COUNT (2) 44 /* @brief GPIO availability on the SoC. */ 45 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 46 /* @brief LPI2C availability on the SoC. */ 47 #define FSL_FEATURE_SOC_LPI2C_COUNT (1) 48 /* @brief LPIT availability on the SoC. */ 49 #define FSL_FEATURE_SOC_LPIT_COUNT (1) 50 /* @brief LPSPI availability on the SoC. */ 51 #define FSL_FEATURE_SOC_LPSPI_COUNT (1) 52 /* @brief LPTMR availability on the SoC. */ 53 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 54 /* @brief LPUART availability on the SoC. */ 55 #define FSL_FEATURE_SOC_LPUART_COUNT (3) 56 /* @brief MCM availability on the SoC. */ 57 #define FSL_FEATURE_SOC_MCM_COUNT (1) 58 /* @brief MMDVSQ availability on the SoC. */ 59 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) 60 /* @brief MSCAN availability on the SoC. */ 61 #define FSL_FEATURE_SOC_MSCAN_COUNT (1) 62 /* @brief MTB availability on the SoC. */ 63 #define FSL_FEATURE_SOC_MTB_COUNT (1) 64 /* @brief MTBDWT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 66 /* @brief PCC availability on the SoC. */ 67 #define FSL_FEATURE_SOC_PCC_COUNT (1) 68 /* @brief PDB availability on the SoC. */ 69 #define FSL_FEATURE_SOC_PDB_COUNT (1) 70 /* @brief PMC availability on the SoC. */ 71 #define FSL_FEATURE_SOC_PMC_COUNT (1) 72 /* @brief PORT availability on the SoC. */ 73 #define FSL_FEATURE_SOC_PORT_COUNT (5) 74 /* @brief PWT availability on the SoC. */ 75 #define FSL_FEATURE_SOC_PWT_COUNT (1) 76 /* @brief RCM availability on the SoC. */ 77 #define FSL_FEATURE_SOC_RCM_COUNT (1) 78 /* @brief ROM availability on the SoC. */ 79 #define FSL_FEATURE_SOC_ROM_COUNT (1) 80 /* @brief RTC availability on the SoC. */ 81 #define FSL_FEATURE_SOC_RTC_COUNT (1) 82 /* @brief SCG availability on the SoC. */ 83 #define FSL_FEATURE_SOC_SCG_COUNT (1) 84 /* @brief SIM availability on the SoC. */ 85 #define FSL_FEATURE_SOC_SIM_COUNT (1) 86 /* @brief SMC availability on the SoC. */ 87 #define FSL_FEATURE_SOC_SMC_COUNT (1) 88 /* @brief TRGMUX availability on the SoC. */ 89 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) 90 /* @brief TSI availability on the SoC. */ 91 #define FSL_FEATURE_SOC_TSI_COUNT (1) 92 /* @brief WDOG availability on the SoC. */ 93 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 94 95 /* ADC12 module features */ 96 97 /* @brief Has DMA support (bit SC2[DMAEN]. */ 98 #define FSL_FEATURE_ADC12_HAS_DMA_SUPPORT (0) 99 /* @brief Conversion control count (related to number of registers SC1n and Rn). */ 100 #define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (4) 101 102 /* ACMP module features */ 103 104 /* @brief Has CMP_C3. */ 105 #define FSL_FEATURE_ACMP_HAS_C3_REG (0) 106 /* @brief Has C0 LINKEN Bit */ 107 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (0) 108 /* @brief Has C0 OFFSET Bit */ 109 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (1) 110 /* @brief Has C1 INPSEL Bit */ 111 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (1) 112 /* @brief Has C1 INNSEL Bit */ 113 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (1) 114 /* @brief Has C1 DACOE Bit */ 115 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (0) 116 /* @brief Has C1 DMODE Bit */ 117 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (0) 118 /* @brief Has C2 RRE Bit */ 119 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (1) 120 121 /* CRC module features */ 122 123 /* @brief Has data register with name CRC */ 124 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 125 126 /* EWM module features */ 127 128 /* @brief Has clock select (register CLKCTRL). */ 129 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 130 /* @brief Has clock prescaler (register CLKPRESCALER). */ 131 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 132 133 /* FGPIO module features */ 134 135 /* No feature definitions */ 136 137 /* FLASH module features */ 138 139 #if defined(CPU_MKE16Z32VLD4) || defined(CPU_MKE16Z32VLF4) 140 /* @brief Is of type FTFA. */ 141 #define FSL_FEATURE_FLASH_IS_FTFA (1) 142 /* @brief Is of type FTFE. */ 143 #define FSL_FEATURE_FLASH_IS_FTFE (0) 144 /* @brief Is of type FTFL. */ 145 #define FSL_FEATURE_FLASH_IS_FTFL (0) 146 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 147 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 148 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 149 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 150 /* @brief Has EEPROM region protection (register FEPROT). */ 151 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 152 /* @brief Has data flash region protection (register FDPROT). */ 153 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 154 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 155 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 156 /* @brief Has flash cache control in FMC module. */ 157 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 158 /* @brief Has flash cache control in MCM module. */ 159 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 160 /* @brief Has flash cache control in MSCM module. */ 161 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 162 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 163 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 164 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 165 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 166 /* @brief P-Flash start address. */ 167 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 168 /* @brief P-Flash block count. */ 169 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 170 /* @brief P-Flash block size. */ 171 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (32768) 172 /* @brief P-Flash sector size. */ 173 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 174 /* @brief P-Flash write unit size. */ 175 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 176 /* @brief P-Flash data path width. */ 177 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 178 /* @brief P-Flash block swap feature. */ 179 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 180 /* @brief P-Flash protection region count. */ 181 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 182 /* @brief Has FlexNVM memory. */ 183 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 184 /* @brief Has FlexNVM alias. */ 185 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 186 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 187 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 188 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 189 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 190 /* @brief FlexNVM block count. */ 191 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 192 /* @brief FlexNVM block size. */ 193 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 194 /* @brief FlexNVM sector size. */ 195 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 196 /* @brief FlexNVM write unit size. */ 197 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 198 /* @brief FlexNVM data path width. */ 199 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 200 /* @brief Has FlexRAM memory. */ 201 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 202 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 203 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 204 /* @brief FlexRAM size. */ 205 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 206 /* @brief Has 0x00 Read 1s Block command. */ 207 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 208 /* @brief Has 0x01 Read 1s Section command. */ 209 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 210 /* @brief Has 0x02 Program Check command. */ 211 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 212 /* @brief Has 0x03 Read Resource command. */ 213 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 214 /* @brief Has 0x06 Program Longword command. */ 215 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 216 /* @brief Has 0x07 Program Phrase command. */ 217 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 218 /* @brief Has 0x08 Erase Flash Block command. */ 219 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 220 /* @brief Has 0x09 Erase Flash Sector command. */ 221 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 222 /* @brief Has 0x0B Program Section command. */ 223 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 224 /* @brief Has 0x40 Read 1s All Blocks command. */ 225 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 226 /* @brief Has 0x41 Read Once command. */ 227 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 228 /* @brief Has 0x43 Program Once command. */ 229 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 230 /* @brief Has 0x44 Erase All Blocks command. */ 231 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 232 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 233 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 234 /* @brief Has 0x46 Swap Control command. */ 235 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 236 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 237 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 238 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 239 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 240 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 241 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 242 /* @brief Has 0x80 Program Partition command. */ 243 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 244 /* @brief Has 0x81 Set FlexRAM Function command. */ 245 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 246 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 247 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 248 /* @brief P-Flash Erase sector command address alignment. */ 249 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 250 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 251 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 252 /* @brief P-Flash Read resource command address alignment. */ 253 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 254 /* @brief P-Flash Program check command address alignment. */ 255 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 256 /* @brief P-Flash Program check command address alignment. */ 257 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 258 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 259 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 260 /* @brief FlexNVM Erase sector command address alignment. */ 261 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 262 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 263 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 264 /* @brief FlexNVM Read resource command address alignment. */ 265 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 266 /* @brief FlexNVM Program check command address alignment. */ 267 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 268 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 269 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 270 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 271 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 272 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 273 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 274 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 275 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 276 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 277 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 278 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 279 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 280 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 281 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 282 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 283 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 284 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 285 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 286 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 287 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 288 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 289 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 290 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 291 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 292 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 293 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 294 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 295 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 296 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 297 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 298 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 299 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 300 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 301 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 302 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 303 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 304 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 305 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 306 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 307 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 308 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 309 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 310 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 311 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 312 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 313 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 314 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 315 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 316 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 317 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 318 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 319 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 320 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 321 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 322 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 323 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 324 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 325 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 326 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 327 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 328 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 329 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 330 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 331 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 332 #elif defined(CPU_MKE16Z64VLD4) || defined(CPU_MKE16Z64VLF4) 333 /* @brief Is of type FTFA. */ 334 #define FSL_FEATURE_FLASH_IS_FTFA (1) 335 /* @brief Is of type FTFE. */ 336 #define FSL_FEATURE_FLASH_IS_FTFE (0) 337 /* @brief Is of type FTFL. */ 338 #define FSL_FEATURE_FLASH_IS_FTFL (0) 339 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 340 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (0) 341 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 342 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 343 /* @brief Has EEPROM region protection (register FEPROT). */ 344 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (0) 345 /* @brief Has data flash region protection (register FDPROT). */ 346 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (0) 347 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 348 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 349 /* @brief Has flash cache control in FMC module. */ 350 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 351 /* @brief Has flash cache control in MCM module. */ 352 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 353 /* @brief Has flash cache control in MSCM module. */ 354 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 355 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 356 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 357 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 358 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 359 /* @brief P-Flash start address. */ 360 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 361 /* @brief P-Flash block count. */ 362 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 363 /* @brief P-Flash block size. */ 364 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (65536) 365 /* @brief P-Flash sector size. */ 366 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (1024) 367 /* @brief P-Flash write unit size. */ 368 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (4) 369 /* @brief P-Flash data path width. */ 370 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (4) 371 /* @brief P-Flash block swap feature. */ 372 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 373 /* @brief P-Flash protection region count. */ 374 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 375 /* @brief Has FlexNVM memory. */ 376 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 377 /* @brief Has FlexNVM alias. */ 378 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 379 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 381 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 383 /* @brief FlexNVM block count. */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 385 /* @brief FlexNVM block size. */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 387 /* @brief FlexNVM sector size. */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 389 /* @brief FlexNVM write unit size. */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 391 /* @brief FlexNVM data path width. */ 392 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 393 /* @brief Has FlexRAM memory. */ 394 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (0) 395 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 396 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x00000000) 397 /* @brief FlexRAM size. */ 398 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (0) 399 /* @brief Has 0x00 Read 1s Block command. */ 400 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (0) 401 /* @brief Has 0x01 Read 1s Section command. */ 402 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 403 /* @brief Has 0x02 Program Check command. */ 404 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 405 /* @brief Has 0x03 Read Resource command. */ 406 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 407 /* @brief Has 0x06 Program Longword command. */ 408 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (1) 409 /* @brief Has 0x07 Program Phrase command. */ 410 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (0) 411 /* @brief Has 0x08 Erase Flash Block command. */ 412 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (0) 413 /* @brief Has 0x09 Erase Flash Sector command. */ 414 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 415 /* @brief Has 0x0B Program Section command. */ 416 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (0) 417 /* @brief Has 0x40 Read 1s All Blocks command. */ 418 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 419 /* @brief Has 0x41 Read Once command. */ 420 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 421 /* @brief Has 0x43 Program Once command. */ 422 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 423 /* @brief Has 0x44 Erase All Blocks command. */ 424 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 425 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 426 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 427 /* @brief Has 0x46 Swap Control command. */ 428 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 429 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 430 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 431 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 432 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 433 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 434 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 435 /* @brief Has 0x80 Program Partition command. */ 436 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 437 /* @brief Has 0x81 Set FlexRAM Function command. */ 438 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 439 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 440 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (4) 441 /* @brief P-Flash Erase sector command address alignment. */ 442 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (4) 443 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 444 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (4) 445 /* @brief P-Flash Read resource command address alignment. */ 446 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (4) 447 /* @brief P-Flash Program check command address alignment. */ 448 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 449 /* @brief P-Flash Program check command address alignment. */ 450 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 451 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 452 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 453 /* @brief FlexNVM Erase sector command address alignment. */ 454 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 455 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 456 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 457 /* @brief FlexNVM Read resource command address alignment. */ 458 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 459 /* @brief FlexNVM Program check command address alignment. */ 460 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 461 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 462 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 463 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 464 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 465 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 466 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 467 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 468 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 469 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 470 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 471 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 472 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 473 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 474 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 475 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 476 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 477 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 478 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 479 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 480 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 481 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 482 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 483 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 484 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 485 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 486 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 487 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 488 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 489 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 490 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 491 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 492 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 493 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 494 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 495 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 496 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 497 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 498 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 499 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 500 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0xFFFF) 501 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 502 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0xFFFF) 503 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 504 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0xFFFF) 505 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 506 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0xFFFF) 507 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 508 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0xFFFF) 509 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 510 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0xFFFF) 511 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 512 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0xFFFF) 513 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 514 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 515 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 516 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 517 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 518 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 519 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 520 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 521 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 522 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 523 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 524 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0xFFFF) 525 #endif /* defined(CPU_MKE16Z32VLD4) || defined(CPU_MKE16Z32VLF4) */ 526 527 /* FTM module features */ 528 529 /* @brief Number of channels. */ 530 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 531 (((x) == FTM0) ? (6) : \ 532 (((x) == FTM1) ? (2) : (-1))) 533 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 534 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 535 /* @brief Has extended deadtime value. */ 536 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 537 /* @brief Enable pwm output for the module. */ 538 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1) 539 /* @brief Has half-cycle reload for the module. */ 540 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1) 541 /* @brief Has reload interrupt. */ 542 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1) 543 /* @brief Has reload initialization trigger. */ 544 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1) 545 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 546 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (0) 547 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 548 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 549 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 550 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 551 /* @brief If instance has only TPM function. */ 552 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 553 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 554 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (1) 555 556 /* GPIO module features */ 557 558 /* @brief Has GPIO attribute checker register (GACR). */ 559 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 560 561 /* LPI2C module features */ 562 563 /* @brief Has separate DMA RX and TX requests. */ 564 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 565 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 566 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 567 568 /* LPIT module features */ 569 570 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 571 #define FSL_FEATURE_LPIT_TIMER_COUNT (2) 572 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 573 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 574 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 575 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 576 577 /* LPSPI module features */ 578 579 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 580 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (0) 581 /* @brief Has separate DMA RX and TX requests. */ 582 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 583 584 /* LPTMR module features */ 585 586 /* @brief Has shared interrupt handler with another LPTMR module. */ 587 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 588 /* @brief Whether LPTMR counter is 32 bits width. */ 589 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 590 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 591 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 592 593 /* LPUART module features */ 594 595 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 596 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 597 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 598 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 599 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 600 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 601 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 602 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 603 /* @brief Has 32-bit register MODIR */ 604 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 605 /* @brief Hardware flow control (RTS, CTS) is supported. */ 606 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 607 /* @brief Infrared (modulation) is supported. */ 608 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 609 /* @brief 2 bits long stop bit is available. */ 610 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 611 /* @brief If 10-bit mode is supported. */ 612 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 613 /* @brief If 7-bit mode is supported. */ 614 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 615 /* @brief Baud rate fine adjustment is available. */ 616 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 617 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 618 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 619 /* @brief Baud rate oversampling is available. */ 620 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 621 /* @brief Baud rate oversampling is available. */ 622 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 623 /* @brief Peripheral type. */ 624 #define FSL_FEATURE_LPUART_IS_SCI (1) 625 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 626 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 627 /* @brief Supports two match addresses to filter incoming frames. */ 628 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 629 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 630 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (0) 631 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 632 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 633 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 634 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 635 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 636 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 637 /* @brief Has improved smart card (ISO7816 protocol) support. */ 638 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 639 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 640 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 641 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 642 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 643 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 644 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 645 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 646 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 647 /* @brief Has separate DMA RX and TX requests. */ 648 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (0) 649 /* @brief Has separate RX and TX interrupts. */ 650 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 651 /* @brief Has LPAURT_PARAM. */ 652 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 653 /* @brief Has LPUART_VERID. */ 654 #define FSL_FEATURE_LPUART_HAS_VERID (1) 655 /* @brief Has LPUART_GLOBAL. */ 656 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 657 /* @brief Has LPUART_PINCFG. */ 658 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 659 660 /* MMDVSQ module features */ 661 662 /* No feature definitions */ 663 664 /* interrupt module features */ 665 666 /* @brief Lowest interrupt request number. */ 667 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 668 /* @brief Highest interrupt request number. */ 669 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 670 671 /* PDB module features */ 672 673 /* @brief Has DAC support. */ 674 #define FSL_FEATURE_PDB_HAS_DAC (0) 675 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 676 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 677 /* @brief PDB channel number). */ 678 #define FSL_FEATURE_PDB_CHANNEL_COUNT (1) 679 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 680 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (4) 681 /* @brief DAC interval trigger number). */ 682 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (0) 683 /* @brief Pulse out number). */ 684 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (1) 685 686 /* PMC module features */ 687 688 /* @brief Has Bandgap Enable In VLPx Operation support. */ 689 #define FSL_FEATURE_PMC_HAS_BGEN (0) 690 /* @brief Has Bandgap Buffer Enable. */ 691 #define FSL_FEATURE_PMC_HAS_BGBE (0) 692 /* @brief Has Bandgap Buffer Drive Select. */ 693 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 694 /* @brief Has Low-Voltage Detect Voltage Select support. */ 695 #define FSL_FEATURE_PMC_HAS_LVDV (0) 696 /* @brief Has Low-Voltage Warning Voltage Select support. */ 697 #define FSL_FEATURE_PMC_HAS_LVWV (0) 698 /* @brief Has LPO. */ 699 #define FSL_FEATURE_PMC_HAS_LPO (1) 700 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 701 #define FSL_FEATURE_PMC_HAS_VLPO (0) 702 /* @brief Has acknowledge isolation support. */ 703 #define FSL_FEATURE_PMC_HAS_ACKISO (0) 704 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 705 #define FSL_FEATURE_PMC_HAS_REGFPM (1) 706 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 707 #define FSL_FEATURE_PMC_HAS_REGONS (0) 708 /* @brief Has PMC_HVDSC1. */ 709 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 710 /* @brief Has PMC_PARAM. */ 711 #define FSL_FEATURE_PMC_HAS_PARAM (0) 712 /* @brief Has PMC_VERID. */ 713 #define FSL_FEATURE_PMC_HAS_VERID (0) 714 715 /* PORT module features */ 716 717 /* @brief Has control lock (register bit PCR[LK]). */ 718 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 719 /* @brief Has open drain control (register bit PCR[ODE]). */ 720 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 721 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 722 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 723 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 724 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 725 /* @brief Has pull resistor selection available. */ 726 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 727 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 728 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 729 /* @brief Has slew rate control (register bit PCR[SRE]). */ 730 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) 731 /* @brief Has passive filter (register bit field PCR[PFE]). */ 732 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 733 /* @brief Has drive strength control (register bit PCR[DSE]). */ 734 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 735 /* @brief Has separate drive strength register (HDRVE). */ 736 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 737 /* @brief Has glitch filter (register IOFLT). */ 738 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 739 /* @brief Defines width of PCR[MUX] field. */ 740 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 741 /* @brief Has dedicated interrupt vector. */ 742 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 743 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 744 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 745 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 746 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 747 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 748 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 749 750 /* RCM module features */ 751 752 /* @brief Has Loss-of-Lock Reset support. */ 753 #define FSL_FEATURE_RCM_HAS_LOL (1) 754 /* @brief Has Loss-of-Clock Reset support. */ 755 #define FSL_FEATURE_RCM_HAS_LOC (1) 756 /* @brief Has JTAG generated Reset support. */ 757 #define FSL_FEATURE_RCM_HAS_JTAG (0) 758 /* @brief Has EzPort generated Reset support. */ 759 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 760 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 761 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 762 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 763 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 764 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 765 #define FSL_FEATURE_RCM_HAS_SSRS (1) 766 /* @brief Has RCM_VERID. */ 767 #define FSL_FEATURE_RCM_HAS_VERID (1) 768 /* @brief Has RCM_PARAM. */ 769 #define FSL_FEATURE_RCM_HAS_PARAM (0) 770 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 771 #define FSL_FEATURE_RCM_HAS_SRIE (1) 772 /* @brief RCM register bit width. */ 773 #define FSL_FEATURE_RCM_REG_WIDTH (32) 774 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 775 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 776 /* @brief Has MDM-AP system reset support RCM_SRS[MDM_AP] */ 777 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 778 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 779 #define FSL_FEATURE_RCM_HAS_WAKEUP (0) 780 781 /* RTC module features */ 782 783 /* @brief Has wakeup pin. */ 784 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) 785 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 786 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 787 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 788 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 789 /* @brief Has read/write access control (registers WAR and RAR). */ 790 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 791 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 792 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 793 /* @brief Has RTC_CLKIN available. */ 794 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 795 /* @brief Has prescaler adjust for LPO. */ 796 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) 797 /* @brief Has Clock Pin Enable field. */ 798 #define FSL_FEATURE_RTC_HAS_CPE (1) 799 /* @brief Has Timer Seconds Interrupt Configuration field. */ 800 #define FSL_FEATURE_RTC_HAS_TSIC (1) 801 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 802 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) 803 /* @brief Has Tamper Interrupt Register (register TIR). */ 804 #define FSL_FEATURE_RTC_HAS_TIR (0) 805 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 806 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 807 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 808 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 809 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 810 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 811 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 812 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 813 /* @brief Has Tamper Detect Register (register TDR). */ 814 #define FSL_FEATURE_RTC_HAS_TDR (0) 815 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 816 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 817 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 818 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 819 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 820 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 821 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 822 #define FSL_FEATURE_RTC_HAS_TTSR (0) 823 /* @brief Has Pin Configuration Register (register PCR). */ 824 #define FSL_FEATURE_RTC_HAS_PCR (0) 825 826 /* SCG module features */ 827 828 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ 829 #define FSL_FEATURE_SCG_HAS_DIVPLAT (0) 830 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ 831 #define FSL_FEATURE_SCG_HAS_DIVBUS (0) 832 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ 833 #define FSL_FEATURE_SCG_HAS_DIVEXT (0) 834 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ 835 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) 836 /* @brief Has OSC freq range SOSCCFG[RANGE]. */ 837 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (1) 838 /* @brief Has SOSCCSR[SOSCERCLKEN]. */ 839 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (1) 840 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ 841 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) 842 /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ 843 #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (0) 844 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ 845 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (0) 846 /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ 847 #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (0) 848 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ 849 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (0) 850 /* @brief Has SCG_SIRCCSR[LPOPO]. */ 851 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) 852 /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ 853 #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (0) 854 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ 855 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (0) 856 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ 857 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) 858 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ 859 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) 860 /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ 861 #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (0) 862 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ 863 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0) 864 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ 865 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) 866 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ 867 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) 868 /* @brief Has SCG_SPLLCFG[PLLS]. */ 869 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) 870 /* @brief Has SCG_SPLLCFG[BYPASS]. */ 871 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) 872 /* @brief Has SCG_SPLLCFG[PFDSEL]. */ 873 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) 874 /* @brief Has SCG_SPLLCSR[SPLLCM]. */ 875 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) 876 /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ 877 #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) 878 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ 879 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) 880 /* @brief Has low power FLL, SCG_LPFLLCSR. */ 881 #define FSL_FEATURE_SCG_HAS_LPFLL (1) 882 /* @brief Has low power FLL stop enable. */ 883 #define FSL_FEATURE_SCG_HAS_LPFLLSTEN (0) 884 /* @brief Has system PLL, SCG_SPLLCSR. */ 885 #define FSL_FEATURE_SCG_HAS_SPLL (0) 886 /* @brief Has system PLL PFD, SCG_SPLLPFD. */ 887 #define FSL_FEATURE_SCG_HAS_SPLLPFD (0) 888 /* @brief Has auxiliary PLL, SCG_APLLCSR. */ 889 #define FSL_FEATURE_SCG_HAS_APLL (0) 890 /* @brief Has RTC OSC control, SCG_ROSCCSR. */ 891 #define FSL_FEATURE_SCG_HAS_ROSC (0) 892 /* @brief Has RTC OSC clock source. */ 893 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (0) 894 /* @brief Has RTC OSC clock out select. */ 895 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (0) 896 /* @brief Has SIRC clock out select. */ 897 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) 898 /* @brief Has FIRC trim source USB0 Start of Frame. */ 899 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0) 900 /* @brief Has FIRC trim source USB1 Start of Frame. */ 901 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) 902 /* @brief Has FIRC trim source system OSC. */ 903 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) 904 /* @brief Has FIRC trim source RTC OSC. */ 905 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (0) 906 907 /* SMC module features */ 908 909 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 910 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 911 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 912 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 913 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 914 #define FSL_FEATURE_SMC_HAS_PORPO (0) 915 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 916 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 917 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 918 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 919 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 920 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 921 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 922 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 923 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 924 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 925 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 926 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 927 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 928 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 929 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 930 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (0) 931 /* @brief Has stop submode. */ 932 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0) 933 /* @brief Has stop submode 0(state VLLS0 of register bit STOPCTRL[VLLSM]). */ 934 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) 935 /* @brief Has stop submode 2(state VLLS2 of register bit STOPCTRL[VLLSM]). */ 936 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 937 /* @brief Has SMC_PARAM. */ 938 #define FSL_FEATURE_SMC_HAS_PARAM (1) 939 /* @brief Has SMC_VERID. */ 940 #define FSL_FEATURE_SMC_HAS_VERID (1) 941 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 942 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 943 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 944 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 945 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 946 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 947 /* @brief Width of SMC registers. */ 948 #define FSL_FEATURE_SMC_REG_WIDTH (32) 949 950 /* SysTick module features */ 951 952 /* @brief Systick has external reference clock. */ 953 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 954 /* @brief Systick external reference clock is core clock divided by this value. */ 955 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 956 957 /* TSI module features */ 958 959 /* @brief TSI module version. */ 960 #define FSL_FEATURE_TSI_VERSION (5) 961 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 962 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1) 963 /* @brief Has channel used for mutual cap TX configuration (register bit MUL0[M_TX_USED]). */ 964 #define FSL_FEATURE_TSI_HAS_M_TX_USED (1) 965 /* @brief Number of TSI channels. */ 966 #define FSL_FEATURE_TSI_CHANNEL_COUNT (25) 967 968 /* WDOG module features */ 969 970 /* @brief Watchdog is available. */ 971 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 972 /* @brief WDOG_CNT can be 32-bit written. */ 973 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 974 975 #endif /* _MKE16Z4_FEATURES_H_ */ 976 977
