1 /*
2 ** ###################################################################
3 **     Processors:          MKE15Z128VLH7
4 **                          MKE15Z128VLL7
5 **                          MKE15Z256VLH7
6 **                          MKE15Z256VLL7
7 **
8 **     Compilers:           Freescale C/C++ for Embedded ARM
9 **                          GNU C Compiler
10 **                          IAR ANSI C/C++ Compiler for ARM
11 **                          Keil ARM C/C++ Compiler
12 **                          MCUXpresso Compiler
13 **
14 **     Reference manual:    KE1xZP100M72SF0RM, Rev. 2, Aug. 2016
15 **     Version:             rev. 6.0, 2016-09-20
16 **     Build:               b201123
17 **
18 **     Abstract:
19 **         Provides a system configuration function and a global variable that
20 **         contains the system frequency. It configures the device and initializes
21 **         the oscillator (PLL) that is part of the microcontroller device.
22 **
23 **     Copyright 2016 Freescale Semiconductor, Inc.
24 **     Copyright 2016-2020 NXP
25 **     All rights reserved.
26 **
27 **     SPDX-License-Identifier: BSD-3-Clause
28 **
29 **     http:                 www.nxp.com
30 **     mail:                 support@nxp.com
31 **
32 **     Revisions:
33 **     - rev. 1.0 (2015-08-19)
34 **         Initial version.
35 **     - rev. 2.0 (2015-09-22)
36 **         Based on rev0final RDP, add PCC/TRGMUX.
37 **     - rev. 3.0 (2015-12-29)
38 **         Align LPFLL register names.
39 **     - rev. 4.0 (2016-02-19)
40 **         Based on rev1final RDP.
41 **     - rev. 5.0 (2016-08-02)
42 **         Based on rev1.x RDP.
43 **     - rev. 6.0 (2016-09-20)
44 **         Based on rev2 RDP.
45 **
46 ** ###################################################################
47 */
48 
49 /*!
50  * @file MKE15Z7
51  * @version 6.0
52  * @date 2016-09-20
53  * @brief Device specific configuration file for MKE15Z7 (implementation file)
54  *
55  * Provides a system configuration function and a global variable that contains
56  * the system frequency. It configures the device and initializes the oscillator
57  * (PLL) that is part of the microcontroller device.
58  */
59 
60 #include <stdint.h>
61 #include "fsl_device_registers.h"
62 
63 
64 
65 /* ----------------------------------------------------------------------------
66    -- Core clock
67    ---------------------------------------------------------------------------- */
68 
69 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
70 
71 /* ----------------------------------------------------------------------------
72    -- SystemInit()
73    ---------------------------------------------------------------------------- */
74 
SystemInit(void)75 void SystemInit (void) {
76 
77   /* Redirect vector table to Flash, in case of boot from ROM without overwriting FOPT boot option */
78   RCM->MR = 3UL << 1U;
79 
80 #if (DISABLE_WDOG)
81   if ((WDOG->CS & WDOG_CS_CMD32EN_MASK) != 0U)
82   {
83       WDOG->CNT = WDOG_UPDATE_KEY;
84   }
85   else
86   {
87       WDOG->CNT = WDOG_UPDATE_KEY & 0xFFFFU;
88       WDOG->CNT = (WDOG_UPDATE_KEY >> 16U) & 0xFFFFU;
89   }
90   WDOG->TOVAL = 0xFFFFU;
91   WDOG->CS = (uint32_t) ((WDOG->CS) & ~WDOG_CS_EN_MASK) | WDOG_CS_UPDATE_MASK;
92 #endif /* (DISABLE_WDOG) */
93 
94   SystemInitHook();
95 }
96 
97 /* ----------------------------------------------------------------------------
98    -- SystemCoreClockUpdate()
99    ---------------------------------------------------------------------------- */
100 
SystemCoreClockUpdate(void)101 void SystemCoreClockUpdate (void) {
102 
103   uint32_t SCGOUTClock;                                 /* Variable to store output clock frequency of the SCG module */
104   uint16_t Divider;
105   Divider = (uint16_t)(((SCG->CSR & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1U);
106 
107   switch ((SCG->CSR & SCG_CSR_SCS_MASK) >> SCG_CSR_SCS_SHIFT) {
108     case 0x1:
109       /* System OSC */
110       SCGOUTClock = CPU_XTAL_CLK_HZ;
111       break;
112     case 0x2:
113       /* Slow IRC */
114       SCGOUTClock = ((((SCG->SIRCCFG & SCG_SIRCCFG_RANGE_MASK) >> SCG_SIRCCFG_RANGE_SHIFT) != 0U) ? 8000000U : 2000000U);
115       break;
116     case 0x3:
117       /* Fast IRC */
118       SCGOUTClock = 48000000U + ((SCG->FIRCCFG & SCG_FIRCCFG_RANGE_MASK) >> SCG_FIRCCFG_RANGE_SHIFT) * 4000000U;
119       break;
120     case 0x5:
121       /* Low Power FLL */
122       SCGOUTClock = 48000000U + ((SCG->LPFLLCFG & SCG_LPFLLCFG_FSEL_MASK) >> SCG_LPFLLCFG_FSEL_SHIFT) * 24000000U;
123       break;
124     default:
125       SCGOUTClock = 0U;
126       break;
127   }
128   SystemCoreClock = (SCGOUTClock / Divider);
129 
130 }
131 
132 /* ----------------------------------------------------------------------------
133    -- SystemInitHook()
134    ---------------------------------------------------------------------------- */
135 
SystemInitHook(void)136 __attribute__ ((weak)) void SystemInitHook (void) {
137   /* Void implementation of the weak function. */
138 }
139