1 /* 2 ** ################################################################### 3 ** Version: rev. 6.0, 2016-09-20 4 ** Build: b220803 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2022 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2015-08-19) 20 ** Initial version. 21 ** - rev. 2.0 (2015-09-22) 22 ** Based on rev0final RDP, add PCC/TRGMUX. 23 ** - rev. 3.0 (2015-12-29) 24 ** Align LPFLL register names. 25 ** - rev. 4.0 (2016-02-19) 26 ** Based on rev1final RDP. 27 ** - rev. 5.0 (2016-08-02) 28 ** Based on rev1.x RDP. 29 ** - rev. 6.0 (2016-09-20) 30 ** Based on rev2 RDP. 31 ** 32 ** ################################################################### 33 */ 34 35 #ifndef _MKE14Z7_FEATURES_H_ 36 #define _MKE14Z7_FEATURES_H_ 37 38 /* SOC module features */ 39 40 /* @brief ACMP availability on the SoC. */ 41 #define FSL_FEATURE_SOC_ACMP_COUNT (2) 42 /* @brief ADC12 availability on the SoC. */ 43 #define FSL_FEATURE_SOC_ADC12_COUNT (2) 44 /* @brief CRC availability on the SoC. */ 45 #define FSL_FEATURE_SOC_CRC_COUNT (1) 46 /* @brief EDMA availability on the SoC. */ 47 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 48 /* @brief DMAMUX availability on the SoC. */ 49 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 50 /* @brief EWM availability on the SoC. */ 51 #define FSL_FEATURE_SOC_EWM_COUNT (1) 52 /* @brief FGPIO availability on the SoC. */ 53 #define FSL_FEATURE_SOC_FGPIO_COUNT (5) 54 /* @brief FLEXIO availability on the SoC. */ 55 #define FSL_FEATURE_SOC_FLEXIO_COUNT (1) 56 /* @brief FTFE availability on the SoC. */ 57 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 58 /* @brief FTM availability on the SoC. */ 59 #define FSL_FEATURE_SOC_FTM_COUNT (3) 60 /* @brief GPIO availability on the SoC. */ 61 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 62 /* @brief LPI2C availability on the SoC. */ 63 #define FSL_FEATURE_SOC_LPI2C_COUNT (2) 64 /* @brief LPIT availability on the SoC. */ 65 #define FSL_FEATURE_SOC_LPIT_COUNT (1) 66 /* @brief LPSPI availability on the SoC. */ 67 #define FSL_FEATURE_SOC_LPSPI_COUNT (2) 68 /* @brief LPTMR availability on the SoC. */ 69 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 70 /* @brief LPUART availability on the SoC. */ 71 #define FSL_FEATURE_SOC_LPUART_COUNT (3) 72 /* @brief MCM availability on the SoC. */ 73 #define FSL_FEATURE_SOC_MCM_COUNT (1) 74 /* @brief MMDVSQ availability on the SoC. */ 75 #define FSL_FEATURE_SOC_MMDVSQ_COUNT (1) 76 /* @brief MTB availability on the SoC. */ 77 #define FSL_FEATURE_SOC_MTB_COUNT (1) 78 /* @brief MTBDWT availability on the SoC. */ 79 #define FSL_FEATURE_SOC_MTBDWT_COUNT (1) 80 /* @brief OSC32 availability on the SoC. */ 81 #define FSL_FEATURE_SOC_OSC32_COUNT (1) 82 /* @brief PDB availability on the SoC. */ 83 #define FSL_FEATURE_SOC_PDB_COUNT (1) 84 /* @brief PCC availability on the SoC. */ 85 #define FSL_FEATURE_SOC_PCC_COUNT (1) 86 /* @brief PMC availability on the SoC. */ 87 #define FSL_FEATURE_SOC_PMC_COUNT (1) 88 /* @brief PORT availability on the SoC. */ 89 #define FSL_FEATURE_SOC_PORT_COUNT (5) 90 /* @brief PWT availability on the SoC. */ 91 #define FSL_FEATURE_SOC_PWT_COUNT (1) 92 /* @brief RCM availability on the SoC. */ 93 #define FSL_FEATURE_SOC_RCM_COUNT (1) 94 /* @brief ROM availability on the SoC. */ 95 #define FSL_FEATURE_SOC_ROM_COUNT (1) 96 /* @brief RTC availability on the SoC. */ 97 #define FSL_FEATURE_SOC_RTC_COUNT (1) 98 /* @brief SCG availability on the SoC. */ 99 #define FSL_FEATURE_SOC_SCG_COUNT (1) 100 /* @brief SIM availability on the SoC. */ 101 #define FSL_FEATURE_SOC_SIM_COUNT (1) 102 /* @brief SMC availability on the SoC. */ 103 #define FSL_FEATURE_SOC_SMC_COUNT (1) 104 /* @brief TRGMUX availability on the SoC. */ 105 #define FSL_FEATURE_SOC_TRGMUX_COUNT (2) 106 /* @brief WDOG availability on the SoC. */ 107 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 108 109 /* ADC12 module features */ 110 111 /* @brief Has DMA support (bit SC2[DMAEN]. */ 112 #define FSL_FEATURE_ADC12_HAS_DMA_SUPPORT (1) 113 /* @brief Conversion control count (related to number of registers SC1n and Rn). */ 114 #define FSL_FEATURE_ADC12_CONVERSION_CONTROL_COUNT (2) 115 116 /* ACMP module features */ 117 118 /* @brief Has CMP_C3. */ 119 #define FSL_FEATURE_ACMP_HAS_C3_REG (0) 120 /* @brief Has C0 LINKEN Bit */ 121 #define FSL_FEATURE_ACMP_HAS_C0_LINKEN_BIT (0) 122 /* @brief Has C0 OFFSET Bit */ 123 #define FSL_FEATURE_ACMP_HAS_C0_OFFSET_BIT (1) 124 /* @brief Has C1 INPSEL Bit */ 125 #define FSL_FEATURE_ACMP_HAS_C1_INPSEL_BIT (1) 126 /* @brief Has C1 INNSEL Bit */ 127 #define FSL_FEATURE_ACMP_HAS_C1_INNSEL_BIT (1) 128 /* @brief Has C1 DACOE Bit */ 129 #define FSL_FEATURE_ACMP_HAS_C1_DACOE_BIT (1) 130 /* @brief Has C1 DMODE Bit */ 131 #define FSL_FEATURE_ACMP_HAS_C1_DMODE_BIT (0) 132 /* @brief Has C2 RRE Bit */ 133 #define FSL_FEATURE_ACMP_HAS_C2_RRE_BIT (1) 134 135 /* CRC module features */ 136 137 /* @brief Has data register with name CRC */ 138 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 139 140 /* EDMA module features */ 141 142 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 143 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (8) 144 /* @brief Total number of DMA channels on all modules. */ 145 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (8) 146 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 147 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 148 /* @brief Has DMA_Error interrupt vector. */ 149 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 150 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 151 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (8) 152 /* @brief Channel IRQ entry shared offset. */ 153 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (4) 154 /* @brief If 8 bytes transfer supported. */ 155 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 156 /* @brief If 16 bytes transfer supported. */ 157 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 158 159 /* DMAMUX module features */ 160 161 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 162 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (8) 163 /* @brief Total number of DMA channels on all modules. */ 164 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (8) 165 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 166 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 167 /* @brief Register CHCFGn width. */ 168 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 169 170 /* EWM module features */ 171 172 /* @brief Has clock select (register CLKCTRL). */ 173 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 174 /* @brief Has clock prescaler (register CLKPRESCALER). */ 175 #define FSL_FEATURE_EWM_HAS_PRESCALER (1) 176 177 /* FGPIO module features */ 178 179 /* No feature definitions */ 180 181 /* FLEXIO module features */ 182 183 /* @brief Has Shifter Status Register (FLEXIO_SHIFTSTAT) */ 184 #define FSL_FEATURE_FLEXIO_HAS_SHIFTER_STATUS (1) 185 /* @brief Has Pin Data Input Register (FLEXIO_PIN) */ 186 #define FSL_FEATURE_FLEXIO_HAS_PIN_STATUS (1) 187 /* @brief Has Shifter Buffer N Nibble Byte Swapped Register (FLEXIO_SHIFTBUFNBSn) */ 188 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_BYTE_SWAP (0) 189 /* @brief Has Shifter Buffer N Half Word Swapped Register (FLEXIO_SHIFTBUFHWSn) */ 190 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_HALF_WORD_SWAP (0) 191 /* @brief Has Shifter Buffer N Nibble Swapped Register (FLEXIO_SHIFTBUFNISn) */ 192 #define FSL_FEATURE_FLEXIO_HAS_SHFT_BUFFER_NIBBLE_SWAP (0) 193 /* @brief Supports Shifter State Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 194 #define FSL_FEATURE_FLEXIO_HAS_STATE_MODE (0) 195 /* @brief Supports Shifter Logic Mode (FLEXIO_SHIFTCTLn[SMOD]) */ 196 #define FSL_FEATURE_FLEXIO_HAS_LOGIC_MODE (0) 197 /* @brief Supports paralle width (FLEXIO_SHIFTCFGn[PWIDTH]) */ 198 #define FSL_FEATURE_FLEXIO_HAS_PARALLEL_WIDTH (0) 199 /* @brief Reset value of the FLEXIO_VERID register */ 200 #define FSL_FEATURE_FLEXIO_VERID_RESET_VALUE (0x1010000) 201 /* @brief Reset value of the FLEXIO_PARAM register */ 202 #define FSL_FEATURE_FLEXIO_PARAM_RESET_VALUE (0x4080404) 203 /* @brief Flexio DMA request base channel */ 204 #define FSL_FEATURE_FLEXIO_DMA_REQUEST_BASE_CHANNEL (0) 205 206 /* FLASH module features */ 207 208 #if defined(CPU_MKE14Z128VLH7) || defined(CPU_MKE14Z128VLL7) 209 /* @brief Is of type FTFA. */ 210 #define FSL_FEATURE_FLASH_IS_FTFA (0) 211 /* @brief Is of type FTFE. */ 212 #define FSL_FEATURE_FLASH_IS_FTFE (1) 213 /* @brief Is of type FTFL. */ 214 #define FSL_FEATURE_FLASH_IS_FTFL (0) 215 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 216 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 217 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 218 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 219 /* @brief Has EEPROM region protection (register FEPROT). */ 220 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 221 /* @brief Has data flash region protection (register FDPROT). */ 222 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 223 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 224 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 225 /* @brief Has flash cache control in FMC module. */ 226 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 227 /* @brief Has flash cache control in MCM module. */ 228 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 229 /* @brief Has flash cache control in MSCM module. */ 230 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 231 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 232 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 233 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 234 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 235 /* @brief P-Flash start address. */ 236 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 237 /* @brief P-Flash block count. */ 238 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 239 /* @brief P-Flash block size. */ 240 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (131072) 241 /* @brief P-Flash sector size. */ 242 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 243 /* @brief P-Flash write unit size. */ 244 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 245 /* @brief P-Flash data path width. */ 246 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 247 /* @brief P-Flash block swap feature. */ 248 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 249 /* @brief P-Flash protection region count. */ 250 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 251 /* @brief Has FlexNVM memory. */ 252 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 253 /* @brief Has FlexNVM alias. */ 254 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 255 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 256 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 257 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 258 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 259 /* @brief FlexNVM block count. */ 260 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 261 /* @brief FlexNVM block size. */ 262 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) 263 /* @brief FlexNVM sector size. */ 264 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (2048) 265 /* @brief FlexNVM write unit size. */ 266 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 267 /* @brief FlexNVM data path width. */ 268 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (8) 269 /* @brief Has FlexRAM memory. */ 270 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 271 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 272 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 273 /* @brief FlexRAM size. */ 274 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 275 /* @brief Has 0x00 Read 1s Block command. */ 276 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 277 /* @brief Has 0x01 Read 1s Section command. */ 278 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 279 /* @brief Has 0x02 Program Check command. */ 280 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 281 /* @brief Has 0x03 Read Resource command. */ 282 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 283 /* @brief Has 0x06 Program Longword command. */ 284 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 285 /* @brief Has 0x07 Program Phrase command. */ 286 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 287 /* @brief Has 0x08 Erase Flash Block command. */ 288 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 289 /* @brief Has 0x09 Erase Flash Sector command. */ 290 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 291 /* @brief Has 0x0B Program Section command. */ 292 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 293 /* @brief Has 0x40 Read 1s All Blocks command. */ 294 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 295 /* @brief Has 0x41 Read Once command. */ 296 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 297 /* @brief Has 0x43 Program Once command. */ 298 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 299 /* @brief Has 0x44 Erase All Blocks command. */ 300 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 301 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 302 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 303 /* @brief Has 0x46 Swap Control command. */ 304 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 305 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 306 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 307 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 308 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 309 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 310 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 311 /* @brief Has 0x80 Program Partition command. */ 312 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 313 /* @brief Has 0x81 Set FlexRAM Function command. */ 314 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 315 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 316 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (8) 317 /* @brief P-Flash Erase sector command address alignment. */ 318 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 319 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 320 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 321 /* @brief P-Flash Read resource command address alignment. */ 322 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 323 /* @brief P-Flash Program check command address alignment. */ 324 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 325 /* @brief P-Flash Program check command address alignment. */ 326 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 327 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 328 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (8) 329 /* @brief FlexNVM Erase sector command address alignment. */ 330 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (8) 331 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 332 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (8) 333 /* @brief FlexNVM Read resource command address alignment. */ 334 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 335 /* @brief FlexNVM Program check command address alignment. */ 336 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 337 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 338 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000U) 339 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 340 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000U) 341 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 342 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000U) 343 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 344 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000U) 345 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 346 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 347 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 348 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 349 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 350 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 351 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 352 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 353 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 354 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000U) 355 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 356 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000U) 357 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 358 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000U) 359 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 360 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000U) 361 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 362 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 363 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 364 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 365 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 366 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 367 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 368 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000U) 369 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 370 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 371 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 372 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 373 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 374 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 375 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 376 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 377 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 378 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 379 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 380 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 381 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 382 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 383 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 384 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 385 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 386 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 387 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 388 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 389 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 390 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 391 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 392 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 393 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 394 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 395 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 396 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 397 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 398 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 399 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 400 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 401 #elif defined(CPU_MKE14Z256VLH7) || defined(CPU_MKE14Z256VLL7) 402 /* @brief Is of type FTFA. */ 403 #define FSL_FEATURE_FLASH_IS_FTFA (0) 404 /* @brief Is of type FTFE. */ 405 #define FSL_FEATURE_FLASH_IS_FTFE (1) 406 /* @brief Is of type FTFL. */ 407 #define FSL_FEATURE_FLASH_IS_FTFL (0) 408 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 409 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 410 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 411 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (0) 412 /* @brief Has EEPROM region protection (register FEPROT). */ 413 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 414 /* @brief Has data flash region protection (register FDPROT). */ 415 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 416 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 417 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 418 /* @brief Has flash cache control in FMC module. */ 419 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (0) 420 /* @brief Has flash cache control in MCM module. */ 421 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (1) 422 /* @brief Has flash cache control in MSCM module. */ 423 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 424 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 425 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 426 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 427 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 428 /* @brief P-Flash start address. */ 429 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 430 /* @brief P-Flash block count. */ 431 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 432 /* @brief P-Flash block size. */ 433 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (262144) 434 /* @brief P-Flash sector size. */ 435 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (2048) 436 /* @brief P-Flash write unit size. */ 437 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 438 /* @brief P-Flash data path width. */ 439 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (8) 440 /* @brief P-Flash block swap feature. */ 441 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 442 /* @brief P-Flash protection region count. */ 443 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 444 /* @brief Has FlexNVM memory. */ 445 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 446 /* @brief Has FlexNVM alias. */ 447 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 448 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 449 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 450 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 451 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 452 /* @brief FlexNVM block count. */ 453 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 454 /* @brief FlexNVM block size. */ 455 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (32768) 456 /* @brief FlexNVM sector size. */ 457 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (2048) 458 /* @brief FlexNVM write unit size. */ 459 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 460 /* @brief FlexNVM data path width. */ 461 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (8) 462 /* @brief Has FlexRAM memory. */ 463 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 464 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 465 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 466 /* @brief FlexRAM size. */ 467 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (2048) 468 /* @brief Has 0x00 Read 1s Block command. */ 469 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 470 /* @brief Has 0x01 Read 1s Section command. */ 471 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 472 /* @brief Has 0x02 Program Check command. */ 473 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 474 /* @brief Has 0x03 Read Resource command. */ 475 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 476 /* @brief Has 0x06 Program Longword command. */ 477 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 478 /* @brief Has 0x07 Program Phrase command. */ 479 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 480 /* @brief Has 0x08 Erase Flash Block command. */ 481 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 482 /* @brief Has 0x09 Erase Flash Sector command. */ 483 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 484 /* @brief Has 0x0B Program Section command. */ 485 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 486 /* @brief Has 0x40 Read 1s All Blocks command. */ 487 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 488 /* @brief Has 0x41 Read Once command. */ 489 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 490 /* @brief Has 0x43 Program Once command. */ 491 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 492 /* @brief Has 0x44 Erase All Blocks command. */ 493 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 494 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 495 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 496 /* @brief Has 0x46 Swap Control command. */ 497 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 498 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 499 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (1) 500 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 501 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 502 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 503 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (1) 504 /* @brief Has 0x80 Program Partition command. */ 505 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 506 /* @brief Has 0x81 Set FlexRAM Function command. */ 507 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 508 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 509 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (8) 510 /* @brief P-Flash Erase sector command address alignment. */ 511 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (8) 512 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 513 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (8) 514 /* @brief P-Flash Read resource command address alignment. */ 515 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 516 /* @brief P-Flash Program check command address alignment. */ 517 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 518 /* @brief P-Flash Program check command address alignment. */ 519 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 520 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 521 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (8) 522 /* @brief FlexNVM Erase sector command address alignment. */ 523 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (8) 524 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 525 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (8) 526 /* @brief FlexNVM Read resource command address alignment. */ 527 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 528 /* @brief FlexNVM Program check command address alignment. */ 529 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 530 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 531 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00008000U) 532 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 533 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0x00006000U) 534 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 535 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x00004000U) 536 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 537 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00000000U) 538 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 539 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 540 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 541 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 542 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 543 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 544 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 545 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 546 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 547 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000U) 548 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 549 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0x00002000U) 550 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 551 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000U) 552 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 553 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000U) 554 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 555 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 556 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 557 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 558 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 559 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 560 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 561 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00008000U) 562 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 563 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 564 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 565 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 566 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 567 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0xFFFF) 568 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 569 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 570 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 571 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 572 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 573 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 574 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 575 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 576 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 577 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 578 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 579 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 580 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 581 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 582 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 583 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 584 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 585 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 586 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 587 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 588 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 589 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 590 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 591 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 592 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 593 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 594 #endif /* defined(CPU_MKE14Z128VLH7) || defined(CPU_MKE14Z128VLL7) */ 595 596 /* FTM module features */ 597 598 /* @brief Number of channels. */ 599 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 600 (((x) == FTM0) ? (8) : \ 601 (((x) == FTM1) ? (4) : \ 602 (((x) == FTM2) ? (4) : (-1)))) 603 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 604 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (1) 605 /* @brief Has extended deadtime value. */ 606 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 607 /* @brief Enable pwm output for the module. */ 608 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (1) 609 /* @brief Has half-cycle reload for the module. */ 610 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (1) 611 /* @brief Has reload interrupt. */ 612 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (1) 613 /* @brief Has reload initialization trigger. */ 614 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (1) 615 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 616 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 617 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 618 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (1) 619 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 620 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (1) 621 /* @brief If instance has only TPM function. */ 622 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 623 /* @brief Has frequency of the reload opportunities, bitfield CONF[LDFQ]. */ 624 #define FSL_FEATURE_FTM_HAS_CONF_LDFQ_BIT (1) 625 626 /* GPIO module features */ 627 628 /* @brief Has GPIO attribute checker register (GACR). */ 629 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 630 631 /* LPI2C module features */ 632 633 /* @brief Has separate DMA RX and TX requests. */ 634 #define FSL_FEATURE_LPI2C_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 635 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 636 #define FSL_FEATURE_LPI2C_FIFO_SIZEn(x) (4) 637 638 /* LPIT module features */ 639 640 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 641 #define FSL_FEATURE_LPIT_TIMER_COUNT (4) 642 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 643 #define FSL_FEATURE_LPIT_HAS_LIFETIME_TIMER (0) 644 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 645 #define FSL_FEATURE_LPIT_HAS_SHARED_IRQ_HANDLER (1) 646 647 /* LPSPI module features */ 648 649 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 650 #define FSL_FEATURE_LPSPI_FIFO_SIZEn(x) (0) 651 /* @brief Has separate DMA RX and TX requests. */ 652 #define FSL_FEATURE_LPSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 653 654 /* LPTMR module features */ 655 656 /* @brief Has shared interrupt handler with another LPTMR module. */ 657 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 658 /* @brief Whether LPTMR counter is 32 bits width. */ 659 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 660 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 661 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (1) 662 663 /* LPUART module features */ 664 665 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 666 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 667 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 668 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 669 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 670 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 671 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 672 #define FSL_FEATURE_LPUART_HAS_FIFO (1) 673 /* @brief Has 32-bit register MODIR */ 674 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 675 /* @brief Hardware flow control (RTS, CTS) is supported. */ 676 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 677 /* @brief Infrared (modulation) is supported. */ 678 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 679 /* @brief 2 bits long stop bit is available. */ 680 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 681 /* @brief If 10-bit mode is supported. */ 682 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 683 /* @brief If 7-bit mode is supported. */ 684 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (1) 685 /* @brief Baud rate fine adjustment is available. */ 686 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 687 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 688 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 689 /* @brief Baud rate oversampling is available. */ 690 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 691 /* @brief Baud rate oversampling is available. */ 692 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 693 /* @brief Peripheral type. */ 694 #define FSL_FEATURE_LPUART_IS_SCI (1) 695 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 696 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (4) 697 /* @brief Supports two match addresses to filter incoming frames. */ 698 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 699 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 700 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 701 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 702 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 703 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 704 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 705 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 706 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 707 /* @brief Has improved smart card (ISO7816 protocol) support. */ 708 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 709 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 710 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 711 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 712 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 713 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 714 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 715 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 716 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 717 /* @brief Has separate DMA RX and TX requests. */ 718 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 719 /* @brief Has separate RX and TX interrupts. */ 720 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 721 /* @brief Has LPAURT_PARAM. */ 722 #define FSL_FEATURE_LPUART_HAS_PARAM (1) 723 /* @brief Has LPUART_VERID. */ 724 #define FSL_FEATURE_LPUART_HAS_VERID (1) 725 /* @brief Has LPUART_GLOBAL. */ 726 #define FSL_FEATURE_LPUART_HAS_GLOBAL (1) 727 /* @brief Has LPUART_PINCFG. */ 728 #define FSL_FEATURE_LPUART_HAS_PINCFG (1) 729 730 /* MMDVSQ module features */ 731 732 /* No feature definitions */ 733 734 /* interrupt module features */ 735 736 /* @brief Lowest interrupt request number. */ 737 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 738 /* @brief Highest interrupt request number. */ 739 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (31) 740 741 /* OSC32 module features */ 742 743 /* No feature definitions */ 744 745 /* PDB module features */ 746 747 /* @brief Has DAC support. */ 748 #define FSL_FEATURE_PDB_HAS_DAC (0) 749 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 750 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 751 /* @brief PDB channel number). */ 752 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 753 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 754 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 755 /* @brief DAC interval trigger number). */ 756 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (0) 757 /* @brief Pulse out number). */ 758 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (2) 759 760 /* PMC module features */ 761 762 /* @brief Has Bandgap Enable In VLPx Operation support. */ 763 #define FSL_FEATURE_PMC_HAS_BGEN (0) 764 /* @brief Has Bandgap Buffer Enable. */ 765 #define FSL_FEATURE_PMC_HAS_BGBE (0) 766 /* @brief Has Bandgap Buffer Drive Select. */ 767 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 768 /* @brief Has Low-Voltage Detect Voltage Select support. */ 769 #define FSL_FEATURE_PMC_HAS_LVDV (0) 770 /* @brief Has Low-Voltage Warning Voltage Select support. */ 771 #define FSL_FEATURE_PMC_HAS_LVWV (0) 772 /* @brief Has LPO. */ 773 #define FSL_FEATURE_PMC_HAS_LPO (1) 774 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 775 #define FSL_FEATURE_PMC_HAS_VLPO (0) 776 /* @brief Has acknowledge isolation support. */ 777 #define FSL_FEATURE_PMC_HAS_ACKISO (0) 778 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 779 #define FSL_FEATURE_PMC_HAS_REGFPM (1) 780 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 781 #define FSL_FEATURE_PMC_HAS_REGONS (0) 782 /* @brief Has PMC_HVDSC1. */ 783 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 784 /* @brief Has PMC_PARAM. */ 785 #define FSL_FEATURE_PMC_HAS_PARAM (0) 786 /* @brief Has PMC_VERID. */ 787 #define FSL_FEATURE_PMC_HAS_VERID (0) 788 789 /* PORT module features */ 790 791 /* @brief Has control lock (register bit PCR[LK]). */ 792 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 793 /* @brief Has open drain control (register bit PCR[ODE]). */ 794 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (0) 795 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 796 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 797 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 798 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 799 /* @brief Has pull resistor selection available. */ 800 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 801 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 802 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 803 /* @brief Has slew rate control (register bit PCR[SRE]). */ 804 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (0) 805 /* @brief Has passive filter (register bit field PCR[PFE]). */ 806 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 807 /* @brief Has drive strength control (register bit PCR[DSE]). */ 808 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 809 /* @brief Has separate drive strength register (HDRVE). */ 810 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 811 /* @brief Has glitch filter (register IOFLT). */ 812 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 813 /* @brief Defines width of PCR[MUX] field. */ 814 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 815 /* @brief Has dedicated interrupt vector. */ 816 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 817 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 818 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 819 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 820 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 821 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 822 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 823 824 /* RCM module features */ 825 826 /* @brief Has Loss-of-Lock Reset support. */ 827 #define FSL_FEATURE_RCM_HAS_LOL (1) 828 /* @brief Has Loss-of-Clock Reset support. */ 829 #define FSL_FEATURE_RCM_HAS_LOC (1) 830 /* @brief Has JTAG generated Reset support. */ 831 #define FSL_FEATURE_RCM_HAS_JTAG (0) 832 /* @brief Has EzPort generated Reset support. */ 833 #define FSL_FEATURE_RCM_HAS_EZPORT (0) 834 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 835 #define FSL_FEATURE_RCM_HAS_EZPMS (0) 836 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 837 #define FSL_FEATURE_RCM_HAS_BOOTROM (1) 838 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 839 #define FSL_FEATURE_RCM_HAS_SSRS (1) 840 /* @brief Has RCM_VERID. */ 841 #define FSL_FEATURE_RCM_HAS_VERID (1) 842 /* @brief Has RCM_PARAM. */ 843 #define FSL_FEATURE_RCM_HAS_PARAM (1) 844 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 845 #define FSL_FEATURE_RCM_HAS_SRIE (1) 846 /* @brief RCM register bit width. */ 847 #define FSL_FEATURE_RCM_REG_WIDTH (32) 848 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 849 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 850 /* @brief Has MDM-AP system reset support RCM_SRS[MDM_AP] */ 851 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 852 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 853 #define FSL_FEATURE_RCM_HAS_WAKEUP (0) 854 855 /* RTC module features */ 856 857 /* @brief Has wakeup pin. */ 858 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (0) 859 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 860 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 861 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 862 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 863 /* @brief Has read/write access control (registers WAR and RAR). */ 864 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 865 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 866 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 867 /* @brief Has RTC_CLKIN available. */ 868 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (1) 869 /* @brief Has prescaler adjust for LPO. */ 870 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (1) 871 /* @brief Has Clock Pin Enable field. */ 872 #define FSL_FEATURE_RTC_HAS_CPE (1) 873 /* @brief Has Timer Seconds Interrupt Configuration field. */ 874 #define FSL_FEATURE_RTC_HAS_TSIC (1) 875 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 876 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (0) 877 /* @brief Has Tamper Interrupt Register (register TIR). */ 878 #define FSL_FEATURE_RTC_HAS_TIR (0) 879 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 880 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 881 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 882 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 883 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 884 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 885 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 886 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 887 /* @brief Has Tamper Detect Register (register TDR). */ 888 #define FSL_FEATURE_RTC_HAS_TDR (0) 889 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 890 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 891 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 892 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 893 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 894 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 895 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 896 #define FSL_FEATURE_RTC_HAS_TTSR (0) 897 /* @brief Has Pin Configuration Register (register PCR). */ 898 #define FSL_FEATURE_RTC_HAS_PCR (0) 899 900 /* SCG module features */ 901 902 /* @brief Has platform clock divider SCG_CSR[DIVPLAT]. */ 903 #define FSL_FEATURE_SCG_HAS_DIVPLAT (0) 904 /* @brief Has bus clock divider SCG_CSR[DIVBUS]. */ 905 #define FSL_FEATURE_SCG_HAS_DIVBUS (0) 906 /* @brief Has external clock divide ratio SCG_CSR[DIVEXT]. */ 907 #define FSL_FEATURE_SCG_HAS_DIVEXT (0) 908 /* @brief Has OSC capacitor setting SOSCCFG[SC2P ~ SC16P]. */ 909 #define FSL_FEATURE_SCG_HAS_OSC_SCXP (0) 910 /* @brief Has OSC freq range SOSCCFG[RANGE]. */ 911 #define FSL_FEATURE_SCG_HAS_SOSC_RANGE (1) 912 /* @brief Has SOSCCSR[SOSCERCLKEN]. */ 913 #define FSL_FEATURE_SCG_HAS_OSC_ERCLK (1) 914 /* @brief Has CLKOUT configure register SCG_CLKOUTCNFG. */ 915 #define FSL_FEATURE_SCG_HAS_CLKOUTCNFG (1) 916 /* @brief Has SCG_SOSCDIV[SOSCDIV1]. */ 917 #define FSL_FEATURE_SCG_HAS_SOSCDIV1 (0) 918 /* @brief Has SCG_SOSCDIV[SOSCDIV3]. */ 919 #define FSL_FEATURE_SCG_HAS_SOSCDIV3 (0) 920 /* @brief Has SCG_SIRCDIV[SIRCDIV1]. */ 921 #define FSL_FEATURE_SCG_HAS_SIRCDIV1 (0) 922 /* @brief Has SCG_SIRCDIV[SIRCDIV3]. */ 923 #define FSL_FEATURE_SCG_HAS_SIRCDIV3 (0) 924 /* @brief Has SCG_SIRCCSR[LPOPO]. */ 925 #define FSL_FEATURE_SCG_HAS_SIRC_LPOPO (0) 926 /* @brief Has SCG_FIRCDIV[FIRCDIV1]. */ 927 #define FSL_FEATURE_SCG_HAS_FIRCDIV1 (0) 928 /* @brief Has SCG_FIRCDIV[FIRCDIV3]. */ 929 #define FSL_FEATURE_SCG_HAS_FIRCDIV3 (0) 930 /* @brief Has SCG_FIRCCSR[FIRCLPEN]. */ 931 #define FSL_FEATURE_SCG_HAS_FIRCLPEN (1) 932 /* @brief Has SCG_FIRCCSR[FIRCREGOFF]. */ 933 #define FSL_FEATURE_SCG_HAS_FIRCREGOFF (1) 934 /* @brief Has SCG_SPLLDIV[SPLLDIV1]. */ 935 #define FSL_FEATURE_SCG_HAS_SPLLDIV1 (0) 936 /* @brief Has SCG_SPLLDIV[SPLLDIV3]. */ 937 #define FSL_FEATURE_SCG_HAS_SPLLDIV3 (0) 938 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV1]. */ 939 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV1 (0) 940 /* @brief Has SCG_SPLLCFG[PLLPOSTDIV2]. */ 941 #define FSL_FEATURE_SCG_HAS_SPLLPOSTDIV2 (0) 942 /* @brief Has SCG_SPLLCFG[PLLS]. */ 943 #define FSL_FEATURE_SCG_HAS_SPLL_PLLS (0) 944 /* @brief Has SCG_SPLLCFG[BYPASS]. */ 945 #define FSL_FEATURE_SCG_HAS_SPLL_BYPASS (0) 946 /* @brief Has SCG_SPLLCFG[PFDSEL]. */ 947 #define FSL_FEATURE_SCG_HAS_SPLL_PFDSEL (0) 948 /* @brief Has SCG_SPLLCSR[SPLLCM]. */ 949 #define FSL_FEATURE_SCG_HAS_SPLL_MONITOR (0) 950 /* @brief Has SCG_LPFLLDIV[FLLDIV1]. */ 951 #define FSL_FEATURE_SCG_HAS_FLLDIV1 (0) 952 /* @brief Has SCG_LPFLLDIV[FLLDIV3]. */ 953 #define FSL_FEATURE_SCG_HAS_FLLDIV3 (0) 954 /* @brief Has low power FLL, SCG_LPFLLCSR. */ 955 #define FSL_FEATURE_SCG_HAS_LPFLL (1) 956 /* @brief Has low power FLL stop enable. */ 957 #define FSL_FEATURE_SCG_HAS_LPFLLSTEN (0) 958 /* @brief Has system PLL, SCG_SPLLCSR. */ 959 #define FSL_FEATURE_SCG_HAS_SPLL (0) 960 /* @brief Has system PLL PFD, SCG_SPLLPFD. */ 961 #define FSL_FEATURE_SCG_HAS_SPLLPFD (0) 962 /* @brief Has auxiliary PLL, SCG_APLLCSR. */ 963 #define FSL_FEATURE_SCG_HAS_APLL (0) 964 /* @brief Has RTC OSC control, SCG_ROSCCSR. */ 965 #define FSL_FEATURE_SCG_HAS_ROSC (0) 966 /* @brief Has RTC OSC clock source. */ 967 #define FSL_FEATURE_SCG_HAS_ROSC_SYS_CLK_SRC (0) 968 /* @brief Has RTC OSC clock out select. */ 969 #define FSL_FEATURE_SCG_HAS_ROSC_CLKOUT (0) 970 /* @brief Has SIRC clock out select. */ 971 #define FSL_FEATURE_SCG_HAS_EXT_CLKOUT (0) 972 /* @brief Has FIRC trim source USB0 Start of Frame. */ 973 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB0 (0) 974 /* @brief Has FIRC trim source USB1 Start of Frame. */ 975 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_USB1 (0) 976 /* @brief Has FIRC trim source system OSC. */ 977 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_SOSC (1) 978 /* @brief Has FIRC trim source RTC OSC. */ 979 #define FSL_FEATURE_SCG_HAS_FIRC_TRIMSRC_RTCOSC (0) 980 981 /* SMC module features */ 982 983 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 984 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 985 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 986 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 987 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 988 #define FSL_FEATURE_SMC_HAS_PORPO (0) 989 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 990 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 991 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 992 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 993 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 994 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 995 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 996 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 997 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 998 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 999 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1000 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1001 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1002 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (0) 1003 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1004 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (0) 1005 /* @brief Has stop submode. */ 1006 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (0) 1007 /* @brief Has stop submode 0(state VLLS0 of register bit STOPCTRL[VLLSM]). */ 1008 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (0) 1009 /* @brief Has stop submode 2(state VLLS2 of register bit STOPCTRL[VLLSM]). */ 1010 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (0) 1011 /* @brief Has SMC_PARAM. */ 1012 #define FSL_FEATURE_SMC_HAS_PARAM (1) 1013 /* @brief Has SMC_VERID. */ 1014 #define FSL_FEATURE_SMC_HAS_VERID (1) 1015 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1016 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1017 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1018 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1019 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1020 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1021 /* @brief Width of SMC registers. */ 1022 #define FSL_FEATURE_SMC_REG_WIDTH (32) 1023 1024 /* SysTick module features */ 1025 1026 /* @brief Systick has external reference clock. */ 1027 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1028 /* @brief Systick external reference clock is core clock divided by this value. */ 1029 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1030 1031 /* WDOG module features */ 1032 1033 /* @brief Watchdog is available. */ 1034 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1035 /* @brief WDOG_CNT can be 32-bit written. */ 1036 #define FSL_FEATURE_WDOG_HAS_32BIT_ACCESS (1) 1037 1038 #endif /* _MKE14Z7_FEATURES_H_ */ 1039 1040
