1 /* 2 ** ################################################################### 3 ** Version: rev. 2.9, 2015-06-08 4 ** Build: b210913 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2013-09-02) 20 ** Initial version. 21 ** - rev. 1.1 (2014-01-30) 22 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 23 ** - rev. 2.0 (2014-02-17) 24 ** Register accessor macros added to the memory map. 25 ** Symbols for Processor Expert memory map compatibility added to the memory map. 26 ** Startup file for gcc has been updated according to CMSIS 3.2. 27 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 28 ** Update according to reference manual rev. 2 29 ** - rev. 2.1 (2014-04-16) 30 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 31 ** - rev. 2.2 (2014-10-14) 32 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. 33 ** - rev. 2.3 (2014-11-20) 34 ** Update according to reverence manual K65P169M180SF5RMV2_NDA, Rev. 0 Draft A, October 2014. 35 ** Update of SystemInit() to use 16MHz external crystal. 36 ** - rev. 2.4 (2015-01-21) 37 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 38 ** - rev. 2.5 (2015-02-19) 39 ** Renamed interrupt vector LLW to LLWU. 40 ** - rev. 2.6 (2015-05-19) 41 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 42 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 43 ** Added features for PDB and PORT. 44 ** - rev. 2.7 (2015-05-25) 45 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 46 ** - rev. 2.8 (2015-05-27) 47 ** Several USB features added. 48 ** - rev. 2.9 (2015-06-08) 49 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 50 ** 51 ** ################################################################### 52 */ 53 54 #ifndef _MK65F18_FEATURES_H_ 55 #define _MK65F18_FEATURES_H_ 56 57 /* SOC module features */ 58 59 /* @brief ADC16 availability on the SoC. */ 60 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 61 /* @brief AIPS availability on the SoC. */ 62 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 63 /* @brief AXBS availability on the SoC. */ 64 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 65 /* @brief FLEXCAN availability on the SoC. */ 66 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (2) 67 /* @brief MMCAU availability on the SoC. */ 68 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 69 /* @brief CMP availability on the SoC. */ 70 #define FSL_FEATURE_SOC_CMP_COUNT (4) 71 /* @brief CMT availability on the SoC. */ 72 #define FSL_FEATURE_SOC_CMT_COUNT (1) 73 /* @brief CRC availability on the SoC. */ 74 #define FSL_FEATURE_SOC_CRC_COUNT (1) 75 /* @brief DAC availability on the SoC. */ 76 #define FSL_FEATURE_SOC_DAC_COUNT (2) 77 /* @brief EDMA availability on the SoC. */ 78 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 79 /* @brief DMAMUX availability on the SoC. */ 80 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 81 /* @brief DSPI availability on the SoC. */ 82 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 83 /* @brief ENET availability on the SoC. */ 84 #define FSL_FEATURE_SOC_ENET_COUNT (1) 85 /* @brief EWM availability on the SoC. */ 86 #define FSL_FEATURE_SOC_EWM_COUNT (1) 87 /* @brief FB availability on the SoC. */ 88 #define FSL_FEATURE_SOC_FB_COUNT (1) 89 /* @brief FMC availability on the SoC. */ 90 #define FSL_FEATURE_SOC_FMC_COUNT (1) 91 /* @brief FTFE availability on the SoC. */ 92 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 93 /* @brief FTM availability on the SoC. */ 94 #define FSL_FEATURE_SOC_FTM_COUNT (4) 95 /* @brief GPIO availability on the SoC. */ 96 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 97 /* @brief I2C availability on the SoC. */ 98 #define FSL_FEATURE_SOC_I2C_COUNT (4) 99 /* @brief I2S availability on the SoC. */ 100 #define FSL_FEATURE_SOC_I2S_COUNT (1) 101 /* @brief LLWU availability on the SoC. */ 102 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 103 /* @brief LMEM availability on the SoC. */ 104 #define FSL_FEATURE_SOC_LMEM_COUNT (1) 105 /* @brief LPTMR availability on the SoC. */ 106 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 107 /* @brief LPUART availability on the SoC. */ 108 #define FSL_FEATURE_SOC_LPUART_COUNT (1) 109 /* @brief MCG availability on the SoC. */ 110 #define FSL_FEATURE_SOC_MCG_COUNT (1) 111 /* @brief MCM availability on the SoC. */ 112 #define FSL_FEATURE_SOC_MCM_COUNT (1) 113 /* @brief SYSMPU availability on the SoC. */ 114 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 115 /* @brief OSC availability on the SoC. */ 116 #define FSL_FEATURE_SOC_OSC_COUNT (1) 117 /* @brief PDB availability on the SoC. */ 118 #define FSL_FEATURE_SOC_PDB_COUNT (1) 119 /* @brief PIT availability on the SoC. */ 120 #define FSL_FEATURE_SOC_PIT_COUNT (1) 121 /* @brief PMC availability on the SoC. */ 122 #define FSL_FEATURE_SOC_PMC_COUNT (1) 123 /* @brief PORT availability on the SoC. */ 124 #define FSL_FEATURE_SOC_PORT_COUNT (5) 125 /* @brief RCM availability on the SoC. */ 126 #define FSL_FEATURE_SOC_RCM_COUNT (1) 127 /* @brief RFSYS availability on the SoC. */ 128 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 129 /* @brief RFVBAT availability on the SoC. */ 130 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 131 /* @brief RNG availability on the SoC. */ 132 #define FSL_FEATURE_SOC_RNG_COUNT (1) 133 /* @brief RTC availability on the SoC. */ 134 #define FSL_FEATURE_SOC_RTC_COUNT (1) 135 /* @brief SDHC availability on the SoC. */ 136 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 137 /* @brief SDRAM availability on the SoC. */ 138 #define FSL_FEATURE_SOC_SDRAM_COUNT (1) 139 /* @brief SIM availability on the SoC. */ 140 #define FSL_FEATURE_SOC_SIM_COUNT (1) 141 /* @brief SMC availability on the SoC. */ 142 #define FSL_FEATURE_SOC_SMC_COUNT (1) 143 /* @brief TPM availability on the SoC. */ 144 #define FSL_FEATURE_SOC_TPM_COUNT (2) 145 /* @brief TSI availability on the SoC. */ 146 #define FSL_FEATURE_SOC_TSI_COUNT (1) 147 /* @brief UART availability on the SoC. */ 148 #define FSL_FEATURE_SOC_UART_COUNT (5) 149 /* @brief USB availability on the SoC. */ 150 #define FSL_FEATURE_SOC_USB_COUNT (1) 151 /* @brief USBDCD availability on the SoC. */ 152 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 153 /* @brief USBHS availability on the SoC. */ 154 #define FSL_FEATURE_SOC_USBHS_COUNT (1) 155 /* @brief USBHSDCD availability on the SoC. */ 156 #define FSL_FEATURE_SOC_USBHSDCD_COUNT (1) 157 /* @brief USBPHY availability on the SoC. */ 158 #define FSL_FEATURE_SOC_USBPHY_COUNT (1) 159 /* @brief VREF availability on the SoC. */ 160 #define FSL_FEATURE_SOC_VREF_COUNT (1) 161 /* @brief WDOG availability on the SoC. */ 162 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 163 164 /* ADC16 module features */ 165 166 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 167 #define FSL_FEATURE_ADC16_HAS_PGA (0) 168 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 169 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 170 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 171 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 172 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 173 #define FSL_FEATURE_ADC16_HAS_DMA (1) 174 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 175 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 176 /* @brief Has FIFO (bit SC4[AFDEP]). */ 177 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 178 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 179 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 180 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 181 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 182 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 183 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 184 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 185 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 186 /* @brief Has HW averaging (bit SC3[AVGE]). */ 187 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 188 /* @brief Has offset correction (register OFS). */ 189 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 190 /* @brief Maximum ADC resolution. */ 191 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 192 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 193 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 194 195 /* FLEXCAN module features */ 196 197 /* @brief Message buffer size */ 198 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 199 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 200 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) 201 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 202 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) 203 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 204 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 205 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 206 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 207 /* @brief Instance has extended bit timing register (register CBT). */ 208 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) 209 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 210 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) 211 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 212 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) 213 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 214 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 215 /* @brief Has bitfield name BUF31TO0M. */ 216 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) 217 /* @brief Number of interrupt vectors. */ 218 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 219 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 220 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 221 222 /* CMP module features */ 223 224 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 225 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (1) 226 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 227 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 228 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 229 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 230 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 231 #define FSL_FEATURE_CMP_HAS_DMA (1) 232 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 233 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) 234 /* @brief Has DAC Test function in CMP (register DACTEST). */ 235 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 236 237 /* CRC module features */ 238 239 /* @brief Has data register with name CRC */ 240 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 241 242 /* DAC module features */ 243 244 /* @brief Define the size of hardware buffer */ 245 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 246 /* @brief Define whether the buffer supports watermark event detection or not. */ 247 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 248 /* @brief Define whether the buffer supports watermark selection detection or not. */ 249 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 250 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 251 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 252 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 253 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 254 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 255 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 256 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 257 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 258 /* @brief Define whether FIFO buffer mode is available or not. */ 259 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 260 /* @brief Define whether swing buffer mode is available or not.. */ 261 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 262 263 /* EDMA module features */ 264 265 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 266 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (32) 267 /* @brief Total number of DMA channels on all modules. */ 268 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (32) 269 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 270 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (2) 271 /* @brief Has DMA_Error interrupt vector. */ 272 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 273 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 274 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (32) 275 /* @brief Channel IRQ entry shared offset. */ 276 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (16) 277 /* @brief If 8 bytes transfer supported. */ 278 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 279 /* @brief If 16 bytes transfer supported. */ 280 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 281 282 /* DMAMUX module features */ 283 284 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 285 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (32) 286 /* @brief Total number of DMA channels on all modules. */ 287 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (32) 288 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 289 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 290 /* @brief Register CHCFGn width. */ 291 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 292 293 /* ENET module features */ 294 295 /* @brief Support Interrupt Coalesce */ 296 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (0) 297 /* @brief Queue Size. */ 298 #define FSL_FEATURE_ENET_QUEUE (1) 299 /* @brief Has AVB Support. */ 300 #define FSL_FEATURE_ENET_HAS_AVB (0) 301 /* @brief Has Timer Pulse Width control. */ 302 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) 303 /* @brief Has Extend MDIO Support. */ 304 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (1) 305 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 306 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) 307 /* @brief Support Interrupt Coalesce for each instance */ 308 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) 309 /* @brief Queue Size for each instance. */ 310 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) 311 /* @brief Has AVB Support for each instance. */ 312 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0) 313 /* @brief Has Timer Pulse Width control for each instance. */ 314 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) 315 /* @brief Has Extend MDIO Support for each instance. */ 316 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (1) 317 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 318 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) 319 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 320 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 321 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 322 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) 323 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 324 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) 325 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ 326 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (1) 327 328 /* EWM module features */ 329 330 /* @brief Has clock select (register CLKCTRL). */ 331 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 332 /* @brief Has clock prescaler (register CLKPRESCALER). */ 333 #define FSL_FEATURE_EWM_HAS_PRESCALER (0) 334 335 /* FLEXBUS module features */ 336 337 /* No feature definitions */ 338 339 /* FLASH module features */ 340 341 #if defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FN2M0VMI18) 342 /* @brief Is of type FTFA. */ 343 #define FSL_FEATURE_FLASH_IS_FTFA (0) 344 /* @brief Is of type FTFE. */ 345 #define FSL_FEATURE_FLASH_IS_FTFE (1) 346 /* @brief Is of type FTFL. */ 347 #define FSL_FEATURE_FLASH_IS_FTFL (0) 348 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 349 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 350 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 351 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 352 /* @brief Has EEPROM region protection (register FEPROT). */ 353 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 354 /* @brief Has data flash region protection (register FDPROT). */ 355 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 356 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 357 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 358 /* @brief Has flash cache control in FMC module. */ 359 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 360 /* @brief Has flash cache control in MCM module. */ 361 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 362 /* @brief Has flash cache control in MSCM module. */ 363 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 364 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 365 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 366 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 367 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 368 /* @brief P-Flash start address. */ 369 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 370 /* @brief P-Flash block count. */ 371 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (4) 372 /* @brief P-Flash block size. */ 373 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 374 /* @brief P-Flash sector size. */ 375 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 376 /* @brief P-Flash write unit size. */ 377 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 378 /* @brief P-Flash data path width. */ 379 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 380 /* @brief P-Flash block swap feature. */ 381 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) 382 /* @brief P-Flash protection region count. */ 383 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 384 /* @brief Has FlexNVM memory. */ 385 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 386 /* @brief Has FlexNVM alias. */ 387 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 388 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 389 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 390 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 391 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 392 /* @brief FlexNVM block count. */ 393 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 394 /* @brief FlexNVM block size. */ 395 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 396 /* @brief FlexNVM sector size. */ 397 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 398 /* @brief FlexNVM write unit size. */ 399 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 400 /* @brief FlexNVM data path width. */ 401 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 402 /* @brief Has FlexRAM memory. */ 403 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 404 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 405 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 406 /* @brief FlexRAM size. */ 407 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 408 /* @brief Has 0x00 Read 1s Block command. */ 409 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 410 /* @brief Has 0x01 Read 1s Section command. */ 411 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 412 /* @brief Has 0x02 Program Check command. */ 413 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 414 /* @brief Has 0x03 Read Resource command. */ 415 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 416 /* @brief Has 0x06 Program Longword command. */ 417 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 418 /* @brief Has 0x07 Program Phrase command. */ 419 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 420 /* @brief Has 0x08 Erase Flash Block command. */ 421 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 422 /* @brief Has 0x09 Erase Flash Sector command. */ 423 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 424 /* @brief Has 0x0B Program Section command. */ 425 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 426 /* @brief Has 0x40 Read 1s All Blocks command. */ 427 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 428 /* @brief Has 0x41 Read Once command. */ 429 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 430 /* @brief Has 0x43 Program Once command. */ 431 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 432 /* @brief Has 0x44 Erase All Blocks command. */ 433 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 434 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 435 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 436 /* @brief Has 0x46 Swap Control command. */ 437 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) 438 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 439 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 440 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 441 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 442 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 443 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 444 /* @brief Has 0x80 Program Partition command. */ 445 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 446 /* @brief Has 0x81 Set FlexRAM Function command. */ 447 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 448 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 449 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 450 /* @brief P-Flash Erase sector command address alignment. */ 451 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 452 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 453 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 454 /* @brief P-Flash Read resource command address alignment. */ 455 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 456 /* @brief P-Flash Program check command address alignment. */ 457 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 458 /* @brief P-Flash Program check command address alignment. */ 459 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) 460 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 461 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 462 /* @brief FlexNVM Erase sector command address alignment. */ 463 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 464 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 465 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 466 /* @brief FlexNVM Read resource command address alignment. */ 467 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 468 /* @brief FlexNVM Program check command address alignment. */ 469 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 470 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 471 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 472 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 473 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 474 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 475 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 476 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 477 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 478 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 479 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 480 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 481 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 482 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 483 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 484 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 485 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 486 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 487 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 488 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 489 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 490 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 491 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 492 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 493 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 494 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 495 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 496 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 497 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 498 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 499 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 500 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 501 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 502 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 503 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 504 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 505 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 506 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 507 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 508 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 509 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 510 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 511 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 512 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 513 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 514 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 515 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 516 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 517 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 518 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 519 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 520 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 521 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 522 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 523 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 524 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 525 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 526 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 527 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 528 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 529 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 530 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 531 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 532 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 533 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 534 #elif defined(CPU_MK65FX1M0CAC18) || defined(CPU_MK65FX1M0VMI18) 535 /* @brief Is of type FTFA. */ 536 #define FSL_FEATURE_FLASH_IS_FTFA (0) 537 /* @brief Is of type FTFE. */ 538 #define FSL_FEATURE_FLASH_IS_FTFE (1) 539 /* @brief Is of type FTFL. */ 540 #define FSL_FEATURE_FLASH_IS_FTFL (0) 541 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 542 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 543 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 544 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 545 /* @brief Has EEPROM region protection (register FEPROT). */ 546 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 547 /* @brief Has data flash region protection (register FDPROT). */ 548 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 549 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 550 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (1) 551 /* @brief Has flash cache control in FMC module. */ 552 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 553 /* @brief Has flash cache control in MCM module. */ 554 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 555 /* @brief Has flash cache control in MSCM module. */ 556 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 557 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 558 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 559 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 560 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 561 /* @brief P-Flash start address. */ 562 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 563 /* @brief P-Flash block count. */ 564 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 565 /* @brief P-Flash block size. */ 566 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 567 /* @brief P-Flash sector size. */ 568 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 569 /* @brief P-Flash write unit size. */ 570 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 571 /* @brief P-Flash data path width. */ 572 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 573 /* @brief P-Flash block swap feature. */ 574 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) 575 /* @brief P-Flash protection region count. */ 576 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (16) 577 /* @brief Has FlexNVM memory. */ 578 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 579 /* @brief Has FlexNVM alias. */ 580 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 581 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 582 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 583 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 584 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 585 /* @brief FlexNVM block count. */ 586 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 587 /* @brief FlexNVM block size. */ 588 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (262144) 589 /* @brief FlexNVM sector size. */ 590 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096) 591 /* @brief FlexNVM write unit size. */ 592 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 593 /* @brief FlexNVM data path width. */ 594 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16) 595 /* @brief Has FlexRAM memory. */ 596 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 597 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 598 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 599 /* @brief FlexRAM size. */ 600 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 601 /* @brief Has 0x00 Read 1s Block command. */ 602 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 603 /* @brief Has 0x01 Read 1s Section command. */ 604 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 605 /* @brief Has 0x02 Program Check command. */ 606 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 607 /* @brief Has 0x03 Read Resource command. */ 608 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 609 /* @brief Has 0x06 Program Longword command. */ 610 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 611 /* @brief Has 0x07 Program Phrase command. */ 612 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 613 /* @brief Has 0x08 Erase Flash Block command. */ 614 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 615 /* @brief Has 0x09 Erase Flash Sector command. */ 616 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 617 /* @brief Has 0x0B Program Section command. */ 618 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 619 /* @brief Has 0x40 Read 1s All Blocks command. */ 620 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 621 /* @brief Has 0x41 Read Once command. */ 622 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 623 /* @brief Has 0x43 Program Once command. */ 624 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 625 /* @brief Has 0x44 Erase All Blocks command. */ 626 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 627 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 628 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 629 /* @brief Has 0x46 Swap Control command. */ 630 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) 631 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 632 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 633 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 634 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 635 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 636 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 637 /* @brief Has 0x80 Program Partition command. */ 638 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 639 /* @brief Has 0x81 Set FlexRAM Function command. */ 640 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 641 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 642 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 643 /* @brief P-Flash Erase sector command address alignment. */ 644 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 645 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 646 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 647 /* @brief P-Flash Read resource command address alignment. */ 648 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 649 /* @brief P-Flash Program check command address alignment. */ 650 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 651 /* @brief P-Flash Program check command address alignment. */ 652 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) 653 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 654 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16) 655 /* @brief FlexNVM Erase sector command address alignment. */ 656 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16) 657 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 658 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16) 659 /* @brief FlexNVM Read resource command address alignment. */ 660 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 661 /* @brief FlexNVM Program check command address alignment. */ 662 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 663 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 664 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00040000U) 665 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 666 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 667 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 668 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 669 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 670 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00038000U) 671 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 672 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00030000U) 673 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 674 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00020000U) 675 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 676 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0x00000000U) 677 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 678 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 679 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 680 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000U) 681 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 682 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 683 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 684 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 685 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 686 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000U) 687 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 688 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000U) 689 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 690 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000U) 691 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 692 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0x00040000U) 693 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 694 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00040000U) 695 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 696 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 697 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 698 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 699 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 700 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 701 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 702 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 703 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 704 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 705 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 706 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 707 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 708 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 709 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 710 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 711 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 712 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 713 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 714 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 715 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 716 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 717 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 718 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 719 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 720 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 721 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 722 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 723 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 724 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 725 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 726 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 727 #endif /* defined(CPU_MK65FN2M0CAC18) || defined(CPU_MK65FN2M0VMI18) */ 728 729 /* FTM module features */ 730 731 /* @brief Number of channels. */ 732 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 733 (((x) == FTM0) ? (8) : \ 734 (((x) == FTM1) ? (2) : \ 735 (((x) == FTM2) ? (2) : \ 736 (((x) == FTM3) ? (8) : (-1))))) 737 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 738 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 739 /* @brief Has extended deadtime value. */ 740 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 741 /* @brief Enable pwm output for the module. */ 742 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 743 /* @brief Has half-cycle reload for the module. */ 744 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 745 /* @brief Has reload interrupt. */ 746 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 747 /* @brief Has reload initialization trigger. */ 748 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 749 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 750 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 751 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 752 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 753 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 754 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 755 /* @brief Has no QDCTRL. */ 756 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 757 /* @brief If instance has only TPM function. */ 758 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 759 760 /* GPIO module features */ 761 762 /* @brief Has GPIO attribute checker register (GACR). */ 763 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 764 765 /* I2C module features */ 766 767 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 768 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 769 /* @brief Maximum supported baud rate in kilobit per second. */ 770 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 771 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 772 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 773 /* @brief Has DMA support (register bit C1[DMAEN]). */ 774 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 775 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 776 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 777 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 778 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 779 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 780 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 781 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 782 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 783 /* @brief Has control of the drive capability of the I2C pins. */ 784 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 785 /* @brief Has double buffering support (register S2). */ 786 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 787 /* @brief Has double buffer enable. */ 788 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 789 790 /* SAI module features */ 791 792 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 793 #define FSL_FEATURE_SAI_FIFO_COUNT (8) 794 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 795 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) 796 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 797 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 798 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 799 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (1) 800 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 801 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (1) 802 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 803 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (1) 804 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 805 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (1) 806 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 807 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 808 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 809 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 810 /* @brief Ihe interrupt source number */ 811 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 812 /* @brief Has register of MCR. */ 813 #define FSL_FEATURE_SAI_HAS_MCR (1) 814 /* @brief Has register of MDR */ 815 #define FSL_FEATURE_SAI_HAS_MDR (1) 816 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 817 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 818 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 819 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 820 821 /* LLWU module features */ 822 823 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 824 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (32) 825 /* @brief Has pins 8-15 connected to LLWU device. */ 826 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 827 /* @brief Maximum number of internal modules connected to LLWU device. */ 828 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 829 /* @brief Number of digital filters. */ 830 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (4) 831 /* @brief Has MF register. */ 832 #define FSL_FEATURE_LLWU_HAS_MF (1) 833 /* @brief Has PF register. */ 834 #define FSL_FEATURE_LLWU_HAS_PF (1) 835 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 836 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (0) 837 /* @brief Has no internal module wakeup flag register. */ 838 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 839 /* @brief Has external pin 0 connected to LLWU device. */ 840 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 841 /* @brief Index of port of external pin. */ 842 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 843 /* @brief Number of external pin port on specified port. */ 844 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 845 /* @brief Has external pin 1 connected to LLWU device. */ 846 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 847 /* @brief Index of port of external pin. */ 848 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 849 /* @brief Number of external pin port on specified port. */ 850 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 851 /* @brief Has external pin 2 connected to LLWU device. */ 852 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 853 /* @brief Index of port of external pin. */ 854 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 855 /* @brief Number of external pin port on specified port. */ 856 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 857 /* @brief Has external pin 3 connected to LLWU device. */ 858 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 859 /* @brief Index of port of external pin. */ 860 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 861 /* @brief Number of external pin port on specified port. */ 862 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 863 /* @brief Has external pin 4 connected to LLWU device. */ 864 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 865 /* @brief Index of port of external pin. */ 866 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 867 /* @brief Number of external pin port on specified port. */ 868 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 869 /* @brief Has external pin 5 connected to LLWU device. */ 870 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 871 /* @brief Index of port of external pin. */ 872 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 873 /* @brief Number of external pin port on specified port. */ 874 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 875 /* @brief Has external pin 6 connected to LLWU device. */ 876 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 877 /* @brief Index of port of external pin. */ 878 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 879 /* @brief Number of external pin port on specified port. */ 880 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 881 /* @brief Has external pin 7 connected to LLWU device. */ 882 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 883 /* @brief Index of port of external pin. */ 884 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 885 /* @brief Number of external pin port on specified port. */ 886 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 887 /* @brief Has external pin 8 connected to LLWU device. */ 888 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 889 /* @brief Index of port of external pin. */ 890 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 891 /* @brief Number of external pin port on specified port. */ 892 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 893 /* @brief Has external pin 9 connected to LLWU device. */ 894 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 895 /* @brief Index of port of external pin. */ 896 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 897 /* @brief Number of external pin port on specified port. */ 898 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 899 /* @brief Has external pin 10 connected to LLWU device. */ 900 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 901 /* @brief Index of port of external pin. */ 902 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 903 /* @brief Number of external pin port on specified port. */ 904 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 905 /* @brief Has external pin 11 connected to LLWU device. */ 906 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 907 /* @brief Index of port of external pin. */ 908 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 909 /* @brief Number of external pin port on specified port. */ 910 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 911 /* @brief Has external pin 12 connected to LLWU device. */ 912 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 913 /* @brief Index of port of external pin. */ 914 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 915 /* @brief Number of external pin port on specified port. */ 916 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 917 /* @brief Has external pin 13 connected to LLWU device. */ 918 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 919 /* @brief Index of port of external pin. */ 920 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 921 /* @brief Number of external pin port on specified port. */ 922 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 923 /* @brief Has external pin 14 connected to LLWU device. */ 924 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 925 /* @brief Index of port of external pin. */ 926 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 927 /* @brief Number of external pin port on specified port. */ 928 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 929 /* @brief Has external pin 15 connected to LLWU device. */ 930 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 931 /* @brief Index of port of external pin. */ 932 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 933 /* @brief Number of external pin port on specified port. */ 934 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 935 /* @brief Has external pin 16 connected to LLWU device. */ 936 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (1) 937 /* @brief Index of port of external pin. */ 938 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (GPIOE_IDX) 939 /* @brief Number of external pin port on specified port. */ 940 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (6) 941 /* @brief Has external pin 17 connected to LLWU device. */ 942 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (1) 943 /* @brief Index of port of external pin. */ 944 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (GPIOE_IDX) 945 /* @brief Number of external pin port on specified port. */ 946 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (9) 947 /* @brief Has external pin 18 connected to LLWU device. */ 948 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (1) 949 /* @brief Index of port of external pin. */ 950 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (GPIOE_IDX) 951 /* @brief Number of external pin port on specified port. */ 952 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (10) 953 /* @brief Has external pin 19 connected to LLWU device. */ 954 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (1) 955 /* @brief Index of port of external pin. */ 956 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (GPIOE_IDX) 957 /* @brief Number of external pin port on specified port. */ 958 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (17) 959 /* @brief Has external pin 20 connected to LLWU device. */ 960 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (1) 961 /* @brief Index of port of external pin. */ 962 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (GPIOE_IDX) 963 /* @brief Number of external pin port on specified port. */ 964 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (18) 965 /* @brief Has external pin 21 connected to LLWU device. */ 966 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (1) 967 /* @brief Index of port of external pin. */ 968 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (GPIOE_IDX) 969 /* @brief Number of external pin port on specified port. */ 970 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (25) 971 /* @brief Has external pin 22 connected to LLWU device. */ 972 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (1) 973 /* @brief Index of port of external pin. */ 974 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (GPIOA_IDX) 975 /* @brief Number of external pin port on specified port. */ 976 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (10) 977 /* @brief Has external pin 23 connected to LLWU device. */ 978 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (1) 979 /* @brief Index of port of external pin. */ 980 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (GPIOA_IDX) 981 /* @brief Number of external pin port on specified port. */ 982 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (11) 983 /* @brief Has external pin 24 connected to LLWU device. */ 984 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (1) 985 /* @brief Index of port of external pin. */ 986 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (GPIOD_IDX) 987 /* @brief Number of external pin port on specified port. */ 988 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (8) 989 /* @brief Has external pin 25 connected to LLWU device. */ 990 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (1) 991 /* @brief Index of port of external pin. */ 992 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (GPIOD_IDX) 993 /* @brief Number of external pin port on specified port. */ 994 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (11) 995 /* @brief Has external pin 26 connected to LLWU device. */ 996 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 997 /* @brief Index of port of external pin. */ 998 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 999 /* @brief Number of external pin port on specified port. */ 1000 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1001 /* @brief Has external pin 27 connected to LLWU device. */ 1002 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1003 /* @brief Index of port of external pin. */ 1004 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1005 /* @brief Number of external pin port on specified port. */ 1006 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1007 /* @brief Has external pin 28 connected to LLWU device. */ 1008 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1009 /* @brief Index of port of external pin. */ 1010 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1011 /* @brief Number of external pin port on specified port. */ 1012 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1013 /* @brief Has external pin 29 connected to LLWU device. */ 1014 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (1) 1015 /* @brief Index of port of external pin. */ 1016 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1017 /* @brief Number of external pin port on specified port. */ 1018 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1019 /* @brief Has external pin 30 connected to LLWU device. */ 1020 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (1) 1021 /* @brief Index of port of external pin. */ 1022 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1023 /* @brief Number of external pin port on specified port. */ 1024 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1025 /* @brief Has external pin 31 connected to LLWU device. */ 1026 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (1) 1027 /* @brief Index of port of external pin. */ 1028 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1029 /* @brief Number of external pin port on specified port. */ 1030 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1031 /* @brief Has internal module 0 connected to LLWU device. */ 1032 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1033 /* @brief Has internal module 1 connected to LLWU device. */ 1034 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1035 /* @brief Has internal module 2 connected to LLWU device. */ 1036 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1037 /* @brief Has internal module 3 connected to LLWU device. */ 1038 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1039 /* @brief Has internal module 4 connected to LLWU device. */ 1040 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (1) 1041 /* @brief Has internal module 5 connected to LLWU device. */ 1042 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1043 /* @brief Has internal module 6 connected to LLWU device. */ 1044 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1045 /* @brief Has internal module 7 connected to LLWU device. */ 1046 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1047 /* @brief Has Version ID Register (LLWU_VERID). */ 1048 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1049 /* @brief Has Parameter Register (LLWU_PARAM). */ 1050 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1051 /* @brief Width of registers of the LLWU. */ 1052 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1053 /* @brief Has DMA Enable register (LLWU_DE). */ 1054 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1055 1056 /* LMEM module features */ 1057 1058 /* @brief Has process identifier support. */ 1059 #define FSL_FEATURE_LMEM_HAS_SYSTEMBUS_CACHE (0) 1060 /* @brief Has L1 cache. */ 1061 #define FSL_FEATURE_HAS_L1CACHE (1) 1062 /* @brief L1 ICACHE line size in byte. */ 1063 #define FSL_FEATURE_L1ICACHE_LINESIZE_BYTE (16) 1064 /* @brief L1 DCACHE line size in byte. */ 1065 #define FSL_FEATURE_L1DCACHE_LINESIZE_BYTE (16) 1066 1067 /* LPTMR module features */ 1068 1069 /* @brief Has shared interrupt handler with another LPTMR module. */ 1070 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1071 /* @brief Whether LPTMR counter is 32 bits width. */ 1072 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1073 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1074 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1075 1076 /* LPUART module features */ 1077 1078 /* @brief LPUART0 and LPUART1 has shared interrupt vector. */ 1079 #define FSL_FEATURE_LPUART_HAS_SHARED_IRQ0_IRQ1 (0) 1080 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1081 #define FSL_FEATURE_LPUART_HAS_IRQ_EXTENDED_FUNCTIONS (0) 1082 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1083 #define FSL_FEATURE_LPUART_HAS_LOW_POWER_UART_SUPPORT (1) 1084 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1085 #define FSL_FEATURE_LPUART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1086 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1087 #define FSL_FEATURE_LPUART_HAS_FIFO (0) 1088 /* @brief Has 32-bit register MODIR */ 1089 #define FSL_FEATURE_LPUART_HAS_MODIR (1) 1090 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1091 #define FSL_FEATURE_LPUART_HAS_MODEM_SUPPORT (1) 1092 /* @brief Infrared (modulation) is supported. */ 1093 #define FSL_FEATURE_LPUART_HAS_IR_SUPPORT (1) 1094 /* @brief 2 bits long stop bit is available. */ 1095 #define FSL_FEATURE_LPUART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1096 /* @brief If 10-bit mode is supported. */ 1097 #define FSL_FEATURE_LPUART_HAS_10BIT_DATA_SUPPORT (1) 1098 /* @brief If 7-bit mode is supported. */ 1099 #define FSL_FEATURE_LPUART_HAS_7BIT_DATA_SUPPORT (0) 1100 /* @brief Baud rate fine adjustment is available. */ 1101 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (0) 1102 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1103 #define FSL_FEATURE_LPUART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (1) 1104 /* @brief Baud rate oversampling is available. */ 1105 #define FSL_FEATURE_LPUART_HAS_RX_RESYNC_SUPPORT (1) 1106 /* @brief Baud rate oversampling is available. */ 1107 #define FSL_FEATURE_LPUART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (1) 1108 /* @brief Peripheral type. */ 1109 #define FSL_FEATURE_LPUART_IS_SCI (1) 1110 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1111 #define FSL_FEATURE_LPUART_FIFO_SIZEn(x) (0) 1112 /* @brief Supports two match addresses to filter incoming frames. */ 1113 #define FSL_FEATURE_LPUART_HAS_ADDRESS_MATCHING (1) 1114 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1115 #define FSL_FEATURE_LPUART_HAS_DMA_ENABLE (1) 1116 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1117 #define FSL_FEATURE_LPUART_HAS_DMA_SELECT (0) 1118 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1119 #define FSL_FEATURE_LPUART_HAS_BIT_ORDER_SELECT (1) 1120 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1121 #define FSL_FEATURE_LPUART_HAS_SMART_CARD_SUPPORT (0) 1122 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1123 #define FSL_FEATURE_LPUART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1124 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1125 #define FSL_FEATURE_LPUART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1126 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1127 #define FSL_FEATURE_LPUART_HAS_32BIT_REGISTERS (1) 1128 /* @brief Lin break detect available (has bit BAUD[LBKDIE]). */ 1129 #define FSL_FEATURE_LPUART_HAS_LIN_BREAK_DETECT (1) 1130 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1131 #define FSL_FEATURE_LPUART_HAS_WAIT_MODE_OPERATION (0) 1132 /* @brief Has separate DMA RX and TX requests. */ 1133 #define FSL_FEATURE_LPUART_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1134 /* @brief Has separate RX and TX interrupts. */ 1135 #define FSL_FEATURE_LPUART_HAS_SEPARATE_RX_TX_IRQ (0) 1136 /* @brief Has LPAURT_PARAM. */ 1137 #define FSL_FEATURE_LPUART_HAS_PARAM (0) 1138 /* @brief Has LPUART_VERID. */ 1139 #define FSL_FEATURE_LPUART_HAS_VERID (0) 1140 /* @brief Has LPUART_GLOBAL. */ 1141 #define FSL_FEATURE_LPUART_HAS_GLOBAL (0) 1142 /* @brief Has LPUART_PINCFG. */ 1143 #define FSL_FEATURE_LPUART_HAS_PINCFG (0) 1144 1145 /* MCG module features */ 1146 1147 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1148 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1149 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1150 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (7) 1151 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1152 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (16) 1153 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1154 #define FSL_FEATURE_MCG_PLL_REF_MIN (8000000) 1155 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1156 #define FSL_FEATURE_MCG_PLL_REF_MAX (16000000) 1157 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1158 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (1) 1159 /* @brief FRDIV supports 1280. */ 1160 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1161 /* @brief FRDIV supports 1536. */ 1162 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1163 /* @brief MCGFFCLK divider. */ 1164 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1165 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1166 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1167 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1168 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 1169 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1170 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1171 /* @brief Has 48MHz internal oscillator. */ 1172 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 1173 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1174 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1175 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1176 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1177 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1178 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1179 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1180 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1181 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1182 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1183 /* @brief TBD */ 1184 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1185 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1186 #define FSL_FEATURE_MCG_HAS_PLL (1) 1187 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1188 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1189 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1190 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1191 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1192 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1193 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1194 #define FSL_FEATURE_MCG_HAS_FLL (1) 1195 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1196 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (1) 1197 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1198 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1199 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1200 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1201 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1202 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (1) 1203 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1204 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1205 /* @brief Has external clock monitor (register bit C6[CME]). */ 1206 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1207 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1208 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1209 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1210 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1211 /* @brief Has PEI mode or PBI mode. */ 1212 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1213 /* @brief Reset clock mode is BLPI. */ 1214 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1215 1216 /* interrupt module features */ 1217 1218 /* @brief Lowest interrupt request number. */ 1219 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1220 /* @brief Highest interrupt request number. */ 1221 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (99) 1222 1223 /* OSC module features */ 1224 1225 /* @brief Has OSC1 external oscillator. */ 1226 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1227 /* @brief Has OSC0 external oscillator. */ 1228 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1229 /* @brief Has OSC external oscillator (without index). */ 1230 #define FSL_FEATURE_OSC_HAS_OSC (1) 1231 /* @brief Number of OSC external oscillators. */ 1232 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1233 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1234 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (1) 1235 1236 /* PDB module features */ 1237 1238 /* @brief Has DAC support. */ 1239 #define FSL_FEATURE_PDB_HAS_DAC (1) 1240 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1241 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1242 /* @brief PDB channel number). */ 1243 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1244 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1245 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1246 /* @brief DAC interval trigger number). */ 1247 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (2) 1248 /* @brief Pulse out number). */ 1249 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (4) 1250 1251 /* PIT module features */ 1252 1253 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1254 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1255 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1256 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (1) 1257 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1258 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1259 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1260 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1261 /* @brief Has timer enable control. */ 1262 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1263 1264 /* PMC module features */ 1265 1266 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1267 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1268 /* @brief Has Bandgap Buffer Enable. */ 1269 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1270 /* @brief Has Bandgap Buffer Drive Select. */ 1271 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1272 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1273 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1274 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1275 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1276 /* @brief Has LPO. */ 1277 #define FSL_FEATURE_PMC_HAS_LPO (0) 1278 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1279 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1280 /* @brief Has acknowledge isolation support. */ 1281 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1282 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1283 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1284 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1285 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1286 /* @brief Has PMC_HVDSC1. */ 1287 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1288 /* @brief Has PMC_PARAM. */ 1289 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1290 /* @brief Has PMC_VERID. */ 1291 #define FSL_FEATURE_PMC_HAS_VERID (0) 1292 1293 /* PORT module features */ 1294 1295 /* @brief Has control lock (register bit PCR[LK]). */ 1296 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1297 /* @brief Has open drain control (register bit PCR[ODE]). */ 1298 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1299 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1300 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1301 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1302 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1303 /* @brief Has pull resistor selection available. */ 1304 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1305 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1306 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1307 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1308 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1309 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1310 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1311 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1312 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1313 /* @brief Has separate drive strength register (HDRVE). */ 1314 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1315 /* @brief Has glitch filter (register IOFLT). */ 1316 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1317 /* @brief Defines width of PCR[MUX] field. */ 1318 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1319 /* @brief Has dedicated interrupt vector. */ 1320 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1321 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1322 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1323 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1324 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1325 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1326 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1327 1328 /* RCM module features */ 1329 1330 /* @brief Has Loss-of-Lock Reset support. */ 1331 #define FSL_FEATURE_RCM_HAS_LOL (1) 1332 /* @brief Has Loss-of-Clock Reset support. */ 1333 #define FSL_FEATURE_RCM_HAS_LOC (1) 1334 /* @brief Has JTAG generated Reset support. */ 1335 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1336 /* @brief Has EzPort generated Reset support. */ 1337 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 1338 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1339 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 1340 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1341 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1342 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1343 #define FSL_FEATURE_RCM_HAS_SSRS (1) 1344 /* @brief Has Version ID Register (RCM_VERID). */ 1345 #define FSL_FEATURE_RCM_HAS_VERID (0) 1346 /* @brief Has Parameter Register (RCM_PARAM). */ 1347 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1348 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1349 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1350 /* @brief Width of registers of the RCM. */ 1351 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1352 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1353 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1354 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1355 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1356 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1357 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1358 1359 /* RTC module features */ 1360 1361 /* @brief Has wakeup pin. */ 1362 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1363 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1364 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1365 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1366 #define FSL_FEATURE_RTC_HAS_MONOTONIC (1) 1367 /* @brief Has read/write access control (registers WAR and RAR). */ 1368 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1369 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1370 #define FSL_FEATURE_RTC_HAS_SECURITY (1) 1371 /* @brief Has RTC_CLKIN available. */ 1372 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1373 /* @brief Has prescaler adjust for LPO. */ 1374 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1375 /* @brief Has Clock Pin Enable field. */ 1376 #define FSL_FEATURE_RTC_HAS_CPE (0) 1377 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1378 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1379 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1380 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1381 /* @brief Has Tamper Interrupt Register (register TIR). */ 1382 #define FSL_FEATURE_RTC_HAS_TIR (0) 1383 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1384 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1385 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1386 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1387 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1388 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1389 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1390 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1391 /* @brief Has Tamper Detect Register (register TDR). */ 1392 #define FSL_FEATURE_RTC_HAS_TDR (0) 1393 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1394 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1395 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1396 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1397 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1398 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1399 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1400 #define FSL_FEATURE_RTC_HAS_TTSR (1) 1401 /* @brief Has Pin Configuration Register (register PCR). */ 1402 #define FSL_FEATURE_RTC_HAS_PCR (0) 1403 1404 /* SDHC module features */ 1405 1406 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ 1407 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (0) 1408 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ 1409 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) 1410 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ 1411 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) 1412 1413 /* SIM module features */ 1414 1415 /* @brief Has USB FS divider. */ 1416 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1417 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1418 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1419 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1420 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1421 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1422 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1423 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1424 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1425 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1426 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1427 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1428 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1429 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1430 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1431 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1432 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (1) 1433 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1434 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (0) 1435 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1436 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1437 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1438 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1439 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1440 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1441 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1442 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1443 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1444 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (1) 1445 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1446 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1447 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1448 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1449 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1450 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1451 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1452 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1453 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1454 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1455 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1456 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1457 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1458 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1459 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1460 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (1) 1461 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1462 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (1) 1463 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1464 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1465 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1466 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1467 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1468 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1469 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1470 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1471 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1472 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1473 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1474 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1475 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1476 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1477 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1478 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1479 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1480 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1481 /* @brief Has FTM module(s) configuration. */ 1482 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1483 /* @brief Number of FTM modules. */ 1484 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1485 /* @brief Number of FTM triggers with selectable source. */ 1486 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1487 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1488 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1489 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1490 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1491 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1492 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1493 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1494 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1495 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1496 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1497 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1498 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (1) 1499 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1500 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (4) 1501 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1502 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1503 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1504 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1505 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1506 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1507 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1508 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (1) 1509 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1510 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (1) 1511 /* @brief Has TPM module(s) configuration. */ 1512 #define FSL_FEATURE_SIM_OPT_HAS_TPM (1) 1513 /* @brief The highest TPM module index. */ 1514 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (2) 1515 /* @brief Has TPM module with index 0. */ 1516 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1517 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1518 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1519 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1520 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1521 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1522 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (1) 1523 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1524 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1525 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1526 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (1) 1527 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1528 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1529 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1530 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1531 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1532 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1533 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1534 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1535 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1536 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1537 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1538 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1539 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1540 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) 1541 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1542 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1543 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1544 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) 1545 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1546 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) 1547 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1548 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1549 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1550 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1551 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1552 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1553 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1554 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (1) 1555 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1556 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1557 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1558 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1559 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1560 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1561 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1562 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1563 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1564 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (1) 1565 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1566 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1567 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1568 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1569 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1570 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1571 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1572 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) 1573 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1574 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1575 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1576 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1577 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1578 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1579 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1580 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1581 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1582 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1583 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1584 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1585 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1586 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1587 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1588 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1589 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1590 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1591 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1592 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1593 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1594 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1595 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1596 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1597 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1598 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1599 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1600 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) 1601 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1602 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1603 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1604 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1605 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1606 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (1) 1607 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1608 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1609 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1610 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (1) 1611 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1612 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1613 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1614 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1615 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1616 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1617 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1618 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1619 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1620 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1621 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1622 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1623 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1624 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1625 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1626 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1627 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1628 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1629 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1630 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1631 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1632 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) 1633 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1634 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) 1635 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1636 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) 1637 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1638 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1639 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1640 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1641 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1642 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1643 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1644 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1645 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1646 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) 1647 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1648 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (1) 1649 /* @brief Has miscellanious control register (register MCR). */ 1650 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1651 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1652 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1653 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1654 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1655 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1656 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1657 /* @brief Has UIDH registers. */ 1658 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1659 /* @brief Has UIDM registers. */ 1660 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1661 1662 /* SMC module features */ 1663 1664 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1665 #define FSL_FEATURE_SMC_HAS_PSTOPO (1) 1666 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1667 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1668 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1669 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1670 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1671 #define FSL_FEATURE_SMC_HAS_LPWUI (0) 1672 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1673 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (1) 1674 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1675 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (0) 1676 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1677 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1678 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1679 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (1) 1680 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1681 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (1) 1682 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1683 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1684 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1685 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1686 /* @brief Has stop submode. */ 1687 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1688 /* @brief Has stop submode 0(VLLS0). */ 1689 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1690 /* @brief Has stop submode 1(VLLS1). */ 1691 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1692 /* @brief Has stop submode 2(VLLS2). */ 1693 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1694 /* @brief Has SMC_PARAM. */ 1695 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1696 /* @brief Has SMC_VERID. */ 1697 #define FSL_FEATURE_SMC_HAS_VERID (0) 1698 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1699 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1700 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1701 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1702 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1703 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1704 /* @brief Width of SMC registers. */ 1705 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1706 1707 /* DSPI module features */ 1708 1709 /* @brief Receive/transmit FIFO size in number of items. */ 1710 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1711 (((x) == SPI0) ? (4) : \ 1712 (((x) == SPI1) ? (1) : \ 1713 (((x) == SPI2) ? (1) : (-1)))) 1714 /* @brief Maximum transfer data width in bits. */ 1715 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1716 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1717 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1718 /* @brief Number of chip select pins. */ 1719 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1720 /* @brief Number of CTAR registers. */ 1721 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1722 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1723 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1724 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1725 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1726 /* @brief Has 16-bit data transfer support. */ 1727 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1728 /* @brief Has separate DMA RX and TX requests. */ 1729 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) (1) 1730 1731 /* SYSMPU module features */ 1732 1733 /* @brief Specifies number of descriptors available. */ 1734 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 1735 /* @brief Has process identifier support. */ 1736 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1737 /* @brief Total number of MPU slave. */ 1738 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) 1739 /* @brief Total number of MPU master. */ 1740 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (7) 1741 1742 /* SysTick module features */ 1743 1744 /* @brief Systick has external reference clock. */ 1745 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1746 /* @brief Systick external reference clock is core clock divided by this value. */ 1747 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1748 1749 /* TPM module features */ 1750 1751 /* @brief Bus clock is the source clock for the module. */ 1752 #define FSL_FEATURE_TPM_BUS_CLOCK (0) 1753 /* @brief Number of channels. */ 1754 #define FSL_FEATURE_TPM_CHANNEL_COUNTn(x) (2) 1755 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 1756 #define FSL_FEATURE_TPM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 1757 /* @brief Has TPM_PARAM. */ 1758 #define FSL_FEATURE_TPM_HAS_PARAM (0) 1759 /* @brief Has TPM_VERID. */ 1760 #define FSL_FEATURE_TPM_HAS_VERID (0) 1761 /* @brief Has TPM_GLOBAL. */ 1762 #define FSL_FEATURE_TPM_HAS_GLOBAL (0) 1763 /* @brief Has TPM_TRIG. */ 1764 #define FSL_FEATURE_TPM_HAS_TRIG (0) 1765 /* @brief Whether TRIG register has effect. */ 1766 #define FSL_FEATURE_TPM_TRIG_HAS_EFFECTn(x) (0) 1767 /* @brief Has counter pause on trigger. */ 1768 #define FSL_FEATURE_TPM_HAS_PAUSE_COUNTER_ON_TRIGGER (1) 1769 /* @brief Has external trigger selection. */ 1770 #define FSL_FEATURE_TPM_HAS_EXTERNAL_TRIGGER_SELECTION (1) 1771 /* @brief Has TPM_COMBINE register. */ 1772 #define FSL_FEATURE_TPM_HAS_COMBINE (1) 1773 /* @brief Whether COMBINE register has effect. */ 1774 #define FSL_FEATURE_TPM_COMBINE_HAS_EFFECTn(x) (1) 1775 /* @brief Has TPM_POL. */ 1776 #define FSL_FEATURE_TPM_HAS_POL (1) 1777 /* @brief Whether POL register has effect. */ 1778 #define FSL_FEATURE_TPM_POL_HAS_EFFECTn(x) (1) 1779 /* @brief Has TPM_FILTER register. */ 1780 #define FSL_FEATURE_TPM_HAS_FILTER (1) 1781 /* @brief Whether FILTER register has effect. */ 1782 #define FSL_FEATURE_TPM_FILTER_HAS_EFFECTn(x) (1) 1783 /* @brief Has TPM_QDCTRL register. */ 1784 #define FSL_FEATURE_TPM_HAS_QDCTRL (1) 1785 /* @brief Whether QDCTRL register has effect. */ 1786 #define FSL_FEATURE_TPM_QDCTRL_HAS_EFFECTn(x) (1) 1787 /* @brief Is affected by errata with ID 050050 (Incorrect duty output when EPWM mode is set to PS=0 during write 1 to CnV register). */ 1788 #define FSL_FEATURE_TPM_HAS_ERRATA_050050 (0) 1789 /* @brief Whether 32 bits counter has effect. */ 1790 #define FSL_FEATURE_TPM_HAS_32BIT_COUNTERn(x) (0) 1791 1792 /* TSI module features */ 1793 1794 /* @brief TSI module version. */ 1795 #define FSL_FEATURE_TSI_VERSION (4) 1796 /* @brief Has end-of-scan DMA transfer request enable (register bit GENCS[EOSDMEO]). */ 1797 #define FSL_FEATURE_TSI_HAS_END_OF_SCAN_DMA_ENABLE (1) 1798 /* @brief Number of TSI channels. */ 1799 #define FSL_FEATURE_TSI_CHANNEL_COUNT (16) 1800 1801 /* UART module features */ 1802 1803 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1804 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1805 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1806 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1807 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1808 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1809 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1810 #define FSL_FEATURE_UART_HAS_FIFO (1) 1811 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1812 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1813 /* @brief Infrared (modulation) is supported. */ 1814 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1815 /* @brief 2 bits long stop bit is available. */ 1816 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1817 /* @brief If 10-bit mode is supported. */ 1818 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1819 /* @brief Baud rate fine adjustment is available. */ 1820 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1821 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1822 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1823 /* @brief Baud rate oversampling is available. */ 1824 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1825 /* @brief Baud rate oversampling is available. */ 1826 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1827 /* @brief Peripheral type. */ 1828 #define FSL_FEATURE_UART_IS_SCI (0) 1829 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1830 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1831 (((x) == UART0) ? (8) : \ 1832 (((x) == UART1) ? (8) : \ 1833 (((x) == UART2) ? (1) : \ 1834 (((x) == UART3) ? (1) : \ 1835 (((x) == UART4) ? (1) : (-1)))))) 1836 /* @brief Supports two match addresses to filter incoming frames. */ 1837 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1838 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1839 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1840 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1841 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1842 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1843 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1844 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1845 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1846 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1847 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (1) 1848 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1849 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1850 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1851 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1852 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1853 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1854 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1855 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1856 /* @brief Has separate DMA RX and TX requests. */ 1857 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1858 (((x) == UART0) ? (1) : \ 1859 (((x) == UART1) ? (1) : \ 1860 (((x) == UART2) ? (1) : \ 1861 (((x) == UART3) ? (1) : \ 1862 (((x) == UART4) ? (0) : (-1)))))) 1863 1864 /* USB module features */ 1865 1866 /* @brief KHCI module instance count */ 1867 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1868 /* @brief HOST mode enabled */ 1869 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 1870 /* @brief OTG mode enabled */ 1871 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 1872 /* @brief Size of the USB dedicated RAM */ 1873 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 1874 /* @brief Has KEEP_ALIVE_CTRL register */ 1875 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1876 /* @brief Has the Dynamic SOF threshold compare support */ 1877 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 1878 /* @brief Has the VBUS detect support */ 1879 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 1880 /* @brief Has the IRC48M module clock support */ 1881 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) 1882 /* @brief Number of endpoints supported */ 1883 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1884 /* @brief Has STALL_IL/OL_DIS registers */ 1885 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 1886 /* @brief Has STALL_IH/OH_DIS registers */ 1887 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 1888 1889 /* USBHS module features */ 1890 1891 /* @brief EHCI module instance count */ 1892 #define FSL_FEATURE_USBHS_EHCI_COUNT (1) 1893 /* @brief Number of endpoints supported */ 1894 #define FSL_FEATURE_USBHS_ENDPT_COUNT (8) 1895 1896 /* VREF module features */ 1897 1898 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1899 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1900 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1901 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1902 /* @brief If high/low buffer mode supported */ 1903 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1904 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1905 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1906 /* @brief Has VREF_TRM4. */ 1907 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1908 1909 /* WDOG module features */ 1910 1911 /* @brief Watchdog is available. */ 1912 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1913 /* @brief Has Wait mode support. */ 1914 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1915 1916 #endif /* _MK65F18_FEATURES_H_ */ 1917 1918
