1 /* 2 ** ################################################################### 3 ** Version: rev. 2.15, 2016-03-21 4 ** Build: b210427 5 ** 6 ** Abstract: 7 ** Chip specific module features. 8 ** 9 ** Copyright 2016 Freescale Semiconductor, Inc. 10 ** Copyright 2016-2021 NXP 11 ** All rights reserved. 12 ** 13 ** SPDX-License-Identifier: BSD-3-Clause 14 ** 15 ** http: www.nxp.com 16 ** mail: support@nxp.com 17 ** 18 ** Revisions: 19 ** - rev. 1.0 (2013-08-12) 20 ** Initial version. 21 ** - rev. 2.0 (2013-10-29) 22 ** Register accessor macros added to the memory map. 23 ** Symbols for Processor Expert memory map compatibility added to the memory map. 24 ** Startup file for gcc has been updated according to CMSIS 3.2. 25 ** System initialization updated. 26 ** MCG - registers updated. 27 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed. 28 ** - rev. 2.1 (2013-10-30) 29 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled. 30 ** - rev. 2.2 (2013-12-09) 31 ** DMA - EARS register removed. 32 ** AIPS0, AIPS1 - MPRA register updated. 33 ** - rev. 2.3 (2014-01-24) 34 ** Update according to reference manual rev. 2 35 ** ENET, MCG, MCM, SIM, USB - registers updated 36 ** - rev. 2.4 (2014-01-30) 37 ** Added single maximum value generation and a constrain to varying feature values that only numbers can have maximum. 38 ** - rev. 2.5 (2014-02-10) 39 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 40 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 41 ** - rev. 2.6 (2014-02-10) 42 ** The declaration of clock configurations has been moved to separate header file system_MK64F12.h 43 ** Update of SystemInit() and SystemCoreClockUpdate() functions. 44 ** Module access macro module_BASES replaced by module_BASE_PTRS. 45 ** - rev. 2.7 (2014-08-28) 46 ** Update of system files - default clock configuration changed. 47 ** Update of startup files - possibility to override DefaultISR added. 48 ** - rev. 2.8 (2014-10-14) 49 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM. 50 ** - rev. 2.9 (2015-01-21) 51 ** Added FSL_FEATURE_SOC_peripheral_COUNT with number of peripheral instances 52 ** - rev. 2.10 (2015-02-19) 53 ** Renamed interrupt vector LLW to LLWU. 54 ** - rev. 2.11 (2015-05-19) 55 ** FSL_FEATURE_SOC_CAU_COUNT remamed to FSL_FEATURE_SOC_MMCAU_COUNT. 56 ** Added FSL_FEATURE_SOC_peripheral_COUNT for TRNG and HSADC. 57 ** Added features for PDB and PORT. 58 ** - rev. 2.12 (2015-05-25) 59 ** Added FSL_FEATURE_FLASH_PFLASH_START_ADDRESS 60 ** - rev. 2.13 (2015-05-27) 61 ** Several USB features added. 62 ** - rev. 2.14 (2015-06-08) 63 ** FTM features BUS_CLOCK and FAST_CLOCK removed. 64 ** - rev. 2.15 (2016-03-21) 65 ** Added MK64FN1M0CAJ12 part. 66 ** 67 ** ################################################################### 68 */ 69 70 #ifndef _MK64F12_FEATURES_H_ 71 #define _MK64F12_FEATURES_H_ 72 73 /* SOC module features */ 74 75 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ 76 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) 77 /* @brief ADC16 availability on the SoC. */ 78 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 79 /* @brief AIPS availability on the SoC. */ 80 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 81 /* @brief AXBS availability on the SoC. */ 82 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 83 /* @brief FLEXCAN availability on the SoC. */ 84 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) 85 /* @brief MMCAU availability on the SoC. */ 86 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 87 /* @brief CMP availability on the SoC. */ 88 #define FSL_FEATURE_SOC_CMP_COUNT (3) 89 /* @brief CMT availability on the SoC. */ 90 #define FSL_FEATURE_SOC_CMT_COUNT (1) 91 /* @brief CRC availability on the SoC. */ 92 #define FSL_FEATURE_SOC_CRC_COUNT (1) 93 /* @brief DAC availability on the SoC. */ 94 #define FSL_FEATURE_SOC_DAC_COUNT (2) 95 /* @brief EDMA availability on the SoC. */ 96 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 97 /* @brief DMAMUX availability on the SoC. */ 98 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 99 /* @brief DSPI availability on the SoC. */ 100 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 101 /* @brief ENET availability on the SoC. */ 102 #define FSL_FEATURE_SOC_ENET_COUNT (1) 103 /* @brief EWM availability on the SoC. */ 104 #define FSL_FEATURE_SOC_EWM_COUNT (1) 105 /* @brief FB availability on the SoC. */ 106 #define FSL_FEATURE_SOC_FB_COUNT (1) 107 /* @brief FMC availability on the SoC. */ 108 #define FSL_FEATURE_SOC_FMC_COUNT (1) 109 /* @brief FTFE availability on the SoC. */ 110 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 111 /* @brief FTM availability on the SoC. */ 112 #define FSL_FEATURE_SOC_FTM_COUNT (4) 113 /* @brief GPIO availability on the SoC. */ 114 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 115 /* @brief I2C availability on the SoC. */ 116 #define FSL_FEATURE_SOC_I2C_COUNT (3) 117 /* @brief I2S availability on the SoC. */ 118 #define FSL_FEATURE_SOC_I2S_COUNT (1) 119 /* @brief LLWU availability on the SoC. */ 120 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 121 /* @brief LPTMR availability on the SoC. */ 122 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 123 /* @brief MCG availability on the SoC. */ 124 #define FSL_FEATURE_SOC_MCG_COUNT (1) 125 /* @brief MCM availability on the SoC. */ 126 #define FSL_FEATURE_SOC_MCM_COUNT (1) 127 /* @brief SYSMPU availability on the SoC. */ 128 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 129 /* @brief OSC availability on the SoC. */ 130 #define FSL_FEATURE_SOC_OSC_COUNT (1) 131 /* @brief PDB availability on the SoC. */ 132 #define FSL_FEATURE_SOC_PDB_COUNT (1) 133 /* @brief PIT availability on the SoC. */ 134 #define FSL_FEATURE_SOC_PIT_COUNT (1) 135 /* @brief PMC availability on the SoC. */ 136 #define FSL_FEATURE_SOC_PMC_COUNT (1) 137 /* @brief PORT availability on the SoC. */ 138 #define FSL_FEATURE_SOC_PORT_COUNT (5) 139 /* @brief RCM availability on the SoC. */ 140 #define FSL_FEATURE_SOC_RCM_COUNT (1) 141 /* @brief RFSYS availability on the SoC. */ 142 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 143 /* @brief RFVBAT availability on the SoC. */ 144 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 145 /* @brief RNG availability on the SoC. */ 146 #define FSL_FEATURE_SOC_RNG_COUNT (1) 147 /* @brief RTC availability on the SoC. */ 148 #define FSL_FEATURE_SOC_RTC_COUNT (1) 149 /* @brief SDHC availability on the SoC. */ 150 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 151 /* @brief SIM availability on the SoC. */ 152 #define FSL_FEATURE_SOC_SIM_COUNT (1) 153 /* @brief SMC availability on the SoC. */ 154 #define FSL_FEATURE_SOC_SMC_COUNT (1) 155 /* @brief UART availability on the SoC. */ 156 #define FSL_FEATURE_SOC_UART_COUNT (6) 157 /* @brief USB availability on the SoC. */ 158 #define FSL_FEATURE_SOC_USB_COUNT (1) 159 /* @brief USBDCD availability on the SoC. */ 160 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 161 /* @brief VREF availability on the SoC. */ 162 #define FSL_FEATURE_SOC_VREF_COUNT (1) 163 /* @brief WDOG availability on the SoC. */ 164 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 165 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) 166 /* @brief ADC16 availability on the SoC. */ 167 #define FSL_FEATURE_SOC_ADC16_COUNT (2) 168 /* @brief AIPS availability on the SoC. */ 169 #define FSL_FEATURE_SOC_AIPS_COUNT (2) 170 /* @brief AXBS availability on the SoC. */ 171 #define FSL_FEATURE_SOC_AXBS_COUNT (1) 172 /* @brief FLEXCAN availability on the SoC. */ 173 #define FSL_FEATURE_SOC_FLEXCAN_COUNT (1) 174 /* @brief MMCAU availability on the SoC. */ 175 #define FSL_FEATURE_SOC_MMCAU_COUNT (1) 176 /* @brief CMP availability on the SoC. */ 177 #define FSL_FEATURE_SOC_CMP_COUNT (3) 178 /* @brief CMT availability on the SoC. */ 179 #define FSL_FEATURE_SOC_CMT_COUNT (1) 180 /* @brief CRC availability on the SoC. */ 181 #define FSL_FEATURE_SOC_CRC_COUNT (1) 182 /* @brief DAC availability on the SoC. */ 183 #define FSL_FEATURE_SOC_DAC_COUNT (1) 184 /* @brief EDMA availability on the SoC. */ 185 #define FSL_FEATURE_SOC_EDMA_COUNT (1) 186 /* @brief DMAMUX availability on the SoC. */ 187 #define FSL_FEATURE_SOC_DMAMUX_COUNT (1) 188 /* @brief DSPI availability on the SoC. */ 189 #define FSL_FEATURE_SOC_DSPI_COUNT (3) 190 /* @brief ENET availability on the SoC. */ 191 #define FSL_FEATURE_SOC_ENET_COUNT (1) 192 /* @brief EWM availability on the SoC. */ 193 #define FSL_FEATURE_SOC_EWM_COUNT (1) 194 /* @brief FB availability on the SoC. */ 195 #define FSL_FEATURE_SOC_FB_COUNT (1) 196 /* @brief FMC availability on the SoC. */ 197 #define FSL_FEATURE_SOC_FMC_COUNT (1) 198 /* @brief FTFE availability on the SoC. */ 199 #define FSL_FEATURE_SOC_FTFE_COUNT (1) 200 /* @brief FTM availability on the SoC. */ 201 #define FSL_FEATURE_SOC_FTM_COUNT (4) 202 /* @brief GPIO availability on the SoC. */ 203 #define FSL_FEATURE_SOC_GPIO_COUNT (5) 204 /* @brief I2C availability on the SoC. */ 205 #define FSL_FEATURE_SOC_I2C_COUNT (3) 206 /* @brief I2S availability on the SoC. */ 207 #define FSL_FEATURE_SOC_I2S_COUNT (1) 208 /* @brief LLWU availability on the SoC. */ 209 #define FSL_FEATURE_SOC_LLWU_COUNT (1) 210 /* @brief LPTMR availability on the SoC. */ 211 #define FSL_FEATURE_SOC_LPTMR_COUNT (1) 212 /* @brief MCG availability on the SoC. */ 213 #define FSL_FEATURE_SOC_MCG_COUNT (1) 214 /* @brief MCM availability on the SoC. */ 215 #define FSL_FEATURE_SOC_MCM_COUNT (1) 216 /* @brief SYSMPU availability on the SoC. */ 217 #define FSL_FEATURE_SOC_SYSMPU_COUNT (1) 218 /* @brief OSC availability on the SoC. */ 219 #define FSL_FEATURE_SOC_OSC_COUNT (1) 220 /* @brief PDB availability on the SoC. */ 221 #define FSL_FEATURE_SOC_PDB_COUNT (1) 222 /* @brief PIT availability on the SoC. */ 223 #define FSL_FEATURE_SOC_PIT_COUNT (1) 224 /* @brief PMC availability on the SoC. */ 225 #define FSL_FEATURE_SOC_PMC_COUNT (1) 226 /* @brief PORT availability on the SoC. */ 227 #define FSL_FEATURE_SOC_PORT_COUNT (5) 228 /* @brief RCM availability on the SoC. */ 229 #define FSL_FEATURE_SOC_RCM_COUNT (1) 230 /* @brief RFSYS availability on the SoC. */ 231 #define FSL_FEATURE_SOC_RFSYS_COUNT (1) 232 /* @brief RFVBAT availability on the SoC. */ 233 #define FSL_FEATURE_SOC_RFVBAT_COUNT (1) 234 /* @brief RNG availability on the SoC. */ 235 #define FSL_FEATURE_SOC_RNG_COUNT (1) 236 /* @brief RTC availability on the SoC. */ 237 #define FSL_FEATURE_SOC_RTC_COUNT (1) 238 /* @brief SDHC availability on the SoC. */ 239 #define FSL_FEATURE_SOC_SDHC_COUNT (1) 240 /* @brief SIM availability on the SoC. */ 241 #define FSL_FEATURE_SOC_SIM_COUNT (1) 242 /* @brief SMC availability on the SoC. */ 243 #define FSL_FEATURE_SOC_SMC_COUNT (1) 244 /* @brief UART availability on the SoC. */ 245 #define FSL_FEATURE_SOC_UART_COUNT (5) 246 /* @brief USB availability on the SoC. */ 247 #define FSL_FEATURE_SOC_USB_COUNT (1) 248 /* @brief USBDCD availability on the SoC. */ 249 #define FSL_FEATURE_SOC_USBDCD_COUNT (1) 250 /* @brief VREF availability on the SoC. */ 251 #define FSL_FEATURE_SOC_VREF_COUNT (1) 252 /* @brief WDOG availability on the SoC. */ 253 #define FSL_FEATURE_SOC_WDOG_COUNT (1) 254 #endif 255 256 /* ADC16 module features */ 257 258 /* @brief Has Programmable Gain Amplifier (PGA) in ADC (register PGA). */ 259 #define FSL_FEATURE_ADC16_HAS_PGA (0) 260 /* @brief Has PGA chopping control in ADC (bit PGA[PGACHPb] or PGA[PGACHP]). */ 261 #define FSL_FEATURE_ADC16_HAS_PGA_CHOPPING (0) 262 /* @brief Has PGA offset measurement mode in ADC (bit PGA[PGAOFSM]). */ 263 #define FSL_FEATURE_ADC16_HAS_PGA_OFFSET_MEASUREMENT (0) 264 /* @brief Has DMA support (bit SC2[DMAEN] or SC4[DMAEN]). */ 265 #define FSL_FEATURE_ADC16_HAS_DMA (1) 266 /* @brief Has differential mode (bitfield SC1x[DIFF]). */ 267 #define FSL_FEATURE_ADC16_HAS_DIFF_MODE (1) 268 /* @brief Has FIFO (bit SC4[AFDEP]). */ 269 #define FSL_FEATURE_ADC16_HAS_FIFO (0) 270 /* @brief FIFO size if available (bitfield SC4[AFDEP]). */ 271 #define FSL_FEATURE_ADC16_FIFO_SIZE (0) 272 /* @brief Has channel set a/b multiplexor (bitfield CFG2[MUXSEL]). */ 273 #define FSL_FEATURE_ADC16_HAS_MUX_SELECT (1) 274 /* @brief Has HW trigger masking (bitfield SC5[HTRGMASKE]. */ 275 #define FSL_FEATURE_ADC16_HAS_HW_TRIGGER_MASK (0) 276 /* @brief Has calibration feature (bit SC3[CAL] and registers CLPx, CLMx). */ 277 #define FSL_FEATURE_ADC16_HAS_CALIBRATION (1) 278 /* @brief Has HW averaging (bit SC3[AVGE]). */ 279 #define FSL_FEATURE_ADC16_HAS_HW_AVERAGE (1) 280 /* @brief Has offset correction (register OFS). */ 281 #define FSL_FEATURE_ADC16_HAS_OFFSET_CORRECTION (1) 282 /* @brief Maximum ADC resolution. */ 283 #define FSL_FEATURE_ADC16_MAX_RESOLUTION (16) 284 /* @brief Number of SC1x and Rx register pairs (conversion control and result registers). */ 285 #define FSL_FEATURE_ADC16_CONVERSION_CONTROL_COUNT (2) 286 287 /* FLEXCAN module features */ 288 289 /* @brief Message buffer size */ 290 #define FSL_FEATURE_FLEXCAN_HAS_MESSAGE_BUFFER_MAX_NUMBERn(x) (16) 291 /* @brief Has doze mode support (register bit field MCR[DOZE]). */ 292 #define FSL_FEATURE_FLEXCAN_HAS_DOZE_MODE_SUPPORT (0) 293 /* @brief Insatnce has doze mode support (register bit field MCR[DOZE]). */ 294 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_DOZE_MODE_SUPPORTn(x) (0) 295 /* @brief Has a glitch filter on the receive pin (register bit field MCR[WAKSRC]). */ 296 #define FSL_FEATURE_FLEXCAN_HAS_GLITCH_FILTER (1) 297 /* @brief Has extended interrupt mask and flag register (register IMASK2, IFLAG2). */ 298 #define FSL_FEATURE_FLEXCAN_HAS_EXTENDED_FLAG_REGISTER (0) 299 /* @brief Instance has extended bit timing register (register CBT). */ 300 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_EXTENDED_TIMING_REGISTERn(x) (0) 301 /* @brief Has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 302 #define FSL_FEATURE_FLEXCAN_HAS_RX_FIFO_DMA (0) 303 /* @brief Instance has a receive FIFO DMA feature (register bit field MCR[DMA]). */ 304 #define FSL_FEATURE_FLEXCAN_INSTANCE_HAS_RX_FIFO_DMAn(x) (0) 305 /* @brief Has separate message buffer 0 interrupt flag (register bit field IFLAG1[BUF0I]). */ 306 #define FSL_FEATURE_FLEXCAN_HAS_SEPARATE_BUFFER_0_FLAG (1) 307 /* @brief Has bitfield name BUF31TO0M. */ 308 #define FSL_FEATURE_FLEXCAN_HAS_BUF31TO0M (0) 309 /* @brief Number of interrupt vectors. */ 310 #define FSL_FEATURE_FLEXCAN_INTERRUPT_COUNT (6) 311 /* @brief Is affected by errata with ID 5641 (Module does not transmit a message that is enabled to be transmitted at a specific moment during the arbitration process). */ 312 #define FSL_FEATURE_FLEXCAN_HAS_ERRATA_5641 (0) 313 314 /* CMP module features */ 315 316 /* @brief Has Trigger mode in CMP (register bit field CR1[TRIGM]). */ 317 #define FSL_FEATURE_CMP_HAS_TRIGGER_MODE (0) 318 /* @brief Has Window mode in CMP (register bit field CR1[WE]). */ 319 #define FSL_FEATURE_CMP_HAS_WINDOW_MODE (1) 320 /* @brief Has External sample supported in CMP (register bit field CR1[SE]). */ 321 #define FSL_FEATURE_CMP_HAS_EXTERNAL_SAMPLE_SUPPORT (1) 322 /* @brief Has DMA support in CMP (register bit field SCR[DMAEN]). */ 323 #define FSL_FEATURE_CMP_HAS_DMA (1) 324 /* @brief Has Pass Through mode in CMP (register bit field MUXCR[PSTM]). */ 325 #define FSL_FEATURE_CMP_HAS_PASS_THROUGH_MODE (1) 326 /* @brief Has DAC Test function in CMP (register DACTEST). */ 327 #define FSL_FEATURE_CMP_HAS_DAC_TEST (0) 328 329 /* CRC module features */ 330 331 /* @brief Has data register with name CRC */ 332 #define FSL_FEATURE_CRC_HAS_CRC_REG (0) 333 334 /* DAC module features */ 335 336 /* @brief Define the size of hardware buffer */ 337 #define FSL_FEATURE_DAC_BUFFER_SIZE (16) 338 /* @brief Define whether the buffer supports watermark event detection or not. */ 339 #define FSL_FEATURE_DAC_HAS_WATERMARK_DETECTION (1) 340 /* @brief Define whether the buffer supports watermark selection detection or not. */ 341 #define FSL_FEATURE_DAC_HAS_WATERMARK_SELECTION (1) 342 /* @brief Define whether the buffer supports watermark event 1 word before buffer upper limit. */ 343 #define FSL_FEATURE_DAC_HAS_WATERMARK_1_WORD (1) 344 /* @brief Define whether the buffer supports watermark event 2 words before buffer upper limit. */ 345 #define FSL_FEATURE_DAC_HAS_WATERMARK_2_WORDS (1) 346 /* @brief Define whether the buffer supports watermark event 3 words before buffer upper limit. */ 347 #define FSL_FEATURE_DAC_HAS_WATERMARK_3_WORDS (1) 348 /* @brief Define whether the buffer supports watermark event 4 words before buffer upper limit. */ 349 #define FSL_FEATURE_DAC_HAS_WATERMARK_4_WORDS (1) 350 /* @brief Define whether FIFO buffer mode is available or not. */ 351 #define FSL_FEATURE_DAC_HAS_BUFFER_FIFO_MODE (0) 352 /* @brief Define whether swing buffer mode is available or not.. */ 353 #define FSL_FEATURE_DAC_HAS_BUFFER_SWING_MODE (1) 354 355 /* EDMA module features */ 356 357 /* @brief Number of DMA channels (related to number of registers TCD, DCHPRI, bit fields ERQ[ERQn], EEI[EEIn], INT[INTn], ERR[ERRn], HRS[HRSn] and bit field widths ES[ERRCHN], CEEI[CEEI], SEEI[SEEI], CERQ[CERQ], SERQ[SERQ], CDNE[CDNE], SSRT[SSRT], CERR[CERR], CINT[CINT], TCDn_CITER_ELINKYES[LINKCH], TCDn_CSR[MAJORLINKCH], TCDn_BITER_ELINKYES[LINKCH]). (Valid only for eDMA modules.) */ 358 #define FSL_FEATURE_EDMA_MODULE_CHANNEL (16) 359 /* @brief Total number of DMA channels on all modules. */ 360 #define FSL_FEATURE_EDMA_DMAMUX_CHANNELS (16) 361 /* @brief Number of DMA channel groups (register bit fields CR[ERGA], CR[GRPnPRI], ES[GPE], DCHPRIn[GRPPRI]). (Valid only for eDMA modules.) */ 362 #define FSL_FEATURE_EDMA_CHANNEL_GROUP_COUNT (1) 363 /* @brief Has DMA_Error interrupt vector. */ 364 #define FSL_FEATURE_EDMA_HAS_ERROR_IRQ (1) 365 /* @brief Number of DMA channels with asynchronous request capability (register EARS). (Valid only for eDMA modules.) */ 366 #define FSL_FEATURE_EDMA_ASYNCHRO_REQUEST_CHANNEL_COUNT (0) 367 /* @brief Channel IRQ entry shared offset. */ 368 #define FSL_FEATURE_EDMA_MODULE_CHANNEL_IRQ_ENTRY_SHARED_OFFSET (0) 369 /* @brief If 8 bytes transfer supported. */ 370 #define FSL_FEATURE_EDMA_SUPPORT_8_BYTES_TRANSFER (0) 371 /* @brief If 16 bytes transfer supported. */ 372 #define FSL_FEATURE_EDMA_SUPPORT_16_BYTES_TRANSFER (1) 373 374 /* DMAMUX module features */ 375 376 /* @brief Number of DMA channels (related to number of register CHCFGn). */ 377 #define FSL_FEATURE_DMAMUX_MODULE_CHANNEL (16) 378 /* @brief Total number of DMA channels on all modules. */ 379 #define FSL_FEATURE_DMAMUX_DMAMUX_CHANNELS (16) 380 /* @brief Has the periodic trigger capability for the triggered DMA channel (register bit CHCFG0[TRIG]). */ 381 #define FSL_FEATURE_DMAMUX_HAS_TRIG (1) 382 /* @brief Register CHCFGn width. */ 383 #define FSL_FEATURE_DMAMUX_CHCFG_REGISTER_WIDTH (8) 384 385 /* ENET module features */ 386 387 /* @brief Support Interrupt Coalesce */ 388 #define FSL_FEATURE_ENET_HAS_INTERRUPT_COALESCE (0) 389 /* @brief Queue Size. */ 390 #define FSL_FEATURE_ENET_QUEUE (1) 391 /* @brief Has AVB Support. */ 392 #define FSL_FEATURE_ENET_HAS_AVB (0) 393 /* @brief Has Timer Pulse Width control. */ 394 #define FSL_FEATURE_ENET_HAS_TIMER_PWCONTROL (0) 395 /* @brief Has Extend MDIO Support. */ 396 #define FSL_FEATURE_ENET_HAS_EXTEND_MDIO (0) 397 /* @brief Has Additional 1588 Timer Channel Interrupt. */ 398 #define FSL_FEATURE_ENET_HAS_ADD_1588_TIMER_CHN_INT (1) 399 /* @brief Support Interrupt Coalesce for each instance */ 400 #define FSL_FEATURE_ENET_INSTANCE_HAS_INTERRUPT_COALESCEn(x) (0) 401 /* @brief Queue Size for each instance. */ 402 #define FSL_FEATURE_ENET_INSTANCE_QUEUEn(x) (1) 403 /* @brief Has AVB Support for each instance. */ 404 #define FSL_FEATURE_ENET_INSTANCE_HAS_AVBn(x) (0) 405 /* @brief Has Timer Pulse Width control for each instance. */ 406 #define FSL_FEATURE_ENET_INSTANCE_HAS_TIMER_PWCONTROLn(x) (0) 407 /* @brief Has Extend MDIO Support for each instance. */ 408 #define FSL_FEATURE_ENET_INSTANCE_HAS_EXTEND_MDIOn(x) (0) 409 /* @brief Has Additional 1588 Timer Channel Interrupt for each instance. */ 410 #define FSL_FEATURE_ENET_INSTANCE_HAS_ADD_1588_TIMER_CHN_INTn(x) (1) 411 /* @brief Has threshold for the number of frames in the receive FIFO (register bit field RSEM[STAT_SECTION_EMPTY]). */ 412 #define FSL_FEATURE_ENET_HAS_RECEIVE_STATUS_THRESHOLD (1) 413 /* @brief Has trasfer clock delay (register bit field ECR[TXC_DLY]). */ 414 #define FSL_FEATURE_ENET_HAS_RGMII_TXC_DELAY (0) 415 /* @brief Has receive clock delay (register bit field ECR[RXC_DLY]). */ 416 #define FSL_FEATURE_ENET_HAS_RGMII_RXC_DELAY (0) 417 /* @brief PTP Timestamp CAPTURE bit always returns 0 when the capture is not over. */ 418 #define FSL_FEATURE_ENET_TIMESTAMP_CAPTURE_BIT_INVALID (1) 419 420 /* EWM module features */ 421 422 /* @brief Has clock select (register CLKCTRL). */ 423 #define FSL_FEATURE_EWM_HAS_CLOCK_SELECT (0) 424 /* @brief Has clock prescaler (register CLKPRESCALER). */ 425 #define FSL_FEATURE_EWM_HAS_PRESCALER (0) 426 427 /* FLEXBUS module features */ 428 429 /* No feature definitions */ 430 431 /* FLASH module features */ 432 433 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 434 defined(CPU_MK64FN1M0VMD12) 435 /* @brief Is of type FTFA. */ 436 #define FSL_FEATURE_FLASH_IS_FTFA (0) 437 /* @brief Is of type FTFE. */ 438 #define FSL_FEATURE_FLASH_IS_FTFE (1) 439 /* @brief Is of type FTFL. */ 440 #define FSL_FEATURE_FLASH_IS_FTFL (0) 441 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 442 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 443 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 444 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 445 /* @brief Has EEPROM region protection (register FEPROT). */ 446 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 447 /* @brief Has data flash region protection (register FDPROT). */ 448 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 449 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 450 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 451 /* @brief Has flash cache control in FMC module. */ 452 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 453 /* @brief Has flash cache control in MCM module. */ 454 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 455 /* @brief Has flash cache control in MSCM module. */ 456 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 457 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 458 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 459 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 460 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 461 /* @brief P-Flash start address. */ 462 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 463 /* @brief P-Flash block count. */ 464 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (2) 465 /* @brief P-Flash block size. */ 466 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 467 /* @brief P-Flash sector size. */ 468 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 469 /* @brief P-Flash write unit size. */ 470 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 471 /* @brief P-Flash data path width. */ 472 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 473 /* @brief P-Flash block swap feature. */ 474 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (1) 475 /* @brief P-Flash protection region count. */ 476 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 477 /* @brief Has FlexNVM memory. */ 478 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (0) 479 /* @brief Has FlexNVM alias. */ 480 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 481 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 482 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x00000000) 483 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 484 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 485 /* @brief FlexNVM block count. */ 486 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (0) 487 /* @brief FlexNVM block size. */ 488 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (0) 489 /* @brief FlexNVM sector size. */ 490 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (0) 491 /* @brief FlexNVM write unit size. */ 492 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (0) 493 /* @brief FlexNVM data path width. */ 494 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (0) 495 /* @brief Has FlexRAM memory. */ 496 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 497 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 498 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 499 /* @brief FlexRAM size. */ 500 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 501 /* @brief Has 0x00 Read 1s Block command. */ 502 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 503 /* @brief Has 0x01 Read 1s Section command. */ 504 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 505 /* @brief Has 0x02 Program Check command. */ 506 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 507 /* @brief Has 0x03 Read Resource command. */ 508 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 509 /* @brief Has 0x06 Program Longword command. */ 510 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 511 /* @brief Has 0x07 Program Phrase command. */ 512 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 513 /* @brief Has 0x08 Erase Flash Block command. */ 514 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 515 /* @brief Has 0x09 Erase Flash Sector command. */ 516 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 517 /* @brief Has 0x0B Program Section command. */ 518 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 519 /* @brief Has 0x40 Read 1s All Blocks command. */ 520 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 521 /* @brief Has 0x41 Read Once command. */ 522 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 523 /* @brief Has 0x43 Program Once command. */ 524 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 525 /* @brief Has 0x44 Erase All Blocks command. */ 526 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 527 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 528 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 529 /* @brief Has 0x46 Swap Control command. */ 530 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (1) 531 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 532 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 533 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 534 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 535 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 536 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 537 /* @brief Has 0x80 Program Partition command. */ 538 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (0) 539 /* @brief Has 0x81 Set FlexRAM Function command. */ 540 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (0) 541 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 542 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 543 /* @brief P-Flash Erase sector command address alignment. */ 544 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 545 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 546 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 547 /* @brief P-Flash Read resource command address alignment. */ 548 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 549 /* @brief P-Flash Program check command address alignment. */ 550 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 551 /* @brief P-Flash Program check command address alignment. */ 552 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (16) 553 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 554 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (0) 555 /* @brief FlexNVM Erase sector command address alignment. */ 556 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (0) 557 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 558 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (0) 559 /* @brief FlexNVM Read resource command address alignment. */ 560 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (0) 561 /* @brief FlexNVM Program check command address alignment. */ 562 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (0) 563 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 564 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0xFFFFFFFFU) 565 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 566 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 567 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 568 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0xFFFFFFFFU) 569 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 570 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0xFFFFFFFFU) 571 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 572 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0xFFFFFFFFU) 573 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 574 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0xFFFFFFFFU) 575 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 576 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 577 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 578 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 579 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 580 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0xFFFFFFFFU) 581 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 582 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 583 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 584 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0xFFFFFFFFU) 585 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 586 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0xFFFFFFFFU) 587 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 588 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0xFFFFFFFFU) 589 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 590 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0xFFFFFFFFU) 591 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 592 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 593 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 594 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0xFFFFFFFFU) 595 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 596 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 597 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 598 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 599 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 600 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 601 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 602 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 603 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 604 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 605 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 606 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 607 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 608 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 609 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 610 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 611 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 612 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 613 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 614 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 615 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 616 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 617 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 618 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 619 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 620 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 621 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 622 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 623 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 624 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 625 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 626 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 627 #elif defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) 628 /* @brief Is of type FTFA. */ 629 #define FSL_FEATURE_FLASH_IS_FTFA (0) 630 /* @brief Is of type FTFE. */ 631 #define FSL_FEATURE_FLASH_IS_FTFE (1) 632 /* @brief Is of type FTFL. */ 633 #define FSL_FEATURE_FLASH_IS_FTFL (0) 634 /* @brief Has flags indicating the status of the FlexRAM (register bits FCNFG[EEERDY], FCNFG[RAMRDY] and FCNFG[PFLSH]). */ 635 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM_FLAGS (1) 636 /* @brief Has program flash swapping status flag (register bit FCNFG[SWAP]). */ 637 #define FSL_FEATURE_FLASH_HAS_PFLASH_SWAPPING_STATUS_FLAG (1) 638 /* @brief Has EEPROM region protection (register FEPROT). */ 639 #define FSL_FEATURE_FLASH_HAS_EEROM_REGION_PROTECTION (1) 640 /* @brief Has data flash region protection (register FDPROT). */ 641 #define FSL_FEATURE_FLASH_HAS_DATA_FLASH_REGION_PROTECTION (1) 642 /* @brief Has flash access control (registers XACCHn, SACCHn, where n is a number, FACSS and FACSN). */ 643 #define FSL_FEATURE_FLASH_HAS_ACCESS_CONTROL (0) 644 /* @brief Has flash cache control in FMC module. */ 645 #define FSL_FEATURE_FLASH_HAS_FMC_FLASH_CACHE_CONTROLS (1) 646 /* @brief Has flash cache control in MCM module. */ 647 #define FSL_FEATURE_FLASH_HAS_MCM_FLASH_CACHE_CONTROLS (0) 648 /* @brief Has flash cache control in MSCM module. */ 649 #define FSL_FEATURE_FLASH_HAS_MSCM_FLASH_CACHE_CONTROLS (0) 650 /* @brief Has prefetch speculation control in flash, such as kv5x. */ 651 #define FSL_FEATURE_FLASH_PREFETCH_SPECULATION_CONTROL_IN_FLASH (0) 652 /* @brief P-Flash flash size coding rule version, value 0 for K1 and K2, value 1 for K3. */ 653 #define FSL_FEATURE_FLASH_SIZE_ENCODING_RULE_VERSION (0) 654 /* @brief P-Flash start address. */ 655 #define FSL_FEATURE_FLASH_PFLASH_START_ADDRESS (0x00000000) 656 /* @brief P-Flash block count. */ 657 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_COUNT (1) 658 /* @brief P-Flash block size. */ 659 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SIZE (524288) 660 /* @brief P-Flash sector size. */ 661 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_SECTOR_SIZE (4096) 662 /* @brief P-Flash write unit size. */ 663 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_WRITE_UNIT_SIZE (8) 664 /* @brief P-Flash data path width. */ 665 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_DATA_PATH_WIDTH (16) 666 /* @brief P-Flash block swap feature. */ 667 #define FSL_FEATURE_FLASH_HAS_PFLASH_BLOCK_SWAP (0) 668 /* @brief P-Flash protection region count. */ 669 #define FSL_FEATURE_FLASH_PFLASH_PROTECTION_REGION_COUNT (32) 670 /* @brief Has FlexNVM memory. */ 671 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM (1) 672 /* @brief Has FlexNVM alias. */ 673 #define FSL_FEATURE_FLASH_HAS_FLEX_NVM_ALIAS (0) 674 /* @brief FlexNVM start address. (Valid only if FlexNVM is available.) */ 675 #define FSL_FEATURE_FLASH_FLEX_NVM_START_ADDRESS (0x10000000) 676 /* @brief FlexNVM alias start address. (Valid only if FlexNVM alias is available.) */ 677 #define FSL_FEATURE_FLASH_FLEX_NVM_ALIAS_START_ADDRESS (0x00000000) 678 /* @brief FlexNVM block count. */ 679 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_COUNT (1) 680 /* @brief FlexNVM block size. */ 681 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SIZE (131072) 682 /* @brief FlexNVM sector size. */ 683 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_SECTOR_SIZE (4096) 684 /* @brief FlexNVM write unit size. */ 685 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_WRITE_UNIT_SIZE (8) 686 /* @brief FlexNVM data path width. */ 687 #define FSL_FEATURE_FLASH_FLEX_BLOCK_DATA_PATH_WIDTH (16) 688 /* @brief Has FlexRAM memory. */ 689 #define FSL_FEATURE_FLASH_HAS_FLEX_RAM (1) 690 /* @brief FlexRAM start address. (Valid only if FlexRAM is available.) */ 691 #define FSL_FEATURE_FLASH_FLEX_RAM_START_ADDRESS (0x14000000) 692 /* @brief FlexRAM size. */ 693 #define FSL_FEATURE_FLASH_FLEX_RAM_SIZE (4096) 694 /* @brief Has 0x00 Read 1s Block command. */ 695 #define FSL_FEATURE_FLASH_HAS_READ_1S_BLOCK_CMD (1) 696 /* @brief Has 0x01 Read 1s Section command. */ 697 #define FSL_FEATURE_FLASH_HAS_READ_1S_SECTION_CMD (1) 698 /* @brief Has 0x02 Program Check command. */ 699 #define FSL_FEATURE_FLASH_HAS_PROGRAM_CHECK_CMD (1) 700 /* @brief Has 0x03 Read Resource command. */ 701 #define FSL_FEATURE_FLASH_HAS_READ_RESOURCE_CMD (1) 702 /* @brief Has 0x06 Program Longword command. */ 703 #define FSL_FEATURE_FLASH_HAS_PROGRAM_LONGWORD_CMD (0) 704 /* @brief Has 0x07 Program Phrase command. */ 705 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PHRASE_CMD (1) 706 /* @brief Has 0x08 Erase Flash Block command. */ 707 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_BLOCK_CMD (1) 708 /* @brief Has 0x09 Erase Flash Sector command. */ 709 #define FSL_FEATURE_FLASH_HAS_ERASE_FLASH_SECTOR_CMD (1) 710 /* @brief Has 0x0B Program Section command. */ 711 #define FSL_FEATURE_FLASH_HAS_PROGRAM_SECTION_CMD (1) 712 /* @brief Has 0x40 Read 1s All Blocks command. */ 713 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_BLOCKS_CMD (1) 714 /* @brief Has 0x41 Read Once command. */ 715 #define FSL_FEATURE_FLASH_HAS_READ_ONCE_CMD (1) 716 /* @brief Has 0x43 Program Once command. */ 717 #define FSL_FEATURE_FLASH_HAS_PROGRAM_ONCE_CMD (1) 718 /* @brief Has 0x44 Erase All Blocks command. */ 719 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_CMD (1) 720 /* @brief Has 0x45 Verify Backdoor Access Key command. */ 721 #define FSL_FEATURE_FLASH_HAS_VERIFY_BACKDOOR_ACCESS_KEY_CMD (1) 722 /* @brief Has 0x46 Swap Control command. */ 723 #define FSL_FEATURE_FLASH_HAS_SWAP_CONTROL_CMD (0) 724 /* @brief Has 0x49 Erase All Blocks Unsecure command. */ 725 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_BLOCKS_UNSECURE_CMD (0) 726 /* @brief Has 0x4A Read 1s All Execute-only Segments command. */ 727 #define FSL_FEATURE_FLASH_HAS_READ_1S_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 728 /* @brief Has 0x4B Erase All Execute-only Segments command. */ 729 #define FSL_FEATURE_FLASH_HAS_ERASE_ALL_EXECUTE_ONLY_SEGMENTS_CMD (0) 730 /* @brief Has 0x80 Program Partition command. */ 731 #define FSL_FEATURE_FLASH_HAS_PROGRAM_PARTITION_CMD (1) 732 /* @brief Has 0x81 Set FlexRAM Function command. */ 733 #define FSL_FEATURE_FLASH_HAS_SET_FLEXRAM_FUNCTION_CMD (1) 734 /* @brief P-Flash Erase/Read 1st all block command address alignment. */ 735 #define FSL_FEATURE_FLASH_PFLASH_BLOCK_CMD_ADDRESS_ALIGMENT (16) 736 /* @brief P-Flash Erase sector command address alignment. */ 737 #define FSL_FEATURE_FLASH_PFLASH_SECTOR_CMD_ADDRESS_ALIGMENT (16) 738 /* @brief P-Flash Rrogram/Verify section command address alignment. */ 739 #define FSL_FEATURE_FLASH_PFLASH_SECTION_CMD_ADDRESS_ALIGMENT (16) 740 /* @brief P-Flash Read resource command address alignment. */ 741 #define FSL_FEATURE_FLASH_PFLASH_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 742 /* @brief P-Flash Program check command address alignment. */ 743 #define FSL_FEATURE_FLASH_PFLASH_CHECK_CMD_ADDRESS_ALIGMENT (4) 744 /* @brief P-Flash Program check command address alignment. */ 745 #define FSL_FEATURE_FLASH_PFLASH_SWAP_CONTROL_CMD_ADDRESS_ALIGMENT (0) 746 /* @brief FlexNVM Erase/Read 1st all block command address alignment. */ 747 #define FSL_FEATURE_FLASH_FLEX_NVM_BLOCK_CMD_ADDRESS_ALIGMENT (16) 748 /* @brief FlexNVM Erase sector command address alignment. */ 749 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTOR_CMD_ADDRESS_ALIGMENT (16) 750 /* @brief FlexNVM Rrogram/Verify section command address alignment. */ 751 #define FSL_FEATURE_FLASH_FLEX_NVM_SECTION_CMD_ADDRESS_ALIGMENT (16) 752 /* @brief FlexNVM Read resource command address alignment. */ 753 #define FSL_FEATURE_FLASH_FLEX_NVM_RESOURCE_CMD_ADDRESS_ALIGMENT (8) 754 /* @brief FlexNVM Program check command address alignment. */ 755 #define FSL_FEATURE_FLASH_FLEX_NVM_CHECK_CMD_ADDRESS_ALIGMENT (4) 756 /* @brief FlexNVM partition code 0000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 757 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0000 (0x00020000U) 758 /* @brief FlexNVM partition code 0001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 759 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0001 (0xFFFFFFFFU) 760 /* @brief FlexNVM partition code 0010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 761 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0010 (0x0001C000U) 762 /* @brief FlexNVM partition code 0011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 763 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0011 (0x00018000U) 764 /* @brief FlexNVM partition code 0100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 765 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0100 (0x00010000U) 766 /* @brief FlexNVM partition code 0101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 767 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0101 (0x00000000U) 768 /* @brief FlexNVM partition code 0110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 769 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0110 (0xFFFFFFFFU) 770 /* @brief FlexNVM partition code 0111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 771 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_0111 (0xFFFFFFFFU) 772 /* @brief FlexNVM partition code 1000 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 773 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1000 (0x00000000U) 774 /* @brief FlexNVM partition code 1001 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 775 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1001 (0xFFFFFFFFU) 776 /* @brief FlexNVM partition code 1010 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 777 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1010 (0x00004000U) 778 /* @brief FlexNVM partition code 1011 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 779 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1011 (0x00008000U) 780 /* @brief FlexNVM partition code 1100 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 781 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1100 (0x00010000U) 782 /* @brief FlexNVM partition code 1101 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 783 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1101 (0x00020000U) 784 /* @brief FlexNVM partition code 1110 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 785 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1110 (0xFFFFFFFFU) 786 /* @brief FlexNVM partition code 1111 mapping to data flash size in bytes (0xFFFFFFFF = reserved). */ 787 #define FSL_FEATURE_FLASH_FLEX_NVM_DFLASH_SIZE_FOR_DEPART_1111 (0x00020000U) 788 /* @brief Emulated eeprom size code 0000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 789 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0000 (0xFFFF) 790 /* @brief Emulated eeprom size code 0001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 791 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0001 (0xFFFF) 792 /* @brief Emulated eeprom size code 0010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 793 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0010 (0x1000) 794 /* @brief Emulated eeprom size code 0011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 795 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0011 (0x0800) 796 /* @brief Emulated eeprom size code 0100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 797 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0100 (0x0400) 798 /* @brief Emulated eeprom size code 0101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 799 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0101 (0x0200) 800 /* @brief Emulated eeprom size code 0110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 801 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0110 (0x0100) 802 /* @brief Emulated eeprom size code 0111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 803 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_0111 (0x0080) 804 /* @brief Emulated eeprom size code 1000 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 805 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1000 (0x0040) 806 /* @brief Emulated eeprom size code 1001 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 807 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1001 (0x0020) 808 /* @brief Emulated eeprom size code 1010 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 809 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1010 (0xFFFF) 810 /* @brief Emulated eeprom size code 1011 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 811 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1011 (0xFFFF) 812 /* @brief Emulated eeprom size code 1100 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 813 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1100 (0xFFFF) 814 /* @brief Emulated eeprom size code 1101 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 815 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1101 (0xFFFF) 816 /* @brief Emulated eeprom size code 1110 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 817 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1110 (0xFFFF) 818 /* @brief Emulated eeprom size code 1111 mapping to emulated eeprom size in bytes (0xFFFF = reserved). */ 819 #define FSL_FEATURE_FLASH_FLEX_NVM_EEPROM_SIZE_FOR_EEESIZE_1111 (0x0000) 820 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 821 defined(CPU_MK64FN1M0VMD12) */ 822 823 /* FTM module features */ 824 825 /* @brief Number of channels. */ 826 #define FSL_FEATURE_FTM_CHANNEL_COUNTn(x) \ 827 (((x) == FTM0) ? (8) : \ 828 (((x) == FTM1) ? (2) : \ 829 (((x) == FTM2) ? (2) : \ 830 (((x) == FTM3) ? (8) : (-1))))) 831 /* @brief Has counter reset by the selected input capture event (register bits C0SC[ICRST], C1SC[ICRST], ...). */ 832 #define FSL_FEATURE_FTM_HAS_COUNTER_RESET_BY_CAPTURE_EVENT (0) 833 /* @brief Has extended deadtime value. */ 834 #define FSL_FEATURE_FTM_HAS_EXTENDED_DEADTIME_VALUE (0) 835 /* @brief Enable pwm output for the module. */ 836 #define FSL_FEATURE_FTM_HAS_ENABLE_PWM_OUTPUT (0) 837 /* @brief Has half-cycle reload for the module. */ 838 #define FSL_FEATURE_FTM_HAS_HALFCYCLE_RELOAD (0) 839 /* @brief Has reload interrupt. */ 840 #define FSL_FEATURE_FTM_HAS_RELOAD_INTERRUPT (0) 841 /* @brief Has reload initialization trigger. */ 842 #define FSL_FEATURE_FTM_HAS_RELOAD_INITIALIZATION_TRIGGER (0) 843 /* @brief Has DMA support, bitfield CnSC[DMA]. */ 844 #define FSL_FEATURE_FTM_HAS_DMA_SUPPORT (1) 845 /* @brief If channel 6 is used to generate channel trigger, bitfield EXTTRIG[CH6TRIG]. */ 846 #define FSL_FEATURE_FTM_HAS_CHANNEL6_TRIGGER (0) 847 /* @brief If channel 7 is used to generate channel trigger, bitfield EXTTRIG[CH7TRIG]. */ 848 #define FSL_FEATURE_FTM_HAS_CHANNEL7_TRIGGER (0) 849 /* @brief Has no QDCTRL. */ 850 #define FSL_FEATURE_FTM_HAS_NO_QDCTRL (0) 851 /* @brief If instance has only TPM function. */ 852 #define FSL_FEATURE_FTM_IS_TPM_ONLY_INSTANCEn(x) (0) 853 854 /* GPIO module features */ 855 856 /* @brief Has GPIO attribute checker register (GACR). */ 857 #define FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER (0) 858 859 /* I2C module features */ 860 861 /* @brief Has System Management Bus support (registers SMB, A2, SLTL and SLTH). */ 862 #define FSL_FEATURE_I2C_HAS_SMBUS (1) 863 /* @brief Maximum supported baud rate in kilobit per second. */ 864 #define FSL_FEATURE_I2C_MAX_BAUD_KBPS (400) 865 /* @brief Is affected by errata with ID 6070 (repeat start cannot be generated if the F[MULT] bit field is set to a non-zero value). */ 866 #define FSL_FEATURE_I2C_HAS_ERRATA_6070 (0) 867 /* @brief Has DMA support (register bit C1[DMAEN]). */ 868 #define FSL_FEATURE_I2C_HAS_DMA_SUPPORT (1) 869 /* @brief Has I2C bus start and stop detection (register bits FLT[SSIE], FLT[STARTF] and FLT[STOPF]). */ 870 #define FSL_FEATURE_I2C_HAS_START_STOP_DETECT (1) 871 /* @brief Has I2C bus stop detection (register bits FLT[STOPIE] and FLT[STOPF]). */ 872 #define FSL_FEATURE_I2C_HAS_STOP_DETECT (0) 873 /* @brief Has I2C bus stop hold off (register bit FLT[SHEN]). */ 874 #define FSL_FEATURE_I2C_HAS_STOP_HOLD_OFF (1) 875 /* @brief Maximum width of the glitch filter in number of bus clocks. */ 876 #define FSL_FEATURE_I2C_MAX_GLITCH_FILTER_WIDTH (15) 877 /* @brief Has control of the drive capability of the I2C pins. */ 878 #define FSL_FEATURE_I2C_HAS_HIGH_DRIVE_SELECTION (1) 879 /* @brief Has double buffering support (register S2). */ 880 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFERING (0) 881 /* @brief Has double buffer enable. */ 882 #define FSL_FEATURE_I2C_HAS_DOUBLE_BUFFER_ENABLE (0) 883 884 /* SAI module features */ 885 886 /* @brief Receive/transmit FIFO size in item count (register bit fields TCSR[FRDE], TCSR[FRIE], TCSR[FRF], TCR1[TFW], RCSR[FRDE], RCSR[FRIE], RCSR[FRF], RCR1[RFW], registers TFRn, RFRn). */ 887 #define FSL_FEATURE_SAI_FIFO_COUNT (8) 888 /* @brief Receive/transmit channel number (register bit fields TCR3[TCE], RCR3[RCE], registers TDRn and RDRn). */ 889 #define FSL_FEATURE_SAI_CHANNEL_COUNTn(x) (2) 890 /* @brief Maximum words per frame (register bit fields TCR3[WDFL], TCR4[FRSZ], TMR[TWM], RCR3[WDFL], RCR4[FRSZ], RMR[RWM]). */ 891 #define FSL_FEATURE_SAI_MAX_WORDS_PER_FRAME (32) 892 /* @brief Has support of combining multiple data channel FIFOs into single channel FIFO (register bit fields TCR3[CFR], TCR4[FCOMB], TFR0[WCP], TFR1[WCP], RCR3[CFR], RCR4[FCOMB], RFR0[RCP], RFR1[RCP]). */ 893 #define FSL_FEATURE_SAI_HAS_FIFO_COMBINE_MODE (0) 894 /* @brief Has packing of 8-bit and 16-bit data into each 32-bit FIFO word (register bit fields TCR4[FPACK], RCR4[FPACK]). */ 895 #define FSL_FEATURE_SAI_HAS_FIFO_PACKING (0) 896 /* @brief Configures when the SAI will continue transmitting after a FIFO error has been detected (register bit fields TCR4[FCONT], RCR4[FCONT]). */ 897 #define FSL_FEATURE_SAI_HAS_FIFO_FUNCTION_AFTER_ERROR (0) 898 /* @brief Configures if the frame sync is generated internally, a frame sync is only generated when the FIFO warning flag is clear or continuously (register bit fields TCR4[ONDEM], RCR4[ONDEM]). */ 899 #define FSL_FEATURE_SAI_HAS_ON_DEMAND_MODE (0) 900 /* @brief Simplified bit clock source and asynchronous/synchronous mode selection (register bit fields TCR2[CLKMODE], RCR2[CLKMODE]), in comparison with the exclusively implemented TCR2[SYNC,BCS,BCI,MSEL], RCR2[SYNC,BCS,BCI,MSEL]. */ 901 #define FSL_FEATURE_SAI_HAS_CLOCKING_MODE (0) 902 /* @brief Has register for configuration of the MCLK divide ratio (register bit fields MDR[FRACT], MDR[DIVIDE]). */ 903 #define FSL_FEATURE_SAI_HAS_MCLKDIV_REGISTER (1) 904 /* @brief Ihe interrupt source number */ 905 #define FSL_FEATURE_SAI_INT_SOURCE_NUM (2) 906 /* @brief Has register of MCR. */ 907 #define FSL_FEATURE_SAI_HAS_MCR (1) 908 /* @brief Has register of MDR */ 909 #define FSL_FEATURE_SAI_HAS_MDR (1) 910 /* @brief Has DIV bit fields of MCR register (register bit fields MCR[DIV]. */ 911 #define FSL_FEATURE_SAI_HAS_MCR_MCLK_POST_DIV (0) 912 /* @brief Support Channel Mode (register bit fields TCR4[CHMOD]). */ 913 #define FSL_FEATURE_SAI_HAS_CHANNEL_MODE (0) 914 915 /* LLWU module features */ 916 917 /* @brief Maximum number of pins (maximal index plus one) connected to LLWU device. */ 918 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN (16) 919 /* @brief Has pins 8-15 connected to LLWU device. */ 920 #define FSL_FEATURE_LLWU_EXTERNAL_PIN_GROUP2 (1) 921 /* @brief Maximum number of internal modules connected to LLWU device. */ 922 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE (8) 923 /* @brief Number of digital filters. */ 924 #define FSL_FEATURE_LLWU_HAS_PIN_FILTER (2) 925 /* @brief Has MF register. */ 926 #define FSL_FEATURE_LLWU_HAS_MF (0) 927 /* @brief Has PF register. */ 928 #define FSL_FEATURE_LLWU_HAS_PF (0) 929 /* @brief Has possibility to enable reset in low leakage power mode and enable digital filter for RESET pin (register LLWU_RST). */ 930 #define FSL_FEATURE_LLWU_HAS_RESET_ENABLE (1) 931 /* @brief Has no internal module wakeup flag register. */ 932 #define FSL_FEATURE_LLWU_HAS_NO_INTERNAL_MODULE_WAKEUP_FLAG_REG (0) 933 /* @brief Has external pin 0 connected to LLWU device. */ 934 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN0 (1) 935 /* @brief Index of port of external pin. */ 936 #define FSL_FEATURE_LLWU_PIN0_GPIO_IDX (GPIOE_IDX) 937 /* @brief Number of external pin port on specified port. */ 938 #define FSL_FEATURE_LLWU_PIN0_GPIO_PIN (1) 939 /* @brief Has external pin 1 connected to LLWU device. */ 940 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN1 (1) 941 /* @brief Index of port of external pin. */ 942 #define FSL_FEATURE_LLWU_PIN1_GPIO_IDX (GPIOE_IDX) 943 /* @brief Number of external pin port on specified port. */ 944 #define FSL_FEATURE_LLWU_PIN1_GPIO_PIN (2) 945 /* @brief Has external pin 2 connected to LLWU device. */ 946 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN2 (1) 947 /* @brief Index of port of external pin. */ 948 #define FSL_FEATURE_LLWU_PIN2_GPIO_IDX (GPIOE_IDX) 949 /* @brief Number of external pin port on specified port. */ 950 #define FSL_FEATURE_LLWU_PIN2_GPIO_PIN (4) 951 /* @brief Has external pin 3 connected to LLWU device. */ 952 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN3 (1) 953 /* @brief Index of port of external pin. */ 954 #define FSL_FEATURE_LLWU_PIN3_GPIO_IDX (GPIOA_IDX) 955 /* @brief Number of external pin port on specified port. */ 956 #define FSL_FEATURE_LLWU_PIN3_GPIO_PIN (4) 957 /* @brief Has external pin 4 connected to LLWU device. */ 958 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN4 (1) 959 /* @brief Index of port of external pin. */ 960 #define FSL_FEATURE_LLWU_PIN4_GPIO_IDX (GPIOA_IDX) 961 /* @brief Number of external pin port on specified port. */ 962 #define FSL_FEATURE_LLWU_PIN4_GPIO_PIN (13) 963 /* @brief Has external pin 5 connected to LLWU device. */ 964 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN5 (1) 965 /* @brief Index of port of external pin. */ 966 #define FSL_FEATURE_LLWU_PIN5_GPIO_IDX (GPIOB_IDX) 967 /* @brief Number of external pin port on specified port. */ 968 #define FSL_FEATURE_LLWU_PIN5_GPIO_PIN (0) 969 /* @brief Has external pin 6 connected to LLWU device. */ 970 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN6 (1) 971 /* @brief Index of port of external pin. */ 972 #define FSL_FEATURE_LLWU_PIN6_GPIO_IDX (GPIOC_IDX) 973 /* @brief Number of external pin port on specified port. */ 974 #define FSL_FEATURE_LLWU_PIN6_GPIO_PIN (1) 975 /* @brief Has external pin 7 connected to LLWU device. */ 976 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN7 (1) 977 /* @brief Index of port of external pin. */ 978 #define FSL_FEATURE_LLWU_PIN7_GPIO_IDX (GPIOC_IDX) 979 /* @brief Number of external pin port on specified port. */ 980 #define FSL_FEATURE_LLWU_PIN7_GPIO_PIN (3) 981 /* @brief Has external pin 8 connected to LLWU device. */ 982 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN8 (1) 983 /* @brief Index of port of external pin. */ 984 #define FSL_FEATURE_LLWU_PIN8_GPIO_IDX (GPIOC_IDX) 985 /* @brief Number of external pin port on specified port. */ 986 #define FSL_FEATURE_LLWU_PIN8_GPIO_PIN (4) 987 /* @brief Has external pin 9 connected to LLWU device. */ 988 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN9 (1) 989 /* @brief Index of port of external pin. */ 990 #define FSL_FEATURE_LLWU_PIN9_GPIO_IDX (GPIOC_IDX) 991 /* @brief Number of external pin port on specified port. */ 992 #define FSL_FEATURE_LLWU_PIN9_GPIO_PIN (5) 993 /* @brief Has external pin 10 connected to LLWU device. */ 994 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN10 (1) 995 /* @brief Index of port of external pin. */ 996 #define FSL_FEATURE_LLWU_PIN10_GPIO_IDX (GPIOC_IDX) 997 /* @brief Number of external pin port on specified port. */ 998 #define FSL_FEATURE_LLWU_PIN10_GPIO_PIN (6) 999 /* @brief Has external pin 11 connected to LLWU device. */ 1000 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN11 (1) 1001 /* @brief Index of port of external pin. */ 1002 #define FSL_FEATURE_LLWU_PIN11_GPIO_IDX (GPIOC_IDX) 1003 /* @brief Number of external pin port on specified port. */ 1004 #define FSL_FEATURE_LLWU_PIN11_GPIO_PIN (11) 1005 /* @brief Has external pin 12 connected to LLWU device. */ 1006 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN12 (1) 1007 /* @brief Index of port of external pin. */ 1008 #define FSL_FEATURE_LLWU_PIN12_GPIO_IDX (GPIOD_IDX) 1009 /* @brief Number of external pin port on specified port. */ 1010 #define FSL_FEATURE_LLWU_PIN12_GPIO_PIN (0) 1011 /* @brief Has external pin 13 connected to LLWU device. */ 1012 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN13 (1) 1013 /* @brief Index of port of external pin. */ 1014 #define FSL_FEATURE_LLWU_PIN13_GPIO_IDX (GPIOD_IDX) 1015 /* @brief Number of external pin port on specified port. */ 1016 #define FSL_FEATURE_LLWU_PIN13_GPIO_PIN (2) 1017 /* @brief Has external pin 14 connected to LLWU device. */ 1018 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN14 (1) 1019 /* @brief Index of port of external pin. */ 1020 #define FSL_FEATURE_LLWU_PIN14_GPIO_IDX (GPIOD_IDX) 1021 /* @brief Number of external pin port on specified port. */ 1022 #define FSL_FEATURE_LLWU_PIN14_GPIO_PIN (4) 1023 /* @brief Has external pin 15 connected to LLWU device. */ 1024 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN15 (1) 1025 /* @brief Index of port of external pin. */ 1026 #define FSL_FEATURE_LLWU_PIN15_GPIO_IDX (GPIOD_IDX) 1027 /* @brief Number of external pin port on specified port. */ 1028 #define FSL_FEATURE_LLWU_PIN15_GPIO_PIN (6) 1029 /* @brief Has external pin 16 connected to LLWU device. */ 1030 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN16 (0) 1031 /* @brief Index of port of external pin. */ 1032 #define FSL_FEATURE_LLWU_PIN16_GPIO_IDX (0) 1033 /* @brief Number of external pin port on specified port. */ 1034 #define FSL_FEATURE_LLWU_PIN16_GPIO_PIN (0) 1035 /* @brief Has external pin 17 connected to LLWU device. */ 1036 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN17 (0) 1037 /* @brief Index of port of external pin. */ 1038 #define FSL_FEATURE_LLWU_PIN17_GPIO_IDX (0) 1039 /* @brief Number of external pin port on specified port. */ 1040 #define FSL_FEATURE_LLWU_PIN17_GPIO_PIN (0) 1041 /* @brief Has external pin 18 connected to LLWU device. */ 1042 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN18 (0) 1043 /* @brief Index of port of external pin. */ 1044 #define FSL_FEATURE_LLWU_PIN18_GPIO_IDX (0) 1045 /* @brief Number of external pin port on specified port. */ 1046 #define FSL_FEATURE_LLWU_PIN18_GPIO_PIN (0) 1047 /* @brief Has external pin 19 connected to LLWU device. */ 1048 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN19 (0) 1049 /* @brief Index of port of external pin. */ 1050 #define FSL_FEATURE_LLWU_PIN19_GPIO_IDX (0) 1051 /* @brief Number of external pin port on specified port. */ 1052 #define FSL_FEATURE_LLWU_PIN19_GPIO_PIN (0) 1053 /* @brief Has external pin 20 connected to LLWU device. */ 1054 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN20 (0) 1055 /* @brief Index of port of external pin. */ 1056 #define FSL_FEATURE_LLWU_PIN20_GPIO_IDX (0) 1057 /* @brief Number of external pin port on specified port. */ 1058 #define FSL_FEATURE_LLWU_PIN20_GPIO_PIN (0) 1059 /* @brief Has external pin 21 connected to LLWU device. */ 1060 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN21 (0) 1061 /* @brief Index of port of external pin. */ 1062 #define FSL_FEATURE_LLWU_PIN21_GPIO_IDX (0) 1063 /* @brief Number of external pin port on specified port. */ 1064 #define FSL_FEATURE_LLWU_PIN21_GPIO_PIN (0) 1065 /* @brief Has external pin 22 connected to LLWU device. */ 1066 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN22 (0) 1067 /* @brief Index of port of external pin. */ 1068 #define FSL_FEATURE_LLWU_PIN22_GPIO_IDX (0) 1069 /* @brief Number of external pin port on specified port. */ 1070 #define FSL_FEATURE_LLWU_PIN22_GPIO_PIN (0) 1071 /* @brief Has external pin 23 connected to LLWU device. */ 1072 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN23 (0) 1073 /* @brief Index of port of external pin. */ 1074 #define FSL_FEATURE_LLWU_PIN23_GPIO_IDX (0) 1075 /* @brief Number of external pin port on specified port. */ 1076 #define FSL_FEATURE_LLWU_PIN23_GPIO_PIN (0) 1077 /* @brief Has external pin 24 connected to LLWU device. */ 1078 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN24 (0) 1079 /* @brief Index of port of external pin. */ 1080 #define FSL_FEATURE_LLWU_PIN24_GPIO_IDX (0) 1081 /* @brief Number of external pin port on specified port. */ 1082 #define FSL_FEATURE_LLWU_PIN24_GPIO_PIN (0) 1083 /* @brief Has external pin 25 connected to LLWU device. */ 1084 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN25 (0) 1085 /* @brief Index of port of external pin. */ 1086 #define FSL_FEATURE_LLWU_PIN25_GPIO_IDX (0) 1087 /* @brief Number of external pin port on specified port. */ 1088 #define FSL_FEATURE_LLWU_PIN25_GPIO_PIN (0) 1089 /* @brief Has external pin 26 connected to LLWU device. */ 1090 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN26 (0) 1091 /* @brief Index of port of external pin. */ 1092 #define FSL_FEATURE_LLWU_PIN26_GPIO_IDX (0) 1093 /* @brief Number of external pin port on specified port. */ 1094 #define FSL_FEATURE_LLWU_PIN26_GPIO_PIN (0) 1095 /* @brief Has external pin 27 connected to LLWU device. */ 1096 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN27 (0) 1097 /* @brief Index of port of external pin. */ 1098 #define FSL_FEATURE_LLWU_PIN27_GPIO_IDX (0) 1099 /* @brief Number of external pin port on specified port. */ 1100 #define FSL_FEATURE_LLWU_PIN27_GPIO_PIN (0) 1101 /* @brief Has external pin 28 connected to LLWU device. */ 1102 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN28 (0) 1103 /* @brief Index of port of external pin. */ 1104 #define FSL_FEATURE_LLWU_PIN28_GPIO_IDX (0) 1105 /* @brief Number of external pin port on specified port. */ 1106 #define FSL_FEATURE_LLWU_PIN28_GPIO_PIN (0) 1107 /* @brief Has external pin 29 connected to LLWU device. */ 1108 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN29 (0) 1109 /* @brief Index of port of external pin. */ 1110 #define FSL_FEATURE_LLWU_PIN29_GPIO_IDX (0) 1111 /* @brief Number of external pin port on specified port. */ 1112 #define FSL_FEATURE_LLWU_PIN29_GPIO_PIN (0) 1113 /* @brief Has external pin 30 connected to LLWU device. */ 1114 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN30 (0) 1115 /* @brief Index of port of external pin. */ 1116 #define FSL_FEATURE_LLWU_PIN30_GPIO_IDX (0) 1117 /* @brief Number of external pin port on specified port. */ 1118 #define FSL_FEATURE_LLWU_PIN30_GPIO_PIN (0) 1119 /* @brief Has external pin 31 connected to LLWU device. */ 1120 #define FSL_FEATURE_LLWU_HAS_EXTERNAL_PIN31 (0) 1121 /* @brief Index of port of external pin. */ 1122 #define FSL_FEATURE_LLWU_PIN31_GPIO_IDX (0) 1123 /* @brief Number of external pin port on specified port. */ 1124 #define FSL_FEATURE_LLWU_PIN31_GPIO_PIN (0) 1125 /* @brief Has internal module 0 connected to LLWU device. */ 1126 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE0 (1) 1127 /* @brief Has internal module 1 connected to LLWU device. */ 1128 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE1 (1) 1129 /* @brief Has internal module 2 connected to LLWU device. */ 1130 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE2 (1) 1131 /* @brief Has internal module 3 connected to LLWU device. */ 1132 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE3 (1) 1133 /* @brief Has internal module 4 connected to LLWU device. */ 1134 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE4 (0) 1135 /* @brief Has internal module 5 connected to LLWU device. */ 1136 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE5 (1) 1137 /* @brief Has internal module 6 connected to LLWU device. */ 1138 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE6 (0) 1139 /* @brief Has internal module 7 connected to LLWU device. */ 1140 #define FSL_FEATURE_LLWU_HAS_INTERNAL_MODULE7 (1) 1141 /* @brief Has Version ID Register (LLWU_VERID). */ 1142 #define FSL_FEATURE_LLWU_HAS_VERID (0) 1143 /* @brief Has Parameter Register (LLWU_PARAM). */ 1144 #define FSL_FEATURE_LLWU_HAS_PARAM (0) 1145 /* @brief Width of registers of the LLWU. */ 1146 #define FSL_FEATURE_LLWU_REG_BITWIDTH (8) 1147 /* @brief Has DMA Enable register (LLWU_DE). */ 1148 #define FSL_FEATURE_LLWU_HAS_DMA_ENABLE_REG (0) 1149 1150 /* LPTMR module features */ 1151 1152 /* @brief Has shared interrupt handler with another LPTMR module. */ 1153 #define FSL_FEATURE_LPTMR_HAS_SHARED_IRQ_HANDLER (0) 1154 /* @brief Whether LPTMR counter is 32 bits width. */ 1155 #define FSL_FEATURE_LPTMR_CNR_WIDTH_IS_32B (0) 1156 /* @brief Has timer DMA request enable (register bit CSR[TDRE]). */ 1157 #define FSL_FEATURE_LPTMR_HAS_CSR_TDRE (0) 1158 1159 /* MCG module features */ 1160 1161 /* @brief PRDIV base value (divider of register bit field [PRDIV] zero value). */ 1162 #define FSL_FEATURE_MCG_PLL_PRDIV_BASE (1) 1163 /* @brief Maximum PLL external reference divider value (max. value of register bit field C5[PRVDIV]). */ 1164 #define FSL_FEATURE_MCG_PLL_PRDIV_MAX (24) 1165 /* @brief VCO divider base value (multiply factor of register bit field C6[VDIV] zero value). */ 1166 #define FSL_FEATURE_MCG_PLL_VDIV_BASE (24) 1167 /* @brief PLL reference clock low range. OSCCLK/PLL_R. */ 1168 #define FSL_FEATURE_MCG_PLL_REF_MIN (2000000) 1169 /* @brief PLL reference clock high range. OSCCLK/PLL_R. */ 1170 #define FSL_FEATURE_MCG_PLL_REF_MAX (4000000) 1171 /* @brief The PLL clock is divided by 2 before VCO divider. */ 1172 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_DIV (0) 1173 /* @brief FRDIV supports 1280. */ 1174 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1280 (1) 1175 /* @brief FRDIV supports 1536. */ 1176 #define FSL_FEATURE_MCG_FRDIV_SUPPORT_1536 (1) 1177 /* @brief MCGFFCLK divider. */ 1178 #define FSL_FEATURE_MCG_FFCLK_DIV (1) 1179 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection in the SIM module. */ 1180 #define FSL_FEATURE_MCG_HAS_PLL_EXTRA_DIV (0) 1181 /* @brief Has 32kHz RTC external reference clock (register bits C8[LOCS1], C8[CME1], C8[LOCRE1] and RTC module are present). */ 1182 #define FSL_FEATURE_MCG_HAS_RTC_32K (1) 1183 /* @brief Has PLL1 external reference clock (registers C10, C11, C12, S2). */ 1184 #define FSL_FEATURE_MCG_HAS_PLL1 (0) 1185 /* @brief Has 48MHz internal oscillator. */ 1186 #define FSL_FEATURE_MCG_HAS_IRC_48M (1) 1187 /* @brief Has OSC1 external oscillator (registers C10, C11, C12, S2). */ 1188 #define FSL_FEATURE_MCG_HAS_OSC1 (0) 1189 /* @brief Has fast internal reference clock fine trim (register bit C2[FCFTRIM]). */ 1190 #define FSL_FEATURE_MCG_HAS_FCFTRIM (1) 1191 /* @brief Has PLL loss of lock reset (register bit C8[LOLRE]). */ 1192 #define FSL_FEATURE_MCG_HAS_LOLRE (1) 1193 /* @brief Has MCG OSC clock selection (register bit C7[OSCSEL]). */ 1194 #define FSL_FEATURE_MCG_USE_OSCSEL (1) 1195 /* @brief Has PLL external reference selection (register bits C5[PLLREFSEL0] and C11[PLLREFSEL1]). */ 1196 #define FSL_FEATURE_MCG_USE_PLLREFSEL (0) 1197 /* @brief TBD */ 1198 #define FSL_FEATURE_MCG_USE_SYSTEM_CLOCK (0) 1199 /* @brief Has phase-locked loop (PLL) (register C5 and bits C6[VDIV], C6[PLLS], C6[LOLIE0], S[PLLST], S[LOCK0], S[LOLS0]). */ 1200 #define FSL_FEATURE_MCG_HAS_PLL (1) 1201 /* @brief Has phase-locked loop (PLL) PRDIV (register C5[PRDIV]. */ 1202 #define FSL_FEATURE_MCG_HAS_PLL_PRDIV (1) 1203 /* @brief Has phase-locked loop (PLL) VDIV (register C6[VDIV]. */ 1204 #define FSL_FEATURE_MCG_HAS_PLL_VDIV (1) 1205 /* @brief PLL/OSC related register bit fields have PLL/OSC index in their name. */ 1206 #define FSL_FEATURE_MCG_HAS_PLL_OSC_INDEX (0) 1207 /* @brief Has frequency-locked loop (FLL) (register ATCVH, ATCVL and bits C1[IREFS], C1[FRDIV]). */ 1208 #define FSL_FEATURE_MCG_HAS_FLL (1) 1209 /* @brief Has PLL external to MCG (C9[PLL_CME], C9[PLL_LOCRE], C9[EXT_PLL_LOCS]). */ 1210 #define FSL_FEATURE_MCG_HAS_EXTERNAL_PLL (0) 1211 /* @brief Has crystal oscillator or external reference clock low power controls (register bits C2[HGO], C2[RANGE]). */ 1212 #define FSL_FEATURE_MCG_HAS_EXT_REF_LOW_POWER_CONTROL (1) 1213 /* @brief Has PLL/FLL selection as MCG output (register bit C6[PLLS]). */ 1214 #define FSL_FEATURE_MCG_HAS_PLL_FLL_SELECTION (1) 1215 /* @brief Has PLL output selection (PLL0/PLL1, PLL/external PLL) (register bit C11[PLLCS]). */ 1216 #define FSL_FEATURE_MCG_HAS_PLL_OUTPUT_SELECTION (0) 1217 /* @brief Has automatic trim machine (registers ATCVH, ATCVL and bits SC[ATMF], SC[ATMS], SC[ATME]). */ 1218 #define FSL_FEATURE_MCG_HAS_AUTO_TRIM_MACHINE (1) 1219 /* @brief Has external clock monitor (register bit C6[CME]). */ 1220 #define FSL_FEATURE_MCG_HAS_EXTERNAL_CLOCK_MONITOR (1) 1221 /* @brief Has low frequency internal reference clock (IRC) (registers LTRIMRNG, LFRIM, LSTRIM and bit MC[LIRC_DIV2]). */ 1222 #define FSL_FEATURE_MCG_HAS_LOW_FREQ_IRC (0) 1223 /* @brief Has high frequency internal reference clock (IRC) (registers HCTRIM, HTTRIM, HFTRIM and bit MC[HIRCEN]). */ 1224 #define FSL_FEATURE_MCG_HAS_HIGH_FREQ_IRC (0) 1225 /* @brief Has PEI mode or PBI mode. */ 1226 #define FSL_FEATURE_MCG_HAS_PLL_INTERNAL_MODE (0) 1227 /* @brief Reset clock mode is BLPI. */ 1228 #define FSL_FEATURE_MCG_RESET_IS_BLPI (0) 1229 1230 /* interrupt module features */ 1231 1232 /* @brief Lowest interrupt request number. */ 1233 #define FSL_FEATURE_INTERRUPT_IRQ_MIN (-14) 1234 /* @brief Highest interrupt request number. */ 1235 #define FSL_FEATURE_INTERRUPT_IRQ_MAX (85) 1236 1237 /* OSC module features */ 1238 1239 /* @brief Has OSC1 external oscillator. */ 1240 #define FSL_FEATURE_OSC_HAS_OSC1 (0) 1241 /* @brief Has OSC0 external oscillator. */ 1242 #define FSL_FEATURE_OSC_HAS_OSC0 (0) 1243 /* @brief Has OSC external oscillator (without index). */ 1244 #define FSL_FEATURE_OSC_HAS_OSC (1) 1245 /* @brief Number of OSC external oscillators. */ 1246 #define FSL_FEATURE_OSC_OSC_COUNT (1) 1247 /* @brief Has external reference clock divider (register bit field DIV[ERPS]). */ 1248 #define FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER (0) 1249 1250 /* PDB module features */ 1251 1252 /* @brief Has DAC support. */ 1253 #define FSL_FEATURE_PDB_HAS_DAC (1) 1254 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1255 #define FSL_FEATURE_PDB_HAS_SHARED_IRQ_HANDLER (0) 1256 /* @brief PDB channel number). */ 1257 #define FSL_FEATURE_PDB_CHANNEL_COUNT (2) 1258 /* @brief Channel pre-trigger nunmber (related to number of registers CHmDLYn). */ 1259 #define FSL_FEATURE_PDB_CHANNEL_PRE_TRIGGER_COUNT (2) 1260 /* @brief DAC interval trigger number). */ 1261 #define FSL_FEATURE_PDB_DAC_INTERVAL_TRIGGER_COUNT (2) 1262 /* @brief Pulse out number). */ 1263 #define FSL_FEATURE_PDB_PULSE_OUT_COUNT (3) 1264 1265 /* PIT module features */ 1266 1267 /* @brief Number of channels (related to number of registers LDVALn, CVALn, TCTRLn, TFLGn). */ 1268 #define FSL_FEATURE_PIT_TIMER_COUNT (4) 1269 /* @brief Has lifetime timer (related to existence of registers LTMR64L and LTMR64H). */ 1270 #define FSL_FEATURE_PIT_HAS_LIFETIME_TIMER (0) 1271 /* @brief Has chain mode (related to existence of register bit field TCTRLn[CHN]). */ 1272 #define FSL_FEATURE_PIT_HAS_CHAIN_MODE (1) 1273 /* @brief Has shared interrupt handler (has not individual interrupt handler for each channel). */ 1274 #define FSL_FEATURE_PIT_HAS_SHARED_IRQ_HANDLER (0) 1275 /* @brief Has timer enable control. */ 1276 #define FSL_FEATURE_PIT_HAS_MDIS (1) 1277 1278 /* PMC module features */ 1279 1280 /* @brief Has Bandgap Enable In VLPx Operation support. */ 1281 #define FSL_FEATURE_PMC_HAS_BGEN (1) 1282 /* @brief Has Bandgap Buffer Enable. */ 1283 #define FSL_FEATURE_PMC_HAS_BGBE (1) 1284 /* @brief Has Bandgap Buffer Drive Select. */ 1285 #define FSL_FEATURE_PMC_HAS_BGBDS (0) 1286 /* @brief Has Low-Voltage Detect Voltage Select support. */ 1287 #define FSL_FEATURE_PMC_HAS_LVDV (1) 1288 /* @brief Has Low-Voltage Warning Voltage Select support. */ 1289 #define FSL_FEATURE_PMC_HAS_LVWV (1) 1290 /* @brief Has LPO. */ 1291 #define FSL_FEATURE_PMC_HAS_LPO (0) 1292 /* @brief Has VLPx option PMC_REGSC[VLPO]. */ 1293 #define FSL_FEATURE_PMC_HAS_VLPO (0) 1294 /* @brief Has acknowledge isolation support. */ 1295 #define FSL_FEATURE_PMC_HAS_ACKISO (1) 1296 /* @brief Has Regulator In Full Performance Mode Status Bit PMC_REGSC[REGFPM]. */ 1297 #define FSL_FEATURE_PMC_HAS_REGFPM (0) 1298 /* @brief Has Regulator In Run Regulation Status Bit PMC_REGSC[REGONS]. */ 1299 #define FSL_FEATURE_PMC_HAS_REGONS (1) 1300 /* @brief Has PMC_HVDSC1. */ 1301 #define FSL_FEATURE_PMC_HAS_HVDSC1 (0) 1302 /* @brief Has PMC_PARAM. */ 1303 #define FSL_FEATURE_PMC_HAS_PARAM (0) 1304 /* @brief Has PMC_VERID. */ 1305 #define FSL_FEATURE_PMC_HAS_VERID (0) 1306 1307 /* PORT module features */ 1308 1309 /* @brief Has control lock (register bit PCR[LK]). */ 1310 #define FSL_FEATURE_PORT_HAS_PIN_CONTROL_LOCK (1) 1311 /* @brief Has open drain control (register bit PCR[ODE]). */ 1312 #define FSL_FEATURE_PORT_HAS_OPEN_DRAIN (1) 1313 /* @brief Has digital filter (registers DFER, DFCR and DFWR). */ 1314 #define FSL_FEATURE_PORT_HAS_DIGITAL_FILTER (1) 1315 /* @brief Has DMA request (register bit field PCR[IRQC] values). */ 1316 #define FSL_FEATURE_PORT_HAS_DMA_REQUEST (1) 1317 /* @brief Has pull resistor selection available. */ 1318 #define FSL_FEATURE_PORT_HAS_PULL_SELECTION (1) 1319 /* @brief Has pull resistor enable (register bit PCR[PE]). */ 1320 #define FSL_FEATURE_PORT_HAS_PULL_ENABLE (1) 1321 /* @brief Has slew rate control (register bit PCR[SRE]). */ 1322 #define FSL_FEATURE_PORT_HAS_SLEW_RATE (1) 1323 /* @brief Has passive filter (register bit field PCR[PFE]). */ 1324 #define FSL_FEATURE_PORT_HAS_PASSIVE_FILTER (1) 1325 /* @brief Has drive strength control (register bit PCR[DSE]). */ 1326 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH (1) 1327 /* @brief Has separate drive strength register (HDRVE). */ 1328 #define FSL_FEATURE_PORT_HAS_DRIVE_STRENGTH_REGISTER (0) 1329 /* @brief Has glitch filter (register IOFLT). */ 1330 #define FSL_FEATURE_PORT_HAS_GLITCH_FILTER (0) 1331 /* @brief Defines width of PCR[MUX] field. */ 1332 #define FSL_FEATURE_PORT_PCR_MUX_WIDTH (3) 1333 /* @brief Has dedicated interrupt vector. */ 1334 #define FSL_FEATURE_PORT_HAS_INTERRUPT_VECTOR (1) 1335 /* @brief Has multiple pin IRQ configuration (register GICLR and GICHR). */ 1336 #define FSL_FEATURE_PORT_HAS_MULTIPLE_IRQ_CONFIG (0) 1337 /* @brief Defines whether PCR[IRQC] bit-field has flag states. */ 1338 #define FSL_FEATURE_PORT_HAS_IRQC_FLAG (0) 1339 /* @brief Defines whether PCR[IRQC] bit-field has trigger states. */ 1340 #define FSL_FEATURE_PORT_HAS_IRQC_TRIGGER (0) 1341 1342 /* RCM module features */ 1343 1344 /* @brief Has Loss-of-Lock Reset support. */ 1345 #define FSL_FEATURE_RCM_HAS_LOL (1) 1346 /* @brief Has Loss-of-Clock Reset support. */ 1347 #define FSL_FEATURE_RCM_HAS_LOC (1) 1348 /* @brief Has JTAG generated Reset support. */ 1349 #define FSL_FEATURE_RCM_HAS_JTAG (1) 1350 /* @brief Has EzPort generated Reset support. */ 1351 #define FSL_FEATURE_RCM_HAS_EZPORT (1) 1352 /* @brief Has bit-field indicating EZP_MS_B pin state during last reset. */ 1353 #define FSL_FEATURE_RCM_HAS_EZPMS (1) 1354 /* @brief Has boot ROM configuration, MR[BOOTROM], FM[FORCEROM] */ 1355 #define FSL_FEATURE_RCM_HAS_BOOTROM (0) 1356 /* @brief Has sticky system reset status register RCM_SSRS0 and RCM_SSRS1. */ 1357 #define FSL_FEATURE_RCM_HAS_SSRS (0) 1358 /* @brief Has Version ID Register (RCM_VERID). */ 1359 #define FSL_FEATURE_RCM_HAS_VERID (0) 1360 /* @brief Has Parameter Register (RCM_PARAM). */ 1361 #define FSL_FEATURE_RCM_HAS_PARAM (0) 1362 /* @brief Has Reset Interrupt Enable Register RCM_SRIE. */ 1363 #define FSL_FEATURE_RCM_HAS_SRIE (0) 1364 /* @brief Width of registers of the RCM. */ 1365 #define FSL_FEATURE_RCM_REG_WIDTH (8) 1366 /* @brief Has Core 1 generated Reset support RCM_SRS[CORE1] */ 1367 #define FSL_FEATURE_RCM_HAS_CORE1 (0) 1368 /* @brief Has MDM-AP system reset support RCM_SRS1[MDM_AP] */ 1369 #define FSL_FEATURE_RCM_HAS_MDM_AP (1) 1370 /* @brief Has wakeup reset feature. Register bit SRS[WAKEUP]. */ 1371 #define FSL_FEATURE_RCM_HAS_WAKEUP (1) 1372 1373 /* RTC module features */ 1374 1375 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 1376 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) 1377 /* @brief Has wakeup pin. */ 1378 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1379 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1380 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1381 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1382 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1383 /* @brief Has read/write access control (registers WAR and RAR). */ 1384 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1385 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1386 #define FSL_FEATURE_RTC_HAS_SECURITY (1) 1387 /* @brief Has RTC_CLKIN available. */ 1388 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1389 /* @brief Has prescaler adjust for LPO. */ 1390 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1391 /* @brief Has Clock Pin Enable field. */ 1392 #define FSL_FEATURE_RTC_HAS_CPE (0) 1393 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1394 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1395 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1396 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1397 /* @brief Has Tamper Interrupt Register (register TIR). */ 1398 #define FSL_FEATURE_RTC_HAS_TIR (0) 1399 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1400 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1401 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1402 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1403 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1404 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1405 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1406 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1407 /* @brief Has Tamper Detect Register (register TDR). */ 1408 #define FSL_FEATURE_RTC_HAS_TDR (0) 1409 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1410 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1411 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1412 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1413 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1414 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1415 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1416 #define FSL_FEATURE_RTC_HAS_TTSR (0) 1417 /* @brief Has Pin Configuration Register (register PCR). */ 1418 #define FSL_FEATURE_RTC_HAS_PCR (0) 1419 #elif defined(CPU_MK64FN1M0VMD12) || defined(CPU_MK64FX512VMD12) 1420 /* @brief Has wakeup pin. */ 1421 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN (1) 1422 /* @brief Has wakeup pin selection (bit field CR[WPS]). */ 1423 #define FSL_FEATURE_RTC_HAS_WAKEUP_PIN_SELECTION (1) 1424 /* @brief Has low power features (registers MER, MCLR and MCHR). */ 1425 #define FSL_FEATURE_RTC_HAS_MONOTONIC (0) 1426 /* @brief Has read/write access control (registers WAR and RAR). */ 1427 #define FSL_FEATURE_RTC_HAS_ACCESS_CONTROL (1) 1428 /* @brief Has security features (registers TTSR, MER, MCLR and MCHR). */ 1429 #define FSL_FEATURE_RTC_HAS_SECURITY (0) 1430 /* @brief Has RTC_CLKIN available. */ 1431 #define FSL_FEATURE_RTC_HAS_RTC_CLKIN (0) 1432 /* @brief Has prescaler adjust for LPO. */ 1433 #define FSL_FEATURE_RTC_HAS_LPO_ADJUST (0) 1434 /* @brief Has Clock Pin Enable field. */ 1435 #define FSL_FEATURE_RTC_HAS_CPE (0) 1436 /* @brief Has Timer Seconds Interrupt Configuration field. */ 1437 #define FSL_FEATURE_RTC_HAS_TSIC (0) 1438 /* @brief Has OSC capacitor setting RTC_CR[SC2P ~ SC16P] */ 1439 #define FSL_FEATURE_RTC_HAS_OSC_SCXP (1) 1440 /* @brief Has Tamper Interrupt Register (register TIR). */ 1441 #define FSL_FEATURE_RTC_HAS_TIR (0) 1442 /* @brief Has Tamper Pin Interrupt Enable (bitfield TIR[TPIE]). */ 1443 #define FSL_FEATURE_RTC_HAS_TIR_TPIE (0) 1444 /* @brief Has Security Interrupt Enable (bitfield TIR[SIE]). */ 1445 #define FSL_FEATURE_RTC_HAS_TIR_SIE (0) 1446 /* @brief Has Loss of Clock Interrupt Enable (bitfield TIR[LCIE]). */ 1447 #define FSL_FEATURE_RTC_HAS_TIR_LCIE (0) 1448 /* @brief Has Tamper Interrupt Detect Flag (bitfield SR[TIDF]). */ 1449 #define FSL_FEATURE_RTC_HAS_SR_TIDF (0) 1450 /* @brief Has Tamper Detect Register (register TDR). */ 1451 #define FSL_FEATURE_RTC_HAS_TDR (0) 1452 /* @brief Has Tamper Pin Flag (bitfield TDR[TPF]). */ 1453 #define FSL_FEATURE_RTC_HAS_TDR_TPF (0) 1454 /* @brief Has Security Tamper Flag (bitfield TDR[STF]). */ 1455 #define FSL_FEATURE_RTC_HAS_TDR_STF (0) 1456 /* @brief Has Loss of Clock Tamper Flag (bitfield TDR[LCTF]). */ 1457 #define FSL_FEATURE_RTC_HAS_TDR_LCTF (0) 1458 /* @brief Has Tamper Time Seconds Register (register TTSR). */ 1459 #define FSL_FEATURE_RTC_HAS_TTSR (0) 1460 /* @brief Has Pin Configuration Register (register PCR). */ 1461 #define FSL_FEATURE_RTC_HAS_PCR (0) 1462 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FN1M0VLQ12) || \ 1463 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLL12) || defined(CPU_MK64FX512VLQ12) */ 1464 1465 /* SDHC module features */ 1466 1467 /* @brief Has external DMA support (register bit VENDOR[EXTDMAEN]). */ 1468 #define FSL_FEATURE_SDHC_HAS_EXTERNAL_DMA_SUPPORT (1) 1469 /* @brief Has support of 3.0V voltage (register bit HTCAPBLT[VS30]). */ 1470 #define FSL_FEATURE_SDHC_HAS_V300_SUPPORT (0) 1471 /* @brief Has support of 1.8V voltage (register bit HTCAPBLT[VS18]). */ 1472 #define FSL_FEATURE_SDHC_HAS_V180_SUPPORT (0) 1473 1474 /* SIM module features */ 1475 1476 /* @brief Has USB FS divider. */ 1477 #define FSL_FEATURE_SIM_USBFS_USE_SPECIAL_DIVIDER (0) 1478 /* @brief Is PLL clock divided by 2 before MCG PLL/FLL clock selection. */ 1479 #define FSL_FEATURE_SIM_PLLCLK_USE_SPECIAL_DIVIDER (0) 1480 /* @brief Has RAM size specification (register bit field SOPT1[RAMSIZE]). */ 1481 #define FSL_FEATURE_SIM_OPT_HAS_RAMSIZE (1) 1482 /* @brief Has 32k oscillator clock output (register bit SOPT1[OSC32KOUT]). */ 1483 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_OUT (0) 1484 /* @brief Has 32k oscillator clock selection (register bit field SOPT1[OSC32KSEL]). */ 1485 #define FSL_FEATURE_SIM_OPT_HAS_OSC32K_SELECTION (1) 1486 /* @brief 32k oscillator clock selection width (width of register bit field SOPT1[OSC32KSEL]). */ 1487 #define FSL_FEATURE_SIM_OPT_OSC32K_SELECTION_WIDTH (2) 1488 /* @brief Has RTC clock output selection (register bit SOPT2[RTCCLKOUTSEL]). */ 1489 #define FSL_FEATURE_SIM_OPT_HAS_RTC_CLOCK_OUT_SELECTION (1) 1490 /* @brief Has USB voltage regulator (register bits SOPT1[USBVSTBY], SOPT1[USBSSTBY], SOPT1[USBREGEN], SOPT1CFG[URWE], SOPT1CFG[UVSWE], SOPT1CFG[USSWE]). */ 1491 #define FSL_FEATURE_SIM_OPT_HAS_USB_VOLTAGE_REGULATOR (1) 1492 /* @brief USB has integrated PHY (register bits USBPHYCTL[USBVREGSEL], USBPHYCTL[USBVREGPD], USBPHYCTL[USB3VOUTTRG], USBPHYCTL[USBDISILIM], SOPT2[USBSLSRC], SOPT2[USBREGEN]). */ 1493 #define FSL_FEATURE_SIM_OPT_HAS_USB_PHY (0) 1494 /* @brief Has PTD7 pad drive strength control (register bit SOPT2[PTD7PAD]). */ 1495 #define FSL_FEATURE_SIM_OPT_HAS_PTD7PAD (1) 1496 /* @brief Has FlexBus security level selection (register bit SOPT2[FBSL]). */ 1497 #define FSL_FEATURE_SIM_OPT_HAS_FBSL (1) 1498 /* @brief Has number of FlexBus hold cycle before FlexBus can release bus (register bit SOPT6[PCR]). */ 1499 #define FSL_FEATURE_SIM_OPT_HAS_PCR (0) 1500 /* @brief Has number of NFC hold cycle in case of FlexBus request (register bit SOPT6[MCC]). */ 1501 #define FSL_FEATURE_SIM_OPT_HAS_MCC (0) 1502 /* @brief Has UART open drain enable (register bits UARTnODE, where n is a number, in register SOPT5). */ 1503 #define FSL_FEATURE_SIM_OPT_HAS_ODE (0) 1504 /* @brief Number of LPUART modules (number of register bits LPUARTn, where n is a number, in register SCGC5). */ 1505 #define FSL_FEATURE_SIM_OPT_LPUART_COUNT (0) 1506 /* @brief Number of UART modules (number of register bits UARTn, where n is a number, in register SCGC4). */ 1507 #define FSL_FEATURE_SIM_OPT_UART_COUNT (4) 1508 /* @brief Has UART0 open drain enable (register bit SOPT5[UART0ODE]). */ 1509 #define FSL_FEATURE_SIM_OPT_HAS_UART0_ODE (0) 1510 /* @brief Has UART1 open drain enable (register bit SOPT5[UART1ODE]). */ 1511 #define FSL_FEATURE_SIM_OPT_HAS_UART1_ODE (0) 1512 /* @brief Has UART2 open drain enable (register bit SOPT5[UART2ODE]). */ 1513 #define FSL_FEATURE_SIM_OPT_HAS_UART2_ODE (0) 1514 /* @brief Has LPUART0 open drain enable (register bit SOPT5[LPUART0ODE]). */ 1515 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_ODE (0) 1516 /* @brief Has LPUART1 open drain enable (register bit SOPT5[LPUART1ODE]). */ 1517 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_ODE (0) 1518 /* @brief Has CMT/UART pad drive strength control (register bit SOPT2[CMTUARTPAD]). */ 1519 #define FSL_FEATURE_SIM_OPT_HAS_CMTUARTPAD (0) 1520 /* @brief Has LPUART0 transmit data source selection (register bit SOPT5[LPUART0TXSRC]). */ 1521 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_TX_SRC (0) 1522 /* @brief Has LPUART0 receive data source selection (register bit SOPT5[LPUART0RXSRC]). */ 1523 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0_RX_SRC (0) 1524 /* @brief Has LPUART1 transmit data source selection (register bit SOPT5[LPUART1TXSRC]). */ 1525 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_TX_SRC (0) 1526 /* @brief Has LPUART1 receive data source selection (register bit SOPT5[LPUART1RXSRC]). */ 1527 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1_RX_SRC (0) 1528 /* @brief Has UART0 transmit data source selection (register bit SOPT5[UART0TXSRC]). */ 1529 #define FSL_FEATURE_SIM_OPT_HAS_UART0_TX_SRC (1) 1530 /* @brief UART0 transmit data source selection width (width of register bit SOPT5[UART0TXSRC]). */ 1531 #define FSL_FEATURE_SIM_OPT_UART0_TX_SRC_WIDTH (2) 1532 /* @brief Has UART0 receive data source selection (register bit SOPT5[UART0RXSRC]). */ 1533 #define FSL_FEATURE_SIM_OPT_HAS_UART0_RX_SRC (1) 1534 /* @brief UART0 receive data source selection width (width of register bit SOPT5[UART0RXSRC]). */ 1535 #define FSL_FEATURE_SIM_OPT_UART0_RX_SRC_WIDTH (2) 1536 /* @brief Has UART1 transmit data source selection (register bit SOPT5[UART1TXSRC]). */ 1537 #define FSL_FEATURE_SIM_OPT_HAS_UART1_TX_SRC (1) 1538 /* @brief Has UART1 receive data source selection (register bit SOPT5[UART1RXSRC]). */ 1539 #define FSL_FEATURE_SIM_OPT_HAS_UART1_RX_SRC (1) 1540 /* @brief UART1 receive data source selection width (width of register bit SOPT5[UART1RXSRC]). */ 1541 #define FSL_FEATURE_SIM_OPT_UART1_RX_SRC_WIDTH (2) 1542 /* @brief Has FTM module(s) configuration. */ 1543 #define FSL_FEATURE_SIM_OPT_HAS_FTM (1) 1544 /* @brief Number of FTM modules. */ 1545 #define FSL_FEATURE_SIM_OPT_FTM_COUNT (4) 1546 /* @brief Number of FTM triggers with selectable source. */ 1547 #define FSL_FEATURE_SIM_OPT_FTM_TRIGGER_COUNT (2) 1548 /* @brief Has FTM0 triggers source selection (register bits SOPT4[FTM0TRGnSRC], where n is a number). */ 1549 #define FSL_FEATURE_SIM_OPT_HAS_FTM0_TRIGGER (1) 1550 /* @brief Has FTM3 triggers source selection (register bits SOPT4[FTM3TRGnSRC], where n is a number). */ 1551 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_TRIGGER (1) 1552 /* @brief Has FTM1 channel 0 input capture source selection (register bit SOPT4[FTM1CH0SRC]). */ 1553 #define FSL_FEATURE_SIM_OPT_HAS_FTM1_CHANNELS (1) 1554 /* @brief Has FTM2 channel 0 input capture source selection (register bit SOPT4[FTM2CH0SRC]). */ 1555 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNELS (1) 1556 /* @brief Has FTM3 channel 0 input capture source selection (register bit SOPT4[FTM3CH0SRC]). */ 1557 #define FSL_FEATURE_SIM_OPT_HAS_FTM3_CHANNELS (0) 1558 /* @brief Has FTM2 channel 1 input capture source selection (register bit SOPT4[FTM2CH1SRC]). */ 1559 #define FSL_FEATURE_SIM_OPT_HAS_FTM2_CHANNEL1 (0) 1560 /* @brief Number of configurable FTM0 fault detection input (number of register bits SOPT4[FTM0FLTn], where n is a number starting from zero). */ 1561 #define FSL_FEATURE_SIM_OPT_FTM0_FAULT_COUNT (3) 1562 /* @brief Number of configurable FTM1 fault detection input (number of register bits SOPT4[FTM1FLTn], where n is a number starting from zero). */ 1563 #define FSL_FEATURE_SIM_OPT_FTM1_FAULT_COUNT (1) 1564 /* @brief Number of configurable FTM2 fault detection input (number of register bits SOPT4[FTM2FLTn], where n is a number starting from zero). */ 1565 #define FSL_FEATURE_SIM_OPT_FTM2_FAULT_COUNT (1) 1566 /* @brief Number of configurable FTM3 fault detection input (number of register bits SOPT4[FTM3FLTn], where n is a number starting from zero). */ 1567 #define FSL_FEATURE_SIM_OPT_FTM3_FAULT_COUNT (1) 1568 /* @brief Has FTM hardware trigger 0 software synchronization (register bit SOPT8[FTMnSYNCBIT], where n is a module instance index). */ 1569 #define FSL_FEATURE_SIM_OPT_HAS_FTM_TRIGGER_SYNC (0) 1570 /* @brief Has FTM channels output source selection (register bit SOPT8[FTMxOCHnSRC], where x is a module instance index and n is a channel index). */ 1571 #define FSL_FEATURE_SIM_OPT_HAS_FTM_CHANNELS_OUTPUT_SRC (0) 1572 /* @brief Has TPM module(s) configuration. */ 1573 #define FSL_FEATURE_SIM_OPT_HAS_TPM (0) 1574 /* @brief The highest TPM module index. */ 1575 #define FSL_FEATURE_SIM_OPT_MAX_TPM_INDEX (0) 1576 /* @brief Has TPM module with index 0. */ 1577 #define FSL_FEATURE_SIM_OPT_HAS_TPM0 (0) 1578 /* @brief Has TPM0 clock selection (register bit field SOPT4[TPM0CLKSEL]). */ 1579 #define FSL_FEATURE_SIM_OPT_HAS_TPM0_CLK_SEL (0) 1580 /* @brief Is TPM channels configuration in the SOPT4 (not SOPT9) register (register bits TPMnCH0SRC, TPMnCLKSEL, where n is a module instance index). */ 1581 #define FSL_FEATURE_SIM_OPT_HAS_TPM_CHANNELS_CONFIG_IN_SOPT4_REG (0) 1582 /* @brief Has TPM1 channel 0 input capture source selection (register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1583 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CH0_SRC_SELECTION (0) 1584 /* @brief Has TPM1 clock selection (register bit field SOPT4[TPM1CLKSEL]). */ 1585 #define FSL_FEATURE_SIM_OPT_HAS_TPM1_CLK_SEL (0) 1586 /* @brief TPM1 channel 0 input capture source selection width (width of register bit field SOPT4[TPM1CH0SRC] or SOPT9[TPM1CH0SRC]). */ 1587 #define FSL_FEATURE_SIM_OPT_TPM1_CH0_SRC_SELECTION_WIDTH (0) 1588 /* @brief Has TPM2 channel 0 input capture source selection (register bit field SOPT4[TPM2CH0SRC]). */ 1589 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CH0_SRC_SELECTION (0) 1590 /* @brief Has TPM2 clock selection (register bit field SOPT4[TPM2CLKSEL]). */ 1591 #define FSL_FEATURE_SIM_OPT_HAS_TPM2_CLK_SEL (0) 1592 /* @brief Has PLL/FLL clock selection (register bit field SOPT2[PLLFLLSEL]). */ 1593 #define FSL_FEATURE_SIM_OPT_HAS_PLL_FLL_SELECTION (1) 1594 /* @brief PLL/FLL clock selection width (width of register bit field SOPT2[PLLFLLSEL]). */ 1595 #define FSL_FEATURE_SIM_OPT_PLL_FLL_SELECTION_WIDTH (1) 1596 /* @brief Has NFC clock source selection (register bit SOPT2[NFCSRC]). */ 1597 #define FSL_FEATURE_SIM_OPT_HAS_NFCSRC (0) 1598 /* @brief Has eSDHC clock source selection (register bit SOPT2[ESDHCSRC]). */ 1599 #define FSL_FEATURE_SIM_OPT_HAS_ESDHCSRC (0) 1600 /* @brief Has SDHC clock source selection (register bit SOPT2[SDHCSRC]). */ 1601 #define FSL_FEATURE_SIM_OPT_HAS_SDHCSRC (1) 1602 /* @brief Has LCDC clock source selection (register bits SOPT2[LCDCSRC], SOPT2[LCDC_CLKSEL]). */ 1603 #define FSL_FEATURE_SIM_OPT_HAS_LCDCSRC (0) 1604 /* @brief Has ENET timestamp clock source selection (register bit SOPT2[TIMESRC]). */ 1605 #define FSL_FEATURE_SIM_OPT_HAS_TIMESRC (1) 1606 /* @brief Has ENET RMII clock source selection (register bit SOPT2[RMIISRC]). */ 1607 #define FSL_FEATURE_SIM_OPT_HAS_RMIISRC (1) 1608 /* @brief Has USB clock source selection (register bit SOPT2[USBSRC]). */ 1609 #define FSL_FEATURE_SIM_OPT_HAS_USBSRC (1) 1610 /* @brief Has USB FS clock source selection (register bit SOPT2[USBFSRC]). */ 1611 #define FSL_FEATURE_SIM_OPT_HAS_USBFSRC (0) 1612 /* @brief Has USB HS clock source selection (register bit SOPT2[USBHSRC]). */ 1613 #define FSL_FEATURE_SIM_OPT_HAS_USBHSRC (0) 1614 /* @brief Has LPUART clock source selection (register bit SOPT2[LPUARTSRC]). */ 1615 #define FSL_FEATURE_SIM_OPT_HAS_LPUARTSRC (0) 1616 /* @brief Has LPUART0 clock source selection (register bit SOPT2[LPUART0SRC]). */ 1617 #define FSL_FEATURE_SIM_OPT_HAS_LPUART0SRC (0) 1618 /* @brief Has LPUART1 clock source selection (register bit SOPT2[LPUART1SRC]). */ 1619 #define FSL_FEATURE_SIM_OPT_HAS_LPUART1SRC (0) 1620 /* @brief Has FLEXIOSRC clock source selection (register bit SOPT2[FLEXIOSRC]). */ 1621 #define FSL_FEATURE_SIM_OPT_HAS_FLEXIOSRC (0) 1622 /* @brief Has UART0 clock source selection (register bit SOPT2[UART0SRC]). */ 1623 #define FSL_FEATURE_SIM_OPT_HAS_UART0SRC (0) 1624 /* @brief Has TPM clock source selection (register bit SOPT2[TPMSRC]). */ 1625 #define FSL_FEATURE_SIM_OPT_HAS_TPMSRC (0) 1626 /* @brief Has debug trace clock selection (register bit SOPT2[TRACECLKSEL]). */ 1627 #define FSL_FEATURE_SIM_OPT_HAS_TRACE_CLKSEL (1) 1628 /* @brief Number of ADC modules (register bits SOPT7[ADCnTRGSEL], SOPT7[ADCnPRETRGSEL], SOPT7[ADCnALTTRGSEL], where n is a module instance index). */ 1629 #define FSL_FEATURE_SIM_OPT_ADC_COUNT (2) 1630 /* @brief ADC0 alternate trigger enable width (width of bit field ADC0ALTTRGEN of register SOPT7). */ 1631 #define FSL_FEATURE_SIM_OPT_ADC0ALTTRGEN_WIDTH (1) 1632 /* @brief ADC1 alternate trigger enable width (width of bit field ADC1ALTTRGEN of register SOPT7). */ 1633 #define FSL_FEATURE_SIM_OPT_ADC1ALTTRGEN_WIDTH (1) 1634 /* @brief ADC2 alternate trigger enable width (width of bit field ADC2ALTTRGEN of register SOPT7). */ 1635 #define FSL_FEATURE_SIM_OPT_ADC2ALTTRGEN_WIDTH (0) 1636 /* @brief ADC3 alternate trigger enable width (width of bit field ADC3ALTTRGEN of register SOPT7). */ 1637 #define FSL_FEATURE_SIM_OPT_ADC3ALTTRGEN_WIDTH (0) 1638 /* @brief HSADC0 converter A alternate trigger enable width (width of bit field HSADC0AALTTRGEN of register SOPT7). */ 1639 #define FSL_FEATURE_SIM_OPT_HSADC0AALTTRGEN_WIDTH (0) 1640 /* @brief HSADC1 converter A alternate trigger enable width (width of bit field HSADC1AALTTRGEN of register SOPT7). */ 1641 #define FSL_FEATURE_SIM_OPT_HSADC1AALTTRGEN_WIDTH (0) 1642 /* @brief ADC converter A alternate trigger enable width (width of bit field ADCAALTTRGEN of register SOPT7). */ 1643 #define FSL_FEATURE_SIM_OPT_ADCAALTTRGEN_WIDTH (0) 1644 /* @brief HSADC0 converter B alternate trigger enable width (width of bit field HSADC0BALTTRGEN of register SOPT7). */ 1645 #define FSL_FEATURE_SIM_OPT_HSADC0BALTTRGEN_WIDTH (0) 1646 /* @brief HSADC1 converter B alternate trigger enable width (width of bit field HSADC1BALTTRGEN of register SOPT7). */ 1647 #define FSL_FEATURE_SIM_OPT_HSADC1BALTTRGEN_WIDTH (0) 1648 /* @brief ADC converter B alternate trigger enable width (width of bit field ADCBALTTRGEN of register SOPT7). */ 1649 #define FSL_FEATURE_SIM_OPT_ADCBALTTRGEN_WIDTH (0) 1650 /* @brief Has clock 2 output divider (register bit field CLKDIV1[OUTDIV2]). */ 1651 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV2 (1) 1652 /* @brief Has clock 3 output divider (register bit field CLKDIV1[OUTDIV3]). */ 1653 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV3 (1) 1654 /* @brief Has clock 4 output divider (register bit field CLKDIV1[OUTDIV4]). */ 1655 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV4 (1) 1656 /* @brief Clock 4 output divider width (width of register bit field CLKDIV1[OUTDIV4]). */ 1657 #define FSL_FEATURE_SIM_DIVIDER_OUTDIV4_WIDTH (4) 1658 /* @brief Has clock 5 output divider (register bit field CLKDIV1[OUTDIV5]). */ 1659 #define FSL_FEATURE_SIM_DIVIDER_HAS_OUTDIV5 (0) 1660 /* @brief Has USB clock divider (register bit field CLKDIV2[USBDIV] and CLKDIV2[USBFRAC]). */ 1661 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBDIV (1) 1662 /* @brief Has USB FS clock divider (register bit field CLKDIV2[USBFSDIV] and CLKDIV2[USBFSFRAC]). */ 1663 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBFSDIV (0) 1664 /* @brief Has USB HS clock divider (register bit field CLKDIV2[USBHSDIV] and CLKDIV2[USBHSFRAC]). */ 1665 #define FSL_FEATURE_SIM_DIVIDER_HAS_USBHSDIV (0) 1666 /* @brief Has PLL/FLL clock divider (register bit field CLKDIV3[PLLFLLDIV] and CLKDIV3[PLLFLLFRAC]). */ 1667 #define FSL_FEATURE_SIM_DIVIDER_HAS_PLLFLLDIV (0) 1668 /* @brief Has LCDC clock divider (register bit field CLKDIV3[LCDCDIV] and CLKDIV3[LCDCFRAC]). */ 1669 #define FSL_FEATURE_SIM_DIVIDER_HAS_LCDCDIV (0) 1670 /* @brief Has trace clock divider (register bit field CLKDIV4[TRACEDIV] and CLKDIV4[TRACEFRAC]). */ 1671 #define FSL_FEATURE_SIM_DIVIDER_HAS_TRACEDIV (0) 1672 /* @brief Has NFC clock divider (register bit field CLKDIV4[NFCDIV] and CLKDIV4[NFCFRAC]). */ 1673 #define FSL_FEATURE_SIM_DIVIDER_HAS_NFCDIV (0) 1674 /* @brief Has Kinetis family ID (register bit field SDID[FAMILYID]). */ 1675 #define FSL_FEATURE_SIM_SDID_HAS_FAMILYID (1) 1676 /* @brief Has Kinetis family ID (register bit field SDID[FAMID]). */ 1677 #define FSL_FEATURE_SIM_SDID_HAS_FAMID (1) 1678 /* @brief Has Kinetis sub-family ID (register bit field SDID[SUBFAMID]). */ 1679 #define FSL_FEATURE_SIM_SDID_HAS_SUBFAMID (1) 1680 /* @brief Has Kinetis series ID (register bit field SDID[SERIESID]). */ 1681 #define FSL_FEATURE_SIM_SDID_HAS_SERIESID (1) 1682 /* @brief Has device die ID (register bit field SDID[DIEID]). */ 1683 #define FSL_FEATURE_SIM_SDID_HAS_DIEID (1) 1684 /* @brief Has system SRAM size specifier (register bit field SDID[SRAMSIZE]). */ 1685 #define FSL_FEATURE_SIM_SDID_HAS_SRAMSIZE (0) 1686 /* @brief Has flash mode (register bit FCFG1[FLASHDOZE]). */ 1687 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDOZE (1) 1688 /* @brief Has flash disable (register bit FCFG1[FLASHDIS]). */ 1689 #define FSL_FEATURE_SIM_FCFG_HAS_FLASHDIS (1) 1690 /* @brief Has FTFE disable (register bit FCFG1[FTFDIS]). */ 1691 #define FSL_FEATURE_SIM_FCFG_HAS_FTFDIS (0) 1692 /* @brief Has FlexNVM size specifier (register bit field FCFG1[NVMSIZE]). */ 1693 #define FSL_FEATURE_SIM_FCFG_HAS_NVMSIZE (1) 1694 /* @brief Has EEPROM size specifier (register bit field FCFG1[EESIZE]). */ 1695 #define FSL_FEATURE_SIM_FCFG_HAS_EESIZE (1) 1696 /* @brief Has FlexNVM partition (register bit field FCFG1[DEPART]). */ 1697 #define FSL_FEATURE_SIM_FCFG_HAS_DEPART (1) 1698 /* @brief Maximum flash address block 0 address specifier (register bit field FCFG2[MAXADDR0]). */ 1699 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR0 (1) 1700 /* @brief Maximum flash address block 1 address specifier (register bit field FCFG2[MAXADDR1]). */ 1701 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR1 (1) 1702 /* @brief Maximum flash address block 0 or 1 address specifier (register bit field FCFG2[MAXADDR01]). */ 1703 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR01 (0) 1704 /* @brief Maximum flash address block 2 or 3 address specifier (register bit field FCFG2[MAXADDR23]). */ 1705 #define FSL_FEATURE_SIM_FCFG_HAS_MAXADDR23 (0) 1706 /* @brief Has program flash availability specifier (register bit FCFG2[PFLSH]). */ 1707 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH (1) 1708 /* @brief Has program flash swapping (register bit FCFG2[SWAPPFLSH]). */ 1709 #define FSL_FEATURE_SIM_FCFG_HAS_PFLSH_SWAP (0) 1710 /* @brief Has miscellanious control register (register MCR). */ 1711 #define FSL_FEATURE_SIM_HAS_MISC_CONTROLS (0) 1712 /* @brief Has COP watchdog (registers COPC and SRVCOP). */ 1713 #define FSL_FEATURE_SIM_HAS_COP_WATCHDOG (0) 1714 /* @brief Has COP watchdog stop (register bits COPC[COPSTPEN], COPC[COPDBGEN] and COPC[COPCLKSEL]). */ 1715 #define FSL_FEATURE_SIM_HAS_COP_STOP (0) 1716 /* @brief Has LLWU clock gate bit (e.g SIM_SCGC4). */ 1717 #define FSL_FEATURE_SIM_HAS_SCGC_LLWU (0) 1718 /* @brief Has UIDH registers. */ 1719 #define FSL_FEATURE_SIM_HAS_UIDH (1) 1720 /* @brief Has UIDM registers. */ 1721 #define FSL_FEATURE_SIM_HAS_UIDM (0) 1722 1723 /* SMC module features */ 1724 1725 /* @brief Has partial stop option (register bit STOPCTRL[PSTOPO]). */ 1726 #define FSL_FEATURE_SMC_HAS_PSTOPO (0) 1727 /* @brief Has LPO power option (register bit STOPCTRL[LPOPO]). */ 1728 #define FSL_FEATURE_SMC_HAS_LPOPO (0) 1729 /* @brief Has POR power option (register bit STOPCTRL[PORPO] or VLLSCTRL[PORPO]). */ 1730 #define FSL_FEATURE_SMC_HAS_PORPO (1) 1731 /* @brief Has low power wakeup on interrupt (register bit PMCTRL[LPWUI]). */ 1732 #define FSL_FEATURE_SMC_HAS_LPWUI (1) 1733 /* @brief Has LLS or VLLS mode control (register bit STOPCTRL[LLSM]). */ 1734 #define FSL_FEATURE_SMC_HAS_LLS_SUBMODE (0) 1735 /* @brief Has VLLS mode control (register bit VLLSCTRL[VLLSM]). */ 1736 #define FSL_FEATURE_SMC_USE_VLLSCTRL_REG (1) 1737 /* @brief Has VLLS mode control (register bit STOPCTRL[VLLSM]). */ 1738 #define FSL_FEATURE_SMC_USE_STOPCTRL_VLLSM (0) 1739 /* @brief Has RAM partition 2 power option (register bit STOPCTRL[RAM2PO]). */ 1740 #define FSL_FEATURE_SMC_HAS_RAM2_POWER_OPTION (0) 1741 /* @brief Has high speed run mode (register bit PMPROT[AHSRUN]). */ 1742 #define FSL_FEATURE_SMC_HAS_HIGH_SPEED_RUN_MODE (0) 1743 /* @brief Has low leakage stop mode (register bit PMPROT[ALLS]). */ 1744 #define FSL_FEATURE_SMC_HAS_LOW_LEAKAGE_STOP_MODE (1) 1745 /* @brief Has very low leakage stop mode (register bit PMPROT[AVLLS]). */ 1746 #define FSL_FEATURE_SMC_HAS_VERY_LOW_LEAKAGE_STOP_MODE (1) 1747 /* @brief Has stop submode. */ 1748 #define FSL_FEATURE_SMC_HAS_SUB_STOP_MODE (1) 1749 /* @brief Has stop submode 0(VLLS0). */ 1750 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE0 (1) 1751 /* @brief Has stop submode 1(VLLS1). */ 1752 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE1 (1) 1753 /* @brief Has stop submode 2(VLLS2). */ 1754 #define FSL_FEATURE_SMC_HAS_STOP_SUBMODE2 (1) 1755 /* @brief Has SMC_PARAM. */ 1756 #define FSL_FEATURE_SMC_HAS_PARAM (0) 1757 /* @brief Has SMC_VERID. */ 1758 #define FSL_FEATURE_SMC_HAS_VERID (0) 1759 /* @brief Has stop abort flag (register bit PMCTRL[STOPA]). */ 1760 #define FSL_FEATURE_SMC_HAS_PMCTRL_STOPA (1) 1761 /* @brief Has tamper reset (register bit SRS[TAMPER]). */ 1762 #define FSL_FEATURE_SMC_HAS_SRS_TAMPER (0) 1763 /* @brief Has security violation reset (register bit SRS[SECVIO]). */ 1764 #define FSL_FEATURE_SMC_HAS_SRS_SECVIO (0) 1765 /* @brief Width of SMC registers. */ 1766 #define FSL_FEATURE_SMC_REG_WIDTH (8) 1767 1768 /* DSPI module features */ 1769 1770 /* @brief Receive/transmit FIFO size in number of items. */ 1771 #define FSL_FEATURE_DSPI_FIFO_SIZEn(x) \ 1772 (((x) == SPI0) ? (4) : \ 1773 (((x) == SPI1) ? (1) : \ 1774 (((x) == SPI2) ? (1) : (-1)))) 1775 /* @brief Maximum transfer data width in bits. */ 1776 #define FSL_FEATURE_DSPI_MAX_DATA_WIDTH (16) 1777 /* @brief Maximum number of chip select pins. (Reflects the width of register bit field PUSHR[PCS].) */ 1778 #define FSL_FEATURE_DSPI_MAX_CHIP_SELECT_COUNT (6) 1779 /* @brief Number of chip select pins. */ 1780 #define FSL_FEATURE_DSPI_CHIP_SELECT_COUNT (6) 1781 /* @brief Number of CTAR registers. */ 1782 #define FSL_FEATURE_DSPI_CTAR_COUNT (2) 1783 /* @brief Has chip select strobe capability on the PCS5 pin. */ 1784 #define FSL_FEATURE_DSPI_HAS_CHIP_SELECT_STROBE (1) 1785 /* @brief Has separated TXDATA and CMD FIFOs (register SREX). */ 1786 #define FSL_FEATURE_DSPI_HAS_SEPARATE_TXDATA_CMD_FIFO (0) 1787 /* @brief Has 16-bit data transfer support. */ 1788 #define FSL_FEATURE_DSPI_16BIT_TRANSFERS (1) 1789 /* @brief Has separate DMA RX and TX requests. */ 1790 #define FSL_FEATURE_DSPI_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1791 (((x) == SPI0) ? (1) : \ 1792 (((x) == SPI1) ? (0) : \ 1793 (((x) == SPI2) ? (0) : (-1)))) 1794 1795 /* SYSMPU module features */ 1796 1797 /* @brief Specifies number of descriptors available. */ 1798 #define FSL_FEATURE_SYSMPU_DESCRIPTOR_COUNT (12) 1799 /* @brief Has process identifier support. */ 1800 #define FSL_FEATURE_SYSMPU_HAS_PROCESS_IDENTIFIER (1) 1801 /* @brief Total number of MPU slave. */ 1802 #define FSL_FEATURE_SYSMPU_SLAVE_COUNT (5) 1803 /* @brief Total number of MPU master. */ 1804 #define FSL_FEATURE_SYSMPU_MASTER_COUNT (6) 1805 1806 /* SysTick module features */ 1807 1808 /* @brief Systick has external reference clock. */ 1809 #define FSL_FEATURE_SYSTICK_HAS_EXT_REF (0) 1810 /* @brief Systick external reference clock is core clock divided by this value. */ 1811 #define FSL_FEATURE_SYSTICK_EXT_REF_CORE_DIV (0) 1812 1813 /* UART module features */ 1814 1815 #if defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ 1816 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) 1817 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1818 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1819 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1820 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1821 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1822 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1823 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1824 #define FSL_FEATURE_UART_HAS_FIFO (1) 1825 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1826 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1827 /* @brief Infrared (modulation) is supported. */ 1828 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1829 /* @brief 2 bits long stop bit is available. */ 1830 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1831 /* @brief If 10-bit mode is supported. */ 1832 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1833 /* @brief Baud rate fine adjustment is available. */ 1834 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1835 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1836 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1837 /* @brief Baud rate oversampling is available. */ 1838 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1839 /* @brief Baud rate oversampling is available. */ 1840 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1841 /* @brief Peripheral type. */ 1842 #define FSL_FEATURE_UART_IS_SCI (0) 1843 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1844 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1845 (((x) == UART0) ? (8) : \ 1846 (((x) == UART1) ? (8) : \ 1847 (((x) == UART2) ? (1) : \ 1848 (((x) == UART3) ? (1) : \ 1849 (((x) == UART4) ? (1) : \ 1850 (((x) == UART5) ? (1) : (-1))))))) 1851 /* @brief Supports two match addresses to filter incoming frames. */ 1852 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1853 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1854 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1855 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1856 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1857 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1858 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1859 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1860 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1861 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1862 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1863 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1864 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1865 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1866 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1867 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1868 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1869 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1870 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1871 /* @brief Has separate DMA RX and TX requests. */ 1872 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1873 (((x) == UART0) ? (1) : \ 1874 (((x) == UART1) ? (1) : \ 1875 (((x) == UART2) ? (1) : \ 1876 (((x) == UART3) ? (1) : \ 1877 (((x) == UART4) ? (0) : \ 1878 (((x) == UART5) ? (0) : (-1))))))) 1879 #elif defined(CPU_MK64FN1M0VLL12) || defined(CPU_MK64FX512VLL12) 1880 /* @brief Has receive FIFO overflow detection (bit field CFIFO[RXOFE]). */ 1881 #define FSL_FEATURE_UART_HAS_IRQ_EXTENDED_FUNCTIONS (1) 1882 /* @brief Has low power features (can be enabled in wait mode via register bit C1[DOZEEN] or CTRL[DOZEEN] if the registers are 32-bit wide). */ 1883 #define FSL_FEATURE_UART_HAS_LOW_POWER_UART_SUPPORT (0) 1884 /* @brief Has extended data register ED (or extra flags in the DATA register if the registers are 32-bit wide). */ 1885 #define FSL_FEATURE_UART_HAS_EXTENDED_DATA_REGISTER_FLAGS (1) 1886 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1887 #define FSL_FEATURE_UART_HAS_FIFO (1) 1888 /* @brief Hardware flow control (RTS, CTS) is supported. */ 1889 #define FSL_FEATURE_UART_HAS_MODEM_SUPPORT (1) 1890 /* @brief Infrared (modulation) is supported. */ 1891 #define FSL_FEATURE_UART_HAS_IR_SUPPORT (1) 1892 /* @brief 2 bits long stop bit is available. */ 1893 #define FSL_FEATURE_UART_HAS_STOP_BIT_CONFIG_SUPPORT (1) 1894 /* @brief If 10-bit mode is supported. */ 1895 #define FSL_FEATURE_UART_HAS_10BIT_DATA_SUPPORT (1) 1896 /* @brief Baud rate fine adjustment is available. */ 1897 #define FSL_FEATURE_UART_HAS_BAUD_RATE_FINE_ADJUST_SUPPORT (1) 1898 /* @brief Baud rate oversampling is available (has bit fields C4[OSR], C5[BOTHEDGE], C5[RESYNCDIS] or BAUD[OSR], BAUD[BOTHEDGE], BAUD[RESYNCDIS] if the registers are 32-bit wide). */ 1899 #define FSL_FEATURE_UART_HAS_BAUD_RATE_OVER_SAMPLING_SUPPORT (0) 1900 /* @brief Baud rate oversampling is available. */ 1901 #define FSL_FEATURE_UART_HAS_RX_RESYNC_SUPPORT (0) 1902 /* @brief Baud rate oversampling is available. */ 1903 #define FSL_FEATURE_UART_HAS_BOTH_EDGE_SAMPLING_SUPPORT (0) 1904 /* @brief Peripheral type. */ 1905 #define FSL_FEATURE_UART_IS_SCI (0) 1906 /* @brief Capacity (number of entries) of the transmit/receive FIFO (or zero if no FIFO is available). */ 1907 #define FSL_FEATURE_UART_FIFO_SIZEn(x) \ 1908 (((x) == UART0) ? (8) : \ 1909 (((x) == UART1) ? (8) : \ 1910 (((x) == UART2) ? (1) : \ 1911 (((x) == UART3) ? (1) : \ 1912 (((x) == UART4) ? (1) : (-1)))))) 1913 /* @brief Supports two match addresses to filter incoming frames. */ 1914 #define FSL_FEATURE_UART_HAS_ADDRESS_MATCHING (1) 1915 /* @brief Has transmitter/receiver DMA enable bits C5[TDMAE]/C5[RDMAE] (or BAUD[TDMAE]/BAUD[RDMAE] if the registers are 32-bit wide). */ 1916 #define FSL_FEATURE_UART_HAS_DMA_ENABLE (0) 1917 /* @brief Has transmitter/receiver DMA select bits C4[TDMAS]/C4[RDMAS], resp. C5[TDMAS]/C5[RDMAS] if IS_SCI = 0. */ 1918 #define FSL_FEATURE_UART_HAS_DMA_SELECT (1) 1919 /* @brief Data character bit order selection is supported (bit field S2[MSBF] or STAT[MSBF] if the registers are 32-bit wide). */ 1920 #define FSL_FEATURE_UART_HAS_BIT_ORDER_SELECT (1) 1921 /* @brief Has smart card (ISO7816 protocol) support and no improved smart card support. */ 1922 #define FSL_FEATURE_UART_HAS_SMART_CARD_SUPPORT (1) 1923 /* @brief Has improved smart card (ISO7816 protocol) support. */ 1924 #define FSL_FEATURE_UART_HAS_IMPROVED_SMART_CARD_SUPPORT (0) 1925 /* @brief Has local operation network (CEA709.1-B protocol) support. */ 1926 #define FSL_FEATURE_UART_HAS_LOCAL_OPERATION_NETWORK_SUPPORT (0) 1927 /* @brief Has 32-bit registers (BAUD, STAT, CTRL, DATA, MATCH, MODIR) instead of 8-bit (BDH, BDL, C1, S1, D, etc.). */ 1928 #define FSL_FEATURE_UART_HAS_32BIT_REGISTERS (0) 1929 /* @brief Lin break detect available (has bit BDH[LBKDIE]). */ 1930 #define FSL_FEATURE_UART_HAS_LIN_BREAK_DETECT (1) 1931 /* @brief UART stops in Wait mode available (has bit C1[UARTSWAI]). */ 1932 #define FSL_FEATURE_UART_HAS_WAIT_MODE_OPERATION (1) 1933 /* @brief Has separate DMA RX and TX requests. */ 1934 #define FSL_FEATURE_UART_HAS_SEPARATE_DMA_RX_TX_REQn(x) \ 1935 (((x) == UART0) ? (1) : \ 1936 (((x) == UART1) ? (1) : \ 1937 (((x) == UART2) ? (1) : \ 1938 (((x) == UART3) ? (1) : \ 1939 (((x) == UART4) ? (0) : (-1)))))) 1940 #endif /* defined(CPU_MK64FN1M0CAJ12) || defined(CPU_MK64FN1M0VDC12) || defined(CPU_MK64FN1M0VLQ12) || defined(CPU_MK64FN1M0VMD12) || \ 1941 defined(CPU_MK64FX512VDC12) || defined(CPU_MK64FX512VLQ12) || defined(CPU_MK64FX512VMD12) */ 1942 1943 /* USB module features */ 1944 1945 /* @brief KHCI module instance count */ 1946 #define FSL_FEATURE_USB_KHCI_COUNT (1) 1947 /* @brief HOST mode enabled */ 1948 #define FSL_FEATURE_USB_KHCI_HOST_ENABLED (1) 1949 /* @brief OTG mode enabled */ 1950 #define FSL_FEATURE_USB_KHCI_OTG_ENABLED (1) 1951 /* @brief Size of the USB dedicated RAM */ 1952 #define FSL_FEATURE_USB_KHCI_USB_RAM (0) 1953 /* @brief Has KEEP_ALIVE_CTRL register */ 1954 #define FSL_FEATURE_USB_KHCI_KEEP_ALIVE_ENABLED (0) 1955 /* @brief Has the Dynamic SOF threshold compare support */ 1956 #define FSL_FEATURE_USB_KHCI_DYNAMIC_SOF_THRESHOLD_COMPARE_ENABLED (0) 1957 /* @brief Has the VBUS detect support */ 1958 #define FSL_FEATURE_USB_KHCI_VBUS_DETECT_ENABLED (0) 1959 /* @brief Has the IRC48M module clock support */ 1960 #define FSL_FEATURE_USB_KHCI_IRC48M_MODULE_CLOCK_ENABLED (1) 1961 /* @brief Number of endpoints supported */ 1962 #define FSL_FEATURE_USB_ENDPT_COUNT (16) 1963 /* @brief Has STALL_IL/OL_DIS registers */ 1964 #define FSL_FEATURE_USB_KHCI_HAS_STALL_LOW (0) 1965 /* @brief Has STALL_IH/OH_DIS registers */ 1966 #define FSL_FEATURE_USB_KHCI_HAS_STALL_HIGH (0) 1967 1968 /* VREF module features */ 1969 1970 /* @brief Has chop oscillator (bit TRM[CHOPEN]) */ 1971 #define FSL_FEATURE_VREF_HAS_CHOP_OSC (1) 1972 /* @brief Has second order curvature compensation (bit SC[ICOMPEN]) */ 1973 #define FSL_FEATURE_VREF_HAS_COMPENSATION (1) 1974 /* @brief If high/low buffer mode supported */ 1975 #define FSL_FEATURE_VREF_MODE_LV_TYPE (1) 1976 /* @brief Module has also low reference (registers VREFL/VREFH) */ 1977 #define FSL_FEATURE_VREF_HAS_LOW_REFERENCE (0) 1978 /* @brief Has VREF_TRM4. */ 1979 #define FSL_FEATURE_VREF_HAS_TRM4 (0) 1980 1981 /* WDOG module features */ 1982 1983 /* @brief Watchdog is available. */ 1984 #define FSL_FEATURE_WDOG_HAS_WATCHDOG (1) 1985 /* @brief Has Wait mode support. */ 1986 #define FSL_FEATURE_WDOG_HAS_WAITEN (1) 1987 1988 #endif /* _MK64F12_FEATURES_H_ */ 1989 1990
