1 /*
2 ** ###################################################################
3 **     Processor:           MK27FN2M0AVMI15
4 **     Compilers:           Freescale C/C++ for Embedded ARM
5 **                          GNU C Compiler
6 **                          IAR ANSI C/C++ Compiler for ARM
7 **                          Keil ARM C/C++ Compiler
8 **                          MCUXpresso Compiler
9 **
10 **     Reference manual:    K27P169M150SF5RM, Rev. 2, Aug 2017
11 **     Version:             rev. 1.3, 2018-01-09
12 **     Build:               b181105
13 **
14 **     Abstract:
15 **         Provides a system configuration function and a global variable that
16 **         contains the system frequency. It configures the device and initializes
17 **         the oscillator (PLL) that is part of the microcontroller device.
18 **
19 **     Copyright 2016 Freescale Semiconductor, Inc.
20 **     Copyright 2016-2018 NXP
21 **     All rights reserved.
22 **
23 **     SPDX-License-Identifier: BSD-3-Clause
24 **
25 **     http:                 www.nxp.com
26 **     mail:                 support@nxp.com
27 **
28 **     Revisions:
29 **     - rev. 1.0 (2016-05-10)
30 **         Initial version
31 **     - rev. 1.1 (2016-10-20)
32 **         Update based on Rev1 RM.
33 **     - rev. 1.2 (2017-04-06)
34 **         Remove TSI.
35 **         Add ISD2FA, ISD3FA, ISD2FB and ISD3FB bits in QuadSPI0_MCR.
36 **     - rev. 1.3 (2018-01-09)
37 **         Add K28FA support.
38 **
39 ** ###################################################################
40 */
41 
42 /*!
43  * @file MK27FA15
44  * @version 1.3
45  * @date 2018-01-09
46  * @brief Device specific configuration file for MK27FA15 (implementation file)
47  *
48  * Provides a system configuration function and a global variable that contains
49  * the system frequency. It configures the device and initializes the oscillator
50  * (PLL) that is part of the microcontroller device.
51  */
52 
53 #include <stdint.h>
54 #include "fsl_device_registers.h"
55 
56 
57 
58 /* ----------------------------------------------------------------------------
59    -- Core clock
60    ---------------------------------------------------------------------------- */
61 
62 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
63 
64 /* ----------------------------------------------------------------------------
65    -- SystemInit()
66    ---------------------------------------------------------------------------- */
67 
SystemInit(void)68 void SystemInit (void) {
69 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
70   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
71 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
72 
73 #if (DISABLE_WDOG)
74   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
75   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
76   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
77   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
78   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
79   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
80                  WDOG_STCTRLH_WAITEN_MASK |
81                  WDOG_STCTRLH_STOPEN_MASK |
82                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
83                  WDOG_STCTRLH_CLKSRC_MASK |
84                  0x0100U;
85 #endif /* (DISABLE_WDOG) */
86 
87   SystemInitHook();
88 }
89 
90 /* ----------------------------------------------------------------------------
91    -- SystemCoreClockUpdate()
92    ---------------------------------------------------------------------------- */
93 
SystemCoreClockUpdate(void)94 void SystemCoreClockUpdate (void) {
95 
96   uint32_t MCGOUTClock;                /* Variable to store output clock frequency of the MCG module */
97   uint16_t Divider;
98   uint8_t tmpC7 = 0;
99 
100   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
101     /* Output of FLL or PLL is selected */
102     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
103       /* FLL is selected */
104       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
105         /* External reference clock is selected */
106         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
107         case 0x00U:
108           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
109           break;
110         case 0x01U:
111           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
112           break;
113         case 0x02U:
114         default:
115           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
116           break;
117         }
118         tmpC7 = MCG->C7;
119         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
120           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
121           case 0x38U:
122             Divider = 1536U;
123             break;
124           case 0x30U:
125             Divider = 1280U;
126             break;
127           default:
128             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
129             break;
130           }
131         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
132           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
133         }
134         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
135       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
136         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
137       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
138       /* Select correct multiplier to calculate the MCG output clock  */
139       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
140         case 0x00U:
141           MCGOUTClock *= 640U;
142           break;
143         case 0x20U:
144           MCGOUTClock *= 1280U;
145           break;
146         case 0x40U:
147           MCGOUTClock *= 1920U;
148           break;
149         case 0x60U:
150           MCGOUTClock *= 2560U;
151           break;
152         case 0x80U:
153           MCGOUTClock *= 732U;
154           break;
155         case 0xA0U:
156           MCGOUTClock *= 1464U;
157           break;
158         case 0xC0U:
159           MCGOUTClock *= 2197U;
160           break;
161         case 0xE0U:
162           MCGOUTClock *= 2929U;
163           break;
164         default:
165           MCGOUTClock *= 640U;
166           break;
167       }
168     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
169       /* PLL is selected */
170       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV_MASK) + 0x01U);
171       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
172       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV_MASK) + 16U);
173       MCGOUTClock *= Divider;          /* Calculate the VCO output clock */
174       MCGOUTClock /= 2U;               /* Calculate the MCG output clock */
175     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
176   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
177     /* Internal reference clock is selected */
178     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
179       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
180     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
181       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
182       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
183     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
184   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
185     /* External reference clock is selected */
186     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
187     case 0x00U:
188       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
189       break;
190     case 0x01U:
191       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
192       break;
193     case 0x02U:
194     default:
195       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
196       break;
197     }
198   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
199     /* Reserved value */
200     return;
201   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
202   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
203 }
204 
205 /* ----------------------------------------------------------------------------
206    -- SystemInitHook()
207    ---------------------------------------------------------------------------- */
208 
SystemInitHook(void)209 __attribute__ ((weak)) void SystemInitHook (void) {
210   /* Void implementation of the weak function. */
211 }
212