1 /* 2 * Copyright (c) 2016, Freescale Semiconductor, Inc. 3 * Copyright 2016-2020 NXP 4 * All rights reserved. 5 * 6 * 7 * SPDX-License-Identifier: BSD-3-Clause 8 */ 9 10 #ifndef _RTE_DEVICE_H 11 #define _RTE_DEVICE_H 12 13 #include "pin_mux.h" 14 15 /* USART Select. */ 16 /* Select UART0 - UART4. */ 17 /* User needs to provide the implementation of LPUARTX_GetFreq/LPUARTX_InitPins/LPUARTX_DeinitPins for the enabled 18 * LPUART instance. */ 19 #define RTE_USART0 0 20 #define RTE_USART0_DMA_EN 0 21 #define RTE_USART1 0 22 #define RTE_USART1_DMA_EN 0 23 #define RTE_USART2 0 24 #define RTE_USART2_DMA_EN 0 25 #define RTE_USART3 0 26 #define RTE_USART3_DMA_EN 0 27 #define RTE_USART4 0 28 #define RTE_USART4_DMA_EN 0 29 30 /* Select LPUART0. */ 31 #define RTE_USART5 0 32 #define RTE_USART5_DMA_EN 0 33 34 /* UART configuration. */ 35 #define USART_RX_BUFFER_LEN 64 36 #define USART0_RX_BUFFER_ENABLE 0 37 #define USART1_RX_BUFFER_ENABLE 0 38 #define USART2_RX_BUFFER_ENABLE 0 39 #define USART3_RX_BUFFER_ENABLE 0 40 #define USART4_RX_BUFFER_ENABLE 0 41 #define USART5_RX_BUFFER_ENABLE 0 42 43 #define RTE_USART0_PIN_INIT LPUART0_InitPins 44 #define RTE_USART0_PIN_DEINIT LPUART0_DeinitPins 45 #define RTE_USART0_DMA_TX_CH 0 46 #define RTE_USART0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Tx 47 #define RTE_USART0_DMA_TX_DMAMUX_BASE DMAMUX0 48 #define RTE_USART0_DMA_TX_DMA_BASE DMA0 49 #define RTE_USART0_DMA_RX_CH 1 50 #define RTE_USART0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART0Rx 51 #define RTE_USART0_DMA_RX_DMAMUX_BASE DMAMUX0 52 #define RTE_USART0_DMA_RX_DMA_BASE DMA0 53 54 #define RTE_USART1_PIN_INIT LPUART1_InitPins 55 #define RTE_USART1_PIN_DEINIT LPUART1_DeinitPins 56 #define RTE_USART1_DMA_TX_CH 0 57 #define RTE_USART1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Tx 58 #define RTE_USART1_DMA_TX_DMAMUX_BASE DMAMUX0 59 #define RTE_USART1_DMA_TX_DMA_BASE DMA0 60 #define RTE_USART1_DMA_RX_CH 1 61 #define RTE_USART1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART1Rx 62 #define RTE_USART1_DMA_RX_DMAMUX_BASE DMAMUX0 63 #define RTE_USART1_DMA_RX_DMA_BASE DMA0 64 65 #define RTE_USART2_PIN_INIT LPUART2_InitPins 66 #define RTE_USART2_PIN_DEINIT LPUART2_DeinitPins 67 #define RTE_USART2_DMA_TX_CH 0 68 #define RTE_USART2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Tx 69 #define RTE_USART2_DMA_TX_DMAMUX_BASE DMAMUX0 70 #define RTE_USART2_DMA_TX_DMA_BASE DMA0 71 #define RTE_USART2_DMA_RX_CH 1 72 #define RTE_USART2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART2Rx 73 #define RTE_USART2_DMA_RX_DMAMUX_BASE DMAMUX0 74 #define RTE_USART2_DMA_RX_DMA_BASE DMA0 75 76 #define RTE_USART3_PIN_INIT LPUART3_InitPins 77 #define RTE_USART3_PIN_DEINIT LPUART3_DeinitPins 78 #define RTE_USART3_DMA_TX_CH 0 79 #define RTE_USART3_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Tx 80 #define RTE_USART3_DMA_TX_DMAMUX_BASE DMAMUX0 81 #define RTE_USART3_DMA_TX_DMA_BASE DMA0 82 #define RTE_USART3_DMA_RX_CH 1 83 #define RTE_USART3_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART3Rx 84 #define RTE_USART3_DMA_RX_DMAMUX_BASE DMAMUX0 85 #define RTE_USART3_DMA_RX_DMA_BASE DMA0 86 87 #define RTE_USART4_PIN_INIT LPUART4_InitPins 88 #define RTE_USART4_PIN_DEINIT LPUART4_DeinitPins 89 #define RTE_USART4_DMA_TX_CH 0 90 #define RTE_USART4_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 91 #define RTE_USART4_DMA_TX_DMAMUX_BASE DMAMUX0 92 #define RTE_USART4_DMA_TX_DMA_BASE DMA0 93 #define RTE_USART4_DMA_RX_CH 1 94 #define RTE_USART4_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0UART4 95 #define RTE_USART4_DMA_RX_DMAMUX_BASE DMAMUX0 96 #define RTE_USART4_DMA_RX_DMA_BASE DMA0 97 98 #define RTE_USART5_PIN_INIT LPUART5_InitPins 99 #define RTE_USART5_PIN_DEINIT LPUART5_DeinitPins 100 #define RTE_USART5_DMA_TX_CH 0 101 #define RTE_USART5_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Tx 102 #define RTE_USART5_DMA_TX_DMAMUX_BASE DMAMUX0 103 #define RTE_USART5_DMA_TX_DMA_BASE DMA0 104 #define RTE_USART5_DMA_RX_CH 1 105 #define RTE_USART5_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0LPUART0Rx 106 #define RTE_USART5_DMA_RX_DMAMUX_BASE DMAMUX0 107 #define RTE_USART5_DMA_RX_DMA_BASE DMA0 108 109 /* I2C Select, I2C0 - I2C3. */ 110 /* User needs to provide the implementation of I2CX_GetFreq/I2CX_InitPins/I2CX_DeinitPins for the enabled I2C instance. 111 */ 112 #define RTE_I2C0 0 113 #define RTE_I2C0_DMA_EN 0 114 #define RTE_I2C1 0 115 #define RTE_I2C1_DMA_EN 0 116 #define RTE_I2C2 0 117 #define RTE_I2C2_DMA_EN 0 118 #define RTE_I2C3 0 119 #define RTE_I2C3_DMA_EN 0 120 121 /* I2C configuration */ 122 #define RTE_I2C0_Master_DMA_BASE DMA0 123 #define RTE_I2C0_Master_DMA_CH 0 124 #define RTE_I2C0_Master_DMAMUX_BASE DMAMUX0 125 #define RTE_I2C0_Master_PERI_SEL kDmaRequestMux0I2C0 126 127 #define RTE_I2C1_Master_DMA_BASE DMA0 128 #define RTE_I2C1_Master_DMA_CH 1 129 #define RTE_I2C1_Master_DMAMUX_BASE DMAMUX0 130 #define RTE_I2C1_Master_PERI_SEL kDmaRequestMux0I2C1 131 132 #define RTE_I2C2_Master_DMA_BASE DMA0 133 #define RTE_I2C2_Master_DMA_CH 2 134 #define RTE_I2C2_Master_DMAMUX_BASE DMAMUX0 135 #define RTE_I2C2_Master_PERI_SEL kDmaRequestMux0I2C2 136 137 #define RTE_I2C3_Master_DMA_BASE DMA0 138 #define RTE_I2C3_Master_DMA_CH 3 139 #define RTE_I2C3_Master_DMAMUX_BASE DMAMUX0 140 #define RTE_I2C3_Master_PERI_SEL kDmaRequestMux0I2C3 141 142 /* DSPI Select, DSPI0 - DSPI2. */ 143 /* User needs to provide the implementation of DSPIX_GetFreq/DSPIX_InitPins/DSPIX_DeinitPins for the enabled DSPI 144 * instance. */ 145 #define RTE_SPI0 0 146 #define RTE_SPI0_DMA_EN 0 147 #define RTE_SPI1 0 148 #define RTE_SPI1_DMA_EN 0 149 #define RTE_SPI2 0 150 #define RTE_SPI2_DMA_EN 0 151 152 /* DSPI configuration. */ 153 #define RTE_SPI0_PCS_TO_SCK_DELAY 1000 154 #define RTE_SPI0_SCK_TO_PSC_DELAY 1000 155 #define RTE_SPI0_BETWEEN_TRANSFER_DELAY 1000 156 #define RTE_SPI0_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 157 #define RTE_SPI0_PIN_INIT DSPI0_InitPins 158 #define RTE_SPI0_PIN_DEINIT DSPI0_DeinitPins 159 #define RTE_SPI0_DMA_TX_CH 0 160 #define RTE_SPI0_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Tx 161 #define RTE_SPI0_DMA_TX_DMAMUX_BASE DMAMUX0 162 #define RTE_SPI0_DMA_TX_DMA_BASE DMA0 163 #define RTE_SPI0_DMA_RX_CH 1 164 #define RTE_SPI0_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI0Rx 165 #define RTE_SPI0_DMA_RX_DMAMUX_BASE DMAMUX0 166 #define RTE_SPI0_DMA_RX_DMA_BASE DMA0 167 #define RTE_SPI0_DMA_LINK_DMA_BASE DMA0 168 #define RTE_SPI0_DMA_LINK_CH 2 169 170 #define RTE_SPI1_PCS_TO_SCK_DELAY 1000 171 #define RTE_SPI1_SCK_TO_PSC_DELAY 1000 172 #define RTE_SPI1_BETWEEN_TRANSFER_DELAY 1000 173 #define RTE_SPI1_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 174 #define RTE_SPI1_PIN_INIT DSPI1_InitPins 175 #define RTE_SPI1_PIN_DEINIT DSPI1_DeinitPins 176 #define RTE_SPI1_DMA_TX_CH 0 177 #define RTE_SPI1_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Tx 178 #define RTE_SPI1_DMA_TX_DMAMUX_BASE DMAMUX0 179 #define RTE_SPI1_DMA_TX_DMA_BASE DMA0 180 #define RTE_SPI1_DMA_RX_CH 1 181 #define RTE_SPI1_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI1Rx 182 #define RTE_SPI1_DMA_RX_DMAMUX_BASE DMAMUX0 183 #define RTE_SPI1_DMA_RX_DMA_BASE DMA0 184 #define RTE_SPI1_DMA_LINK_DMA_BASE DMA0 185 #define RTE_SPI1_DMA_LINK_CH 2 186 187 #define RTE_SPI2_PCS_TO_SCK_DELAY 1000 188 #define RTE_SPI2_SCK_TO_PSC_DELAY 1000 189 #define RTE_SPI2_BETWEEN_TRANSFER_DELAY 1000 190 #define RTE_SPI2_MASTER_PCS_PIN_SEL kDSPI_MasterPcs0 191 #define RTE_SPI2_PIN_INIT DSPI2_InitPins 192 #define RTE_SPI2_PIN_DEINIT DSPI2_DeinitPins 193 #define RTE_SPI2_DMA_TX_CH 0 194 #define RTE_SPI2_DMA_TX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2Tx 195 #define RTE_SPI2_DMA_TX_DMAMUX_BASE DMAMUX0 196 #define RTE_SPI2_DMA_TX_DMA_BASE DMA0 197 #define RTE_SPI2_DMA_RX_CH 1 198 #define RTE_SPI2_DMA_RX_PERI_SEL (uint8_t) kDmaRequestMux0SPI2Rx 199 #define RTE_SPI2_DMA_RX_DMAMUX_BASE DMAMUX0 200 #define RTE_SPI2_DMA_RX_DMA_BASE DMA0 201 #define RTE_SPI2_DMA_LINK_DMA_BASE DMA0 202 #define RTE_SPI2_DMA_LINK_CH 2 203 204 #endif /* _RTE_DEVICE_H */ 205
