1 /*
2 ** ###################################################################
3 **     Processors:          MK22FN128CAH12
4 **                          MK22FN256CAH12
5 **                          MK22FN256VDC12
6 **                          MK22FN256VLH12
7 **                          MK22FN256VLL12
8 **                          MK22FN256VMP12
9 **
10 **     Compilers:           Freescale C/C++ for Embedded ARM
11 **                          GNU C Compiler
12 **                          IAR ANSI C/C++ Compiler for ARM
13 **                          Keil ARM C/C++ Compiler
14 **                          MCUXpresso Compiler
15 **
16 **     Reference manual:    K22P121M120SF8RM, Rev. 1, March 24, 2014
17 **     Version:             rev. 1.8, 2015-02-19
18 **     Build:               b181105
19 **
20 **     Abstract:
21 **         Provides a system configuration function and a global variable that
22 **         contains the system frequency. It configures the device and initializes
23 **         the oscillator (PLL) that is part of the microcontroller device.
24 **
25 **     Copyright 2016 Freescale Semiconductor, Inc.
26 **     Copyright 2016-2018 NXP
27 **     All rights reserved.
28 **
29 **     SPDX-License-Identifier: BSD-3-Clause
30 **
31 **     http:                 www.nxp.com
32 **     mail:                 support@nxp.com
33 **
34 **     Revisions:
35 **     - rev. 1.0 (2013-09-17)
36 **         Initial version.
37 **     - rev. 1.1 (2013-10-29)
38 **         Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
39 **     - rev. 1.2 (2013-12-20)
40 **         Update according to reference manual rev. 0.6,
41 **     - rev. 1.3 (2014-02-06)
42 **         Update according to reference manual rev. 0.61,
43 **     - rev. 1.4 (2014-02-10)
44 **         The declaration of clock configurations has been moved to separate header file system_MK22F25612.h
45 **     - rev. 1.5 (2014-04-30)
46 **         Update of MCM and USB modules according to the RM rev. 1.
47 **         Update of system and startup files.
48 **         Module access macro module_BASES replaced by module_BASE_PTRS.
49 **     - rev. 1.6 (2014-08-28)
50 **         Update of system files - default clock configuration changed.
51 **         Update of startup files - possibility to override DefaultISR added.
52 **     - rev. 1.7 (2014-10-14)
53 **         Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
54 **     - rev. 1.8 (2015-02-19)
55 **         Renamed interrupt vector LLW to LLWU.
56 **
57 ** ###################################################################
58 */
59 
60 /*!
61  * @file MK22F25612
62  * @version 1.8
63  * @date 2015-02-19
64  * @brief Device specific configuration file for MK22F25612 (implementation file)
65  *
66  * Provides a system configuration function and a global variable that contains
67  * the system frequency. It configures the device and initializes the oscillator
68  * (PLL) that is part of the microcontroller device.
69  */
70 
71 #include <stdint.h>
72 #include "fsl_device_registers.h"
73 
74 
75 
76 /* ----------------------------------------------------------------------------
77    -- Core clock
78    ---------------------------------------------------------------------------- */
79 
80 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
81 
82 /* ----------------------------------------------------------------------------
83    -- SystemInit()
84    ---------------------------------------------------------------------------- */
85 
SystemInit(void)86 void SystemInit (void) {
87 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
88   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access */
89 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
90 
91 #if (DISABLE_WDOG)
92   /* WDOG->UNLOCK: WDOGUNLOCK=0xC520 */
93   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xC520); /* Key 1 */
94   /* WDOG->UNLOCK: WDOGUNLOCK=0xD928 */
95   WDOG->UNLOCK = WDOG_UNLOCK_WDOGUNLOCK(0xD928); /* Key 2 */
96   /* WDOG->STCTRLH: ?=0,DISTESTWDOG=0,BYTESEL=0,TESTSEL=0,TESTWDOG=0,?=0,?=1,WAITEN=1,STOPEN=1,DBGEN=0,ALLOWUPDATE=1,WINEN=0,IRQRSTEN=0,CLKSRC=1,WDOGEN=0 */
97   WDOG->STCTRLH = WDOG_STCTRLH_BYTESEL(0x00) |
98                  WDOG_STCTRLH_WAITEN_MASK |
99                  WDOG_STCTRLH_STOPEN_MASK |
100                  WDOG_STCTRLH_ALLOWUPDATE_MASK |
101                  WDOG_STCTRLH_CLKSRC_MASK |
102                  0x0100U;
103 #endif /* (DISABLE_WDOG) */
104 
105   SystemInitHook();
106 }
107 
108 /* ----------------------------------------------------------------------------
109    -- SystemCoreClockUpdate()
110    ---------------------------------------------------------------------------- */
111 
SystemCoreClockUpdate(void)112 void SystemCoreClockUpdate (void) {
113 
114   uint32_t MCGOUTClock;                                                        /* Variable to store output clock frequency of the MCG module */
115   uint16_t Divider;
116   uint8_t tmpC7 = 0;
117 
118   if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x00U) {
119     /* Output of FLL or PLL is selected */
120     if ((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U) {
121       /* FLL is selected */
122       if ((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U) {
123         /* External reference clock is selected */
124         switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
125         case 0x00U:
126           MCGOUTClock = CPU_XTAL_CLK_HZ; /* System oscillator drives MCG clock */
127           break;
128         case 0x01U:
129           MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
130           break;
131         case 0x02U:
132         default:
133           MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
134           break;
135         }
136         tmpC7 = MCG->C7;
137         if (((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) && ((tmpC7 & MCG_C7_OSCSEL_MASK) != 0x01U)) {
138           switch (MCG->C1 & MCG_C1_FRDIV_MASK) {
139           case 0x38U:
140             Divider = 1536U;
141             break;
142           case 0x30U:
143             Divider = 1280U;
144             break;
145           default:
146             Divider = (uint16_t)(32LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
147             break;
148           }
149         } else {/* ((MCG->C2 & MCG_C2_RANGE_MASK) != 0x00U) */
150           Divider = (uint16_t)(1LU << ((MCG->C1 & MCG_C1_FRDIV_MASK) >> MCG_C1_FRDIV_SHIFT));
151         }
152         MCGOUTClock = (MCGOUTClock / Divider); /* Calculate the divided FLL reference clock */
153       } else { /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
154         MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* The slow internal reference clock is selected */
155       } /* (!((MCG->C1 & MCG_C1_IREFS_MASK) == 0x00U)) */
156       /* Select correct multiplier to calculate the MCG output clock  */
157       switch (MCG->C4 & (MCG_C4_DMX32_MASK | MCG_C4_DRST_DRS_MASK)) {
158         case 0x00U:
159           MCGOUTClock *= 640U;
160           break;
161         case 0x20U:
162           MCGOUTClock *= 1280U;
163           break;
164         case 0x40U:
165           MCGOUTClock *= 1920U;
166           break;
167         case 0x60U:
168           MCGOUTClock *= 2560U;
169           break;
170         case 0x80U:
171           MCGOUTClock *= 732U;
172           break;
173         case 0xA0U:
174           MCGOUTClock *= 1464U;
175           break;
176         case 0xC0U:
177           MCGOUTClock *= 2197U;
178           break;
179         case 0xE0U:
180           MCGOUTClock *= 2929U;
181           break;
182         default:
183           MCGOUTClock *= 640U;
184           break;
185       }
186     } else { /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
187       /* PLL is selected */
188       Divider = (((uint16_t)MCG->C5 & MCG_C5_PRDIV0_MASK) + 0x01U);
189       MCGOUTClock = (uint32_t)(CPU_XTAL_CLK_HZ / Divider); /* Calculate the PLL reference clock */
190       Divider = (((uint16_t)MCG->C6 & MCG_C6_VDIV0_MASK) + 24U);
191       MCGOUTClock *= Divider;          /* Calculate the MCG output clock */
192     } /* (!((MCG->C6 & MCG_C6_PLLS_MASK) == 0x00U)) */
193   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x40U) {
194     /* Internal reference clock is selected */
195     if ((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U) {
196       MCGOUTClock = CPU_INT_SLOW_CLK_HZ; /* Slow internal reference clock selected */
197     } else { /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
198       Divider = (uint16_t)(0x01LU << ((MCG->SC & MCG_SC_FCRDIV_MASK) >> MCG_SC_FCRDIV_SHIFT));
199       MCGOUTClock = (uint32_t) (CPU_INT_FAST_CLK_HZ / Divider); /* Fast internal reference clock selected */
200     } /* (!((MCG->C2 & MCG_C2_IRCS_MASK) == 0x00U)) */
201   } else if ((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U) {
202     /* External reference clock is selected */
203     switch (MCG->C7 & MCG_C7_OSCSEL_MASK) {
204     case 0x00U:
205       MCGOUTClock = CPU_XTAL_CLK_HZ;   /* System oscillator drives MCG clock */
206       break;
207     case 0x01U:
208       MCGOUTClock = CPU_XTAL32k_CLK_HZ; /* RTC 32 kHz oscillator drives MCG clock */
209       break;
210     case 0x02U:
211     default:
212       MCGOUTClock = CPU_INT_IRC_CLK_HZ; /* IRC 48MHz oscillator drives MCG clock */
213       break;
214     }
215   } else { /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
216     /* Reserved value */
217     return;
218   } /* (!((MCG->C1 & MCG_C1_CLKS_MASK) == 0x80U)) */
219   SystemCoreClock = (MCGOUTClock / (0x01U + ((SIM->CLKDIV1 & SIM_CLKDIV1_OUTDIV1_MASK) >> SIM_CLKDIV1_OUTDIV1_SHIFT)));
220 
221 }
222 
223 /* ----------------------------------------------------------------------------
224    -- SystemInitHook()
225    ---------------------------------------------------------------------------- */
226 
SystemInitHook(void)227 __attribute__ ((weak)) void SystemInitHook (void) {
228   /* Void implementation of the weak function. */
229 }
230