1 /*
2 ** ###################################################################
3 **     Processors:          MIMXRT633SFAWBR
4 **                          MIMXRT633SFFOB
5 **                          MIMXRT633SFVKB
6 **
7 **     Compilers:           GNU C Compiler
8 **                          IAR ANSI C/C++ Compiler for ARM
9 **                          Keil ARM C/C++ Compiler
10 **                          MCUXpresso Compiler
11 **
12 **     Reference manual:    MIMXRT685 User manual Rev. 0.95 11 November 2019
13 **     Version:             rev. 2.0, 2019-11-12
14 **     Build:               b201016
15 **
16 **     Abstract:
17 **         Provides a system configuration function and a global variable that
18 **         contains the system frequency. It configures the device and initializes
19 **         the oscillator (PLL) that is part of the microcontroller device.
20 **
21 **     Copyright 2016 Freescale Semiconductor, Inc.
22 **     Copyright 2016-2020 NXP
23 **     All rights reserved.
24 **
25 **     SPDX-License-Identifier: BSD-3-Clause
26 **
27 **     http:                 www.nxp.com
28 **     mail:                 support@nxp.com
29 **
30 **     Revisions:
31 **     - rev. 1.0 (2018-06-19)
32 **         Initial version.
33 **     - rev. 2.0 (2019-11-12)
34 **         Base on rev 0.95 RM (B0 Header)
35 **
36 ** ###################################################################
37 */
38 
39 /*!
40  * @file MIMXRT633S
41  * @version 2.0
42  * @date 2019-11-12
43  * @brief Device specific configuration file for MIMXRT633S (implementation file)
44  *
45  * Provides a system configuration function and a global variable that contains
46  * the system frequency. It configures the device and initializes the oscillator
47  * (PLL) that is part of the microcontroller device.
48  */
49 
50 #include <stdint.h>
51 #include "fsl_device_registers.h"
52 
53 
54 #define SYSTEM_IS_XIP_FLEXSPI()                                                                               \
55     ((((uint32_t)SystemCoreClockUpdate >= 0x08000000U) && ((uint32_t)SystemCoreClockUpdate < 0x10000000U)) || \
56      (((uint32_t)SystemCoreClockUpdate >= 0x18000000U) && ((uint32_t)SystemCoreClockUpdate < 0x20000000U)))
57 
58 /* Get OSC clock from SYSOSC_BYPASS */
getOscClk(void)59 static uint32_t getOscClk(void)
60 {
61   return (CLKCTL0->SYSOSCBYPASS == 0U) ? CLK_XTAL_OSC_CLK : ((CLKCTL0->SYSOSCBYPASS == 1U) ? CLK_EXT_CLKIN : 0U);
62 }
63 
64 /* Get FFRO clock from FFROCTL0 setting */
getFFroFreq(void)65 static uint32_t getFFroFreq(void)
66 {
67   uint32_t freq = 0U;
68 
69   switch (CLKCTL0->FFROCTL0 & CLKCTL0_FFROCTL0_TRIM_RANGE_MASK)
70   {
71     case CLKCTL0_FFROCTL0_TRIM_RANGE(0):
72       freq = CLK_FRO_48MHZ;
73       break;
74     case CLKCTL0_FFROCTL0_TRIM_RANGE(3):
75       freq = CLK_FRO_60MHZ;
76       break;
77     default:
78       freq = 0U;
79       break;
80   }
81   return freq;
82 }
83 
84 
85 
86 /* ----------------------------------------------------------------------------
87    -- Core clock
88    ---------------------------------------------------------------------------- */
89 
90 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
91 
92 /* ----------------------------------------------------------------------------
93    -- SystemInit()
94    ---------------------------------------------------------------------------- */
95 
SystemInit(void)96 __attribute__ ((weak)) void SystemInit (void) {
97 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
98   SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Secure mode */
99   #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
100   SCB_NS->CPACR |= ((3UL << 10*2) | (3UL << 11*2));    /* set CP10, CP11 Full Access in Non-secure mode */
101   #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
102 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
103 
104   SCB->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
105 
106 #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
107   SCB_NS->CPACR |= ((3UL << 0*2) | (3UL << 1*2));    /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
108 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
109 
110   SCB->NSACR |= ((3UL << 0) | (3UL << 10));   /* enable CP0, CP1, CP10, CP11 Non-secure Access */
111 
112   SYSCTL0->DSPSTALL = SYSCTL0_DSPSTALL_DSPSTALL_MASK;
113 
114   if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL->POLSEL == 0U)) /* Enable cache to accelerate boot. */
115   {
116     /* set command to invalidate all ways and write GO bit to initiate command */
117     CACHE64->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
118     CACHE64->CCR |= CACHE64_CTRL_CCR_GO_MASK;
119     /* Wait until the command completes */
120     while ((CACHE64->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
121     {
122     }
123     /* Enable cache, enable write buffer */
124     CACHE64->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
125 
126     /* Set whole FlexSPI0 space to write through. */
127     CACHE64_POLSEL->REG0_TOP = 0x07FFFC00U;
128     CACHE64_POLSEL->REG1_TOP = 0x0U;
129     CACHE64_POLSEL->POLSEL = 0x1U;
130 
131     __ISB();
132     __DSB();
133   }
134 
135   SystemInitHook();
136 }
137 
138 /* ----------------------------------------------------------------------------
139    -- SystemCoreClockUpdate()
140    ---------------------------------------------------------------------------- */
141 
SystemCoreClockUpdate(void)142 void SystemCoreClockUpdate (void) {
143 
144   /* iMXRT6xx systemCoreClockUpdate */
145   uint32_t freq = 0U;
146   uint64_t freqTmp = 0U;
147 
148   switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
149   {
150     case CLKCTL0_MAINCLKSELB_SEL(0): /* MAINCLKSELA clock */
151       switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
152       {
153         case CLKCTL0_MAINCLKSELA_SEL(0): /* FFRO clock (48/60m_irc) divider by 4 */
154           freq = getFFroFreq() / 4U;
155           break;
156         case CLKCTL0_MAINCLKSELA_SEL(1): /* OSC clock (clk_in) */
157           freq = getOscClk();
158           break;
159         case CLKCTL0_MAINCLKSELA_SEL(2): /* Low Power Oscillator Clock (1m_lposc) */
160           freq = CLK_LPOSC_1MHZ;
161           break;
162         case CLKCTL0_MAINCLKSELA_SEL(3): /* FFRO clock */
163           freq = getFFroFreq();
164           break;
165         default:
166           freq = 0U;
167           break;
168       }
169       break;
170     case CLKCTL0_MAINCLKSELB_SEL(1): /* SFRO clock */
171       freq = CLK_FRO_16MHZ;
172       break;
173     case CLKCTL0_MAINCLKSELB_SEL(2): /* Main System PLL clock */
174       switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
175       {
176         case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* SFRO clock */
177           freq = CLK_FRO_16MHZ;
178           break;
179         case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock (clk_in) */
180           freq = getOscClk();
181           break;
182         case CLKCTL0_SYSPLL0CLKSEL_SEL(2): /* FFRO clock (48/60m_irc) divider by 2 */
183           freq = getFFroFreq() / 2U;
184           break;
185         default:
186           freq = 0U;
187           break;
188       }
189 
190       if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
191       {
192         /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
193         freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
194         freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
195         freq += (uint32_t)freqTmp;
196         freq = (uint32_t)((uint64_t)freq * 18U /
197                ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
198       }
199       freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
200       break;
201 
202     case CLKCTL0_MAINCLKSELB_SEL(3): /* RTC 32KHz clock */
203         freq = CLK_RTC_32K_CLK;
204         break;
205 
206     default:
207         freq = 0U;
208         break;
209   }
210 
211   SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & 0xffU) + 1U);
212 
213 }
214 
215 /* ----------------------------------------------------------------------------
216    -- SystemInitHook()
217    ---------------------------------------------------------------------------- */
218 
SystemInitHook(void)219 __attribute__ ((weak)) void SystemInitHook (void) {
220   /* Void implementation of the weak function. */
221 }
222