1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT555SFAWC
4 ** MIMXRT555SFFOC
5 **
6 ** Compilers: GNU C Compiler
7 ** IAR ANSI C/C++ Compiler for ARM
8 ** Keil ARM C/C++ Compiler
9 ** MCUXpresso Compiler
10 **
11 ** Reference manual: iMXRT500RM Rev.0, 01/2021
12 ** Version: rev. 5.0, 2020-08-27
13 ** Build: b220711
14 **
15 ** Abstract:
16 ** Provides a system configuration function and a global variable that
17 ** contains the system frequency. It configures the device and initializes
18 ** the oscillator (PLL) that is part of the microcontroller device.
19 **
20 ** Copyright 2016 Freescale Semiconductor, Inc.
21 ** Copyright 2016-2022 NXP
22 ** All rights reserved.
23 **
24 ** SPDX-License-Identifier: BSD-3-Clause
25 **
26 ** http: www.nxp.com
27 ** mail: support@nxp.com
28 **
29 ** Revisions:
30 ** - rev. 1.0 (2019-04-19)
31 ** Initial version.
32 ** - rev. 2.0 (2019-07-22)
33 ** Base on rev 0.7 RM.
34 ** - rev. 3.0 (2020-03-16)
35 ** Base on Rev.A RM.
36 ** - rev. 4.0 (2020-05-18)
37 ** Base on Rev.B RM.
38 ** - rev. 5.0 (2020-08-27)
39 ** Base on Rev.C RM.
40 **
41 ** ###################################################################
42 */
43
44 /*!
45 * @file MIMXRT555S
46 * @version 5.0
47 * @date 2020-08-27
48 * @brief Device specific configuration file for MIMXRT555S (implementation file)
49 *
50 * Provides a system configuration function and a global variable that contains
51 * the system frequency. It configures the device and initializes the oscillator
52 * (PLL) that is part of the microcontroller device.
53 */
54
55 #include <stdint.h>
56 #include "fsl_device_registers.h"
57
58 #define SYSTEM_IS_XIP_FLEXSPI() \
59 ((((uint32_t)SystemCoreClockUpdate >= 0x08000000U) && ((uint32_t)SystemCoreClockUpdate < 0x10000000U)) || \
60 (((uint32_t)SystemCoreClockUpdate >= 0x18000000U) && ((uint32_t)SystemCoreClockUpdate < 0x20000000U)))
61
62 /* Get FRO DIV clock from FRODIVSEL */
getFroDivClk(void)63 static uint32_t getFroDivClk(void)
64 {
65 uint32_t freq = 0U;
66
67 switch ((CLKCTL0->FRODIVSEL) & CLKCTL0_FRODIVSEL_SEL_MASK)
68 {
69 case CLKCTL0_FRODIVSEL_SEL(0):
70 freq = CLK_FRO_DIV2_CLK;
71 break;
72 case CLKCTL0_FRODIVSEL_SEL(1):
73 freq = CLK_FRO_DIV4_CLK;
74 break;
75 case CLKCTL0_FRODIVSEL_SEL(2):
76 freq = CLK_FRO_DIV8_CLK;
77 break;
78 case CLKCTL0_FRODIVSEL_SEL(3):
79 freq = CLK_FRO_DIV16_CLK;
80 break;
81 default:
82 freq = 0U;
83 break;
84 }
85
86 return freq;
87 }
88
89 /* ----------------------------------------------------------------------------
90 -- Core clock
91 ---------------------------------------------------------------------------- */
92
93 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
94
95 /* ----------------------------------------------------------------------------
96 -- SystemInit()
97 ---------------------------------------------------------------------------- */
98
SystemInit(void)99 __attribute__((weak)) void SystemInit(void)
100 {
101 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
102 SCB->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Secure mode */
103 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
104 SCB_NS->CPACR |= ((3UL << 10 * 2) | (3UL << 11 * 2)); /* set CP10, CP11 Full Access in Non-secure mode */
105 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
106 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
107
108 SCB->CPACR |= ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Secure mode (enable PowerQuad) */
109
110 #if defined(__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
111 SCB_NS->CPACR |=
112 ((3UL << 0 * 2) | (3UL << 1 * 2)); /* set CP0, CP1 Full Access in Non-secure mode (enable PowerQuad) */
113 #endif /* (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
114
115 SCB->NSACR |= ((3UL << 0) | (3UL << 10)); /* enable CP0, CP1, CP10, CP11 Non-secure Access */
116
117 SYSCTL0->DSPSTALL = SYSCTL0_DSPSTALL_DSPSTALL_MASK;
118
119 PMC->CTRL |= PMC_CTRL_CLKDIVEN_MASK; /* enable the internal clock divider for power saving */
120
121 if (SYSTEM_IS_XIP_FLEXSPI() && (CACHE64_POLSEL0->POLSEL == 0U)) /* set CAHCHE64 if not configured */
122 {
123 /* set command to invalidate all ways and write GO bit to initiate command */
124 CACHE64_CTRL0->CCR = CACHE64_CTRL_CCR_INVW1_MASK | CACHE64_CTRL_CCR_INVW0_MASK;
125 CACHE64_CTRL0->CCR |= CACHE64_CTRL_CCR_GO_MASK;
126 /* Wait until the command completes */
127 while ((CACHE64_CTRL0->CCR & CACHE64_CTRL_CCR_GO_MASK) != 0U)
128 {
129 }
130 /* Enable cache, enable write buffer */
131 CACHE64_CTRL0->CCR = (CACHE64_CTRL_CCR_ENWRBUF_MASK | CACHE64_CTRL_CCR_ENCACHE_MASK);
132
133 /* Set whole FlexSPI0 space to write through. */
134 CACHE64_POLSEL0->REG0_TOP = 0x07FFFC00U;
135 CACHE64_POLSEL0->REG1_TOP = 0x0U;
136 CACHE64_POLSEL0->POLSEL = 0x1U;
137
138 __ISB();
139 __DSB();
140 }
141
142 SystemInitHook();
143 }
144
145 /* ----------------------------------------------------------------------------
146 -- SystemCoreClockUpdate()
147 ---------------------------------------------------------------------------- */
148
SystemCoreClockUpdate(void)149 void SystemCoreClockUpdate(void)
150 {
151 /* iMXRT5xx systemCoreClockUpdate */
152 uint32_t freq = 0U;
153 uint64_t freqTmp = 0U;
154
155 switch ((CLKCTL0->MAINCLKSELB) & CLKCTL0_MAINCLKSELB_SEL_MASK)
156 {
157 case CLKCTL0_MAINCLKSELB_SEL(0): /* MAINCLKSELA clock */
158 switch ((CLKCTL0->MAINCLKSELA) & CLKCTL0_MAINCLKSELA_SEL_MASK)
159 {
160 case CLKCTL0_MAINCLKSELA_SEL(0): /* Low Power Oscillator Clock (1m_lposc) */
161 freq = CLK_LPOSC_1MHZ;
162 break;
163 case CLKCTL0_MAINCLKSELA_SEL(1): /* FRO DIV clock */
164 freq = getFroDivClk();
165 break;
166 case CLKCTL0_MAINCLKSELA_SEL(2): /* OSC clock */
167 freq = CLK_OSC_CLK;
168 break;
169 case CLKCTL0_MAINCLKSELA_SEL(3): /* FRO clock */
170 freq = CLK_FRO_CLK;
171 break;
172 default:
173 freq = 0U;
174 break;
175 }
176 break;
177
178 case CLKCTL0_MAINCLKSELB_SEL(1): /* Main System PLL clock */
179 switch ((CLKCTL0->SYSPLL0CLKSEL) & CLKCTL0_SYSPLL0CLKSEL_SEL_MASK)
180 {
181 case CLKCTL0_SYSPLL0CLKSEL_SEL(0): /* FRO_DIV8 clock */
182 freq = CLK_FRO_DIV8_CLK;
183 break;
184 case CLKCTL0_SYSPLL0CLKSEL_SEL(1): /* OSC clock */
185 freq = CLK_OSC_CLK;
186 break;
187 default:
188 freq = 0U;
189 break;
190 }
191
192 if (((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_BYPASS_MASK) == 0U)
193 {
194 /* PLL output frequency = Fref * (DIV_SELECT + NUM/DENOM). */
195 freqTmp = ((uint64_t)freq * ((uint64_t)(CLKCTL0->SYSPLL0NUM))) / ((uint64_t)(CLKCTL0->SYSPLL0DENOM));
196 freq *= ((CLKCTL0->SYSPLL0CTL0) & CLKCTL0_SYSPLL0CTL0_MULT_MASK) >> CLKCTL0_SYSPLL0CTL0_MULT_SHIFT;
197 freq += (uint32_t)freqTmp;
198 freq =
199 (uint32_t)((uint64_t)freq * 18U /
200 ((CLKCTL0->SYSPLL0PFD & CLKCTL0_SYSPLL0PFD_PFD0_MASK) >> CLKCTL0_SYSPLL0PFD_PFD0_SHIFT));
201 }
202
203 freq = freq / ((CLKCTL0->MAINPLLCLKDIV & CLKCTL0_MAINPLLCLKDIV_DIV_MASK) + 1U);
204 break;
205
206 case CLKCTL0_MAINCLKSELB_SEL(2): /* RTC 32KHz clock */
207 freq = CLK_RTC_32K_CLK;
208 break;
209
210 default:
211 freq = 0U;
212 break;
213 }
214
215 SystemCoreClock = freq / ((CLKCTL0->SYSCPUAHBCLKDIV & CLKCTL0_SYSCPUAHBCLKDIV_DIV_MASK) + 1U);
216 }
217
218 /* ----------------------------------------------------------------------------
219 -- SystemInitHook()
220 ---------------------------------------------------------------------------- */
221
SystemInitHook(void)222 __attribute__((weak)) void SystemInitHook(void)
223 {
224 /* Void implementation of the weak function. */
225 }
226
