1 /*
2  * Copyright 2019-2021,2023 NXP
3  * All rights reserved.
4  *
5  *
6  * SPDX-License-Identifier: BSD-3-Clause
7  */
8 
9 #ifndef _FSL_PGMC_H_
10 #define _FSL_PGMC_H_
11 
12 #include "fsl_common.h"
13 
14 /*!
15  * @addtogroup PGMC
16  * @{
17  */
18 
19 /*******************************************************************************
20  * Definitions
21  ******************************************************************************/
22 
23 /*! @name Driver version */
24 /*@{*/
25 /*! @brief PGMC driver version 2.1.2. */
26 #define FSL_PGMC_RIVER_VERSION (MAKE_VERSION(2, 1, 2))
27 /*@}*/
28 
29 /*! @brief The enumeration of setpoint.
30  * @anchor _pgmc_setpoint_map
31  */
32 enum
33 {
34     kPGMC_SetPoint0  = 1UL << 0UL,  /*!< The mask of set point0. */
35     kPGMC_SetPoint1  = 1UL << 1UL,  /*!< The mask of set point1. */
36     kPGMC_SetPoint2  = 1UL << 2UL,  /*!< The mask of set point2. */
37     kPGMC_SetPoint3  = 1UL << 3UL,  /*!< The mask of set point3. */
38     kPGMC_SetPoint4  = 1UL << 4UL,  /*!< The mask of set point4. */
39     kPGMC_SetPoint5  = 1UL << 5UL,  /*!< The mask of set point5. */
40     kPGMC_SetPoint6  = 1UL << 6UL,  /*!< The mask of set point6. */
41     kPGMC_SetPoint7  = 1UL << 7UL,  /*!< The mask of set point7. */
42     kPGMC_SetPoint8  = 1UL << 8UL,  /*!< The mask of set point8. */
43     kPGMC_SetPoint9  = 1UL << 9UL,  /*!< The mask of set point9. */
44     kPGMC_SetPoint10 = 1UL << 10UL, /*!< The mask of set point10. */
45     kPGMC_SetPoint11 = 1UL << 11UL, /*!< The mask of set point11. */
46     kPGMC_SetPoint12 = 1UL << 12UL, /*!< The mask of set point12. */
47     kPGMC_SetPoint13 = 1UL << 13UL, /*!< The mask of set point13. */
48     kPGMC_SetPoint14 = 1UL << 14UL, /*!< The mask of set point14. */
49     kPGMC_SetPoint15 = 1UL << 15UL, /*!< The mask of set point15. */
50 };
51 
52 /*!
53  * @brief The enumeration of MIF signal behaviour(Such as Sleep Signal, Standby Signal, and so on).
54  */
55 enum _pgmc_mif_signal_behaviour
56 {
57     kPGMC_AssertSleepSignal               = 1U << 0U,  /*!< Assert Sleep signal. */
58     kPGMC_AssertInputGateSignal           = 1U << 1U,  /*!< Assert InputGate signal. */
59     kPGMC_AssetLowSpeedSignal             = 1U << 2U,  /*!< Assert LowSpeed signal. */
60     kPGMC_AssertHighSpeedSignal           = 1U << 3U,  /*!< Assert HighSpeed signal. */
61     kPGMC_AssertStandbySignal             = 1U << 4U,  /*!< Assert Standby signal. */
62     kPGMC_AssertArrayPowerDownSignal      = 1U << 5U,  /*!< Assert ArrayPowerDown signal. */
63     kPGMC_AssertPeripheralPowerDownSignal = 1U << 6U,  /*!< Assert PeripheralPowerDown signal. */
64     kPGMC_AssertInitnSignal               = 1U << 7U,  /*!< Assert Initn signal. */
65     kPGMC_AssertSwitch1OffSignal          = 1U << 8U,  /*!< Assert Switch1Off signal. */
66     kPGMC_AssertSwitch2OffSignal          = 1U << 9U,  /*!< Assert Switch2Off signal. */
67     kPGMC_AssertIsoSignal                 = 1U << 10U, /*!< Assert Iso_en signal. */
68 };
69 
70 /*!
71  * @brief PGMC BPC assign domain enumeration.
72  */
73 typedef enum _pgmc_bpc_assign_domain
74 {
75     kPGMC_CM7Core = 0U, /*!< CM7 Core domain. */
76     kPGMC_CM4Core = 1U  /*!< CM4 Core domain. */
77 } pgmc_bpc_assign_domain_t;
78 
79 /*! @brief CPU mode. */
80 typedef enum _pgmc_cpu_mode
81 {
82     kPGMC_RunMode     = 0x0UL, /*!< RUN mode. */
83     kPGMC_WaitMode    = 0x1UL, /*!< WAIT mode. */
84     kPGMC_StopMode    = 0x2UL, /*!< STOP mode. */
85     kPGMC_SuspendMode = 0x3UL, /*!< SUSPEND mode. */
86 } pgmc_cpu_mode_t;
87 
88 /*! @brief PGMC control modes. */
89 typedef enum _pgmc_control_mode
90 {
91     kPGMC_DisableLowPowerControl   = 0UL,
92     kPGMC_ControlledByCpuPowerMode = 1UL,
93     kPGMC_ControlledBySetPoint     = 2UL,
94 } pgmc_control_mode_t;
95 
96 /*!
97  * @brief The enumeration of memory low power level.
98  */
99 typedef enum _pgmc_memory_low_power_level
100 {
101     kPGMC_MLPLHighSpeed    = 1U,  /*!< Memory low power level: High speed. */
102     kPGMC_MLPLNormal       = 3U,  /*!< Memory low power level: Normal. */
103     kPGMC_MLPLLowSpeed     = 4U,  /*!< Memory low power level: Low Speed. */
104     kPGMC_MLPLInputGating  = 5U,  /*!< Memory low power level: Input Gating. */
105     kPGMC_MLPLStandby      = 6U,  /*!< Memory low power level: Standby. */
106     kPGMC_MLPLSleep        = 8U,  /*!< Memory low power level: Sleep. */
107     kPGMC_MLPLArrOnPerOff  = 9U,  /*!< Memory low power level: Arr on per off. */
108     kPGMC_MLPLArrOffPerOn  = 10U, /*!< Memory low power level: Arr off per on. */
109     kPGMC_MLPLArrOffPerOff = 11U, /*!< Memory low power level: Arr off per off. */
110     kPGMC_MLPLSw2          = 13U, /*!< Memory low power level: SW2. */
111     kPGMC_MLPLSw2PerOff    = 14U, /*!< Memory low power level: SW2 Per off. */
112     kPGMC_MLPLSw1PerOff    = 15U, /*!< Memory low power level: SW1 Per off. */
113 } pgmc_memory_low_power_level_t;
114 
115 /*!
116  * @brief The enumeration of MIF signal.
117  */
118 typedef enum _pgmc_mif_signal
119 {
120     kPGMC_SleepSignal               = 0U,  /*!< MIF Sleep signal. */
121     kPGMC_InputGateSignal           = 1U,  /*!< MIF InputGate signal. */
122     kPGMC_LowSpeedSignal            = 2U,  /*!< MIF LowSpeed signal. */
123     kPGMC_HighSpeedSignal           = 3U,  /*!< MIF HighSpeed signal. */
124     kPGMC_StandbySignal             = 4U,  /*!< MIF Standby signal. */
125     kPGMC_ArrayPowerDownSignal      = 5U,  /*!< MIF ArrayPowerDown signal. */
126     kPGMC_PeripheralPowerDownSignal = 6U,  /*!< MIF PeripheralPowerDown signal. */
127     kPGMC_InitnSignal               = 7U,  /*!< MIF Initn signal. */
128     kPGMC_Switch1OffSignal          = 8U,  /*!< MIF Switch1Off signal. */
129     kPGMC_Switch2OffSignal          = 9U,  /*!< MIF Switch2Off signal. */
130     kPGMC_IsoSignal                 = 10U, /*!< MIF Iso_en signal. */
131 } pgmc_mif_signal_t;
132 
133 /*!
134  * @brief The control option of the power domain controlled by CPU power mode.
135  */
136 typedef struct _pgmc_bpc_cpu_power_mode_option
137 {
138     pgmc_bpc_assign_domain_t assignDomain; /*!< Domain assignment of the BPC. The power mode of the selected core domain
139                                               will control the selected power domain. */
140     bool stateSave; /*!< Request save the state of power domain before entering target power mode.
141                             - \b true Save data when domain enter the selected mode.
142                             - \b false Do not save data when domain enter the selected mode. */
143     bool powerOff;  /*!< Request power off the power domain.
144                             - \b true Power off the power domain when enter the selected mode.
145                             - \b false Do not power off the power domain when enter the selected mode. */
146 } pgmc_bpc_cpu_power_mode_option_t;
147 
148 /*!
149  * @brief The control option of the power domain controlled by setpoint mode.
150  */
151 typedef struct _pgmc_bpc_setpoint_mode_option
152 {
153     bool stateSave; /*!< Request save the state of power domain before entering target setpoint.
154                             - \b true Save data when domain enter the selected setpoint.
155                             - \b false Do not save data when domain enter the selected setpoint. */
156     bool powerOff;  /*!< Request power off the power domain.
157                             - \b true Power off the power domain when enter the selected setpoint.
158                             - \b false Do not power off the power domain when enter the selected setpoint. */
159 } pgmc_bpc_setpoint_mode_option_t;
160 
161 /*******************************************************************************
162  * API
163  ******************************************************************************/
164 #if defined(__cplusplus)
165 extern "C" {
166 #endif
167 
168 /*!
169  * @name Basic Power Controller Related Interfaces
170  * @{
171  */
172 
173 /*!
174  * @brief Makes the BPC module controlled by the target CPU power mode, such as Wait mode.
175  *
176  * This function makes the module controlled by four typical CPU power modes, It also configs the resource domain and
177  * set memory low power level.
178  *
179  * @param base PGMC basic power controller base address.
180  * @param mode Target CPU power mode.
181  * @param option The pointer of @ref pgmc_bpc_cpu_power_mode_option_t structure.
182  */
183 void PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC_Type *base,
184                                                pgmc_cpu_mode_t mode,
185                                                const pgmc_bpc_cpu_power_mode_option_t *option);
186 
187 /*!
188  * @brief Makes the BPC module controlled by the target set points.
189  *
190  * This function makes the module controlled by specific set point, It also supports set memory lowe power level.
191  *
192  * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map.
193  *
194  * @param base PGMC basic power controller base address.
195  * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map.
196  * @param option The pointer of @ref pgmc_bpc_setpoint_mode_option_t structure.
197  */
198 void PGMC_BPC_ControlPowerDomainBySetPointMode(PGMC_BPC_Type *base,
199                                                uint32_t setPointMap,
200                                                const pgmc_bpc_setpoint_mode_option_t *option);
201 
202 /*!
203  * @brief Controls the selected power domain by software mode.
204  *
205  * @note The function is used to control power domain when the CPU is in RUN mode.
206  *
207  * @param base PGMC basic power controller base address.
208  * @param powerOff Power On/Off power domain in software mode.
209  *                  - \b true Power off the power domain in software mode.
210  *                  - \b false Power on the power domain in software mode.
211  */
212 void PGMC_BPC_ControlPowerDomainBySoftwareMode(PGMC_BPC_Type *base, bool powerOff);
213 
214 /*!
215  * @brief Disables low power mode control.
216  *
217  * @param base PGMC basic power controller base address.
218  */
PGMC_BPC_DisableLowPower(PGMC_BPC_Type * base)219 static inline void PGMC_BPC_DisableLowPower(PGMC_BPC_Type *base)
220 {
221     base->BPC_MODE = PGMC_BPC_BPC_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
222 }
223 
224 /*!
225  * @brief Requests power domain state restore at run mode.
226  *
227  * @param base PGMC basic power controller base address.
228  */
PGMC_BPC_RequestStateRestoreAtRunMode(PGMC_BPC_Type * base)229 static inline void PGMC_BPC_RequestStateRestoreAtRunMode(PGMC_BPC_Type *base)
230 {
231     base->BPC_SSAR_RESTORE_CTRL |= PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_RUN_MASK;
232 }
233 
234 /*!
235  * @brief Requests power domain state restore when enters the selected set points.
236  *
237  * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map.
238  * @param base PGMC basic power controller base address.
239  * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map.
240  */
PGMC_BPC_RequestStateRestoreAtSetPoint(PGMC_BPC_Type * base,uint32_t setPointMap)241 static inline void PGMC_BPC_RequestStateRestoreAtSetPoint(PGMC_BPC_Type *base, uint32_t setPointMap)
242 {
243     base->BPC_SSAR_RESTORE_CTRL |= PGMC_BPC_BPC_SSAR_RESTORE_CTRL_RESTORE_AT_SP(setPointMap & 0xFFFFU);
244 }
245 
246 /*!
247  * @brief Allows user mode access or not for the BPC module.
248  *
249  * @note If locked access related settings, the setting via this function is useless.
250  *
251  * @param base PGMC basic power controller base address.
252  * @param enable Used to control whether allow user mode access.
253  *           - \b true Allow both privilege and user mode to access CPU mode control registers.
254  *           - \b false Allow only privilege mode to access CPU mode control registers.
255  */
PGMC_BPC_AllowUserModeAccess(PGMC_BPC_Type * base,bool enable)256 static inline void PGMC_BPC_AllowUserModeAccess(PGMC_BPC_Type *base, bool enable)
257 {
258     if (enable)
259     {
260         base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK;
261     }
262     else
263     {
264         base->BPC_AUTHEN_CTRL &= ~PGMC_BPC_BPC_AUTHEN_CTRL_USER_MASK;
265     }
266 }
267 
268 /*!
269  * @brief Allows non-secure mode access or not for the BPC module.
270  *
271  * @note If locked access related settings, the setting via this function is useless.
272  *
273  * @param base PGMC basic power controller base address.
274  * @param enable Used to control whether allow non-secure mode to access CPU mode control registers.
275  *           - \b true Allow both secure and non-secure mode to access CPU mode control registers.
276  *           - \b false Allow only secure mode to access CPU mode control registers.
277  */
PGMC_BPC_AllowNonSecureModeAccess(PGMC_BPC_Type * base,bool enable)278 static inline void PGMC_BPC_AllowNonSecureModeAccess(PGMC_BPC_Type *base, bool enable)
279 {
280     if (enable)
281     {
282         base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK;
283     }
284     else
285     {
286         base->BPC_AUTHEN_CTRL &= ~PGMC_BPC_BPC_AUTHEN_CTRL_NONSECURE_MASK;
287     }
288 }
289 
290 /*!
291  * @brief Locks access related settings for the BPC module, including Secure access setting and user access setting.
292  *
293  * @note This function used to lock access related settings. After locked the related bit field
294  * can not be written unless POR.
295  *
296  * @param base PGMC basic power controller base address.
297  */
PGMC_BPC_LockAccessSetting(PGMC_BPC_Type * base)298 static inline void PGMC_BPC_LockAccessSetting(PGMC_BPC_Type *base)
299 {
300     base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_SETTING_MASK;
301 }
302 
303 /*!
304  * @brief Sets the corrsponding domain ID that can access CPU mode control registers for the BPC module.
305  *
306  * @note If locked the domain ID white list, the setting via this function is useless.
307  *
308  * @param base PGMC basic power controller base address.
309  * @param domainId Should be the OR'ed value of @ref pgmc_bpc_assign_domain_t.
310  */
PGMC_BPC_SetDomainIdWhiteList(PGMC_BPC_Type * base,uint8_t domainId)311 static inline void PGMC_BPC_SetDomainIdWhiteList(PGMC_BPC_Type *base, uint8_t domainId)
312 {
313     base->BPC_AUTHEN_CTRL = (base->BPC_AUTHEN_CTRL & (~PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST_MASK)) |
314                             PGMC_BPC_BPC_AUTHEN_CTRL_WHITE_LIST(domainId);
315 }
316 
317 /*!
318  * @brief Locks the value of Domain ID white list for the BPC module.
319  *
320  * @note After locked the domain ID white list can not be written again unless POR.
321  *
322  * @param base PGMC basic power controller base address.
323  */
PGMC_BPC_LockDomainIDWhiteList(PGMC_BPC_Type * base)324 static inline void PGMC_BPC_LockDomainIDWhiteList(PGMC_BPC_Type *base)
325 {
326     base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_LIST_MASK;
327 }
328 
329 /*!
330  * @brief Locks low power configuration fields for the BPC module.
331  *
332  * @note After locked the low power configurations fields can not be updated unless POR.
333  *
334  * @param base PGMC basic power controller base address.
335  */
PGMC_BPC_LockLowPowerConfigurationFields(PGMC_BPC_Type * base)336 static inline void PGMC_BPC_LockLowPowerConfigurationFields(PGMC_BPC_Type *base)
337 {
338     base->BPC_AUTHEN_CTRL |= PGMC_BPC_BPC_AUTHEN_CTRL_LOCK_CFG_MASK;
339 }
340 
341 /*!
342  * @}
343  */
344 
345 /*!
346  * @name CPU Power Controller Related Interfaces
347  * @{
348  */
349 
350 /*!
351  * @brief Powers off the CPC core module by the target CPU power mode, such as Wait mode.
352  *
353  * @param base CPC CORE module base address.
354  * @param mode Target CPU power mode.
355  */
356 void PGMC_CPC_CORE_PowerOffByCpuPowerMode(PGMC_CPC_Type *base, pgmc_cpu_mode_t mode);
357 
358 /*!
359  * @brief Powers off/on the CPC core module by the software.
360  *
361  * @param base CPC CORE module base address.
362  * @param powerOff Used to power off/on the CPC core module.
363  *              - \b true Power off the CPC core module.
364  *              - \b false Power on the CPC core module.
365  */
PGMC_CPC_CORE_PowerOffBySoftwareMode(PGMC_CPC_Type * base,bool powerOff)366 static inline void PGMC_CPC_CORE_PowerOffBySoftwareMode(PGMC_CPC_Type *base, bool powerOff)
367 {
368     if (powerOff)
369     {
370         base->CPC_CORE_POWER_CTRL |=
371             (PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_OFF_SOFT_MASK | PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_ON_SOFT_MASK);
372     }
373     else
374     {
375         base->CPC_CORE_POWER_CTRL |=
376             (PGMC_CPC_CPC_CORE_POWER_CTRL_ISO_OFF_SOFT_MASK | PGMC_CPC_CPC_CORE_POWER_CTRL_PSW_ON_SOFT_MASK);
377     }
378 }
379 
380 /*!
381  * @brief Disables low power mode control, the CPU core will not be affected by any low power modes.
382  *
383  * @param base CPC CORE module base address.
384  */
PGMC_CPC_CORE_DisableLowPower(PGMC_CPC_Type * base)385 static inline void PGMC_CPC_CORE_DisableLowPower(PGMC_CPC_Type *base)
386 {
387     base->CPC_CORE_MODE = PGMC_CPC_CPC_CORE_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
388 }
389 
390 /*!
391  * @brief Makes the CPC CACHE module controlled by the target CPU power mode, such as Wait mode.
392  *
393  * This function makes the module controlled by four typical CPU power modes, it also can set memory low power level.
394  *
395  * @param base CPC CACHE module base address.
396  * @param mode Target CPU power mode.
397  * @param memoryLowPowerLevel Memory low power level.
398  */
399 void PGMC_CPC_CACHE_ControlByCpuPowerMode(PGMC_CPC_Type *base,
400                                           pgmc_cpu_mode_t mode,
401                                           pgmc_memory_low_power_level_t memoryLowPowerLevel);
402 
403 /*!
404  * @brief Makes the CPC CACHE module controlled by the target set points.
405  *
406  * This function makes the module controlled by specific set point, It also supports set memory lowe power level.
407  *
408  * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map.
409  *
410  * @param base CPC CACHE module base address.
411  * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map.
412  * @param memoryLowPowerLevel Memory low power level.
413  */
414 void PGMC_CPC_CACHE_ControlBySetPointMode(PGMC_CPC_Type *base,
415                                           uint32_t setPointMap,
416                                           pgmc_memory_low_power_level_t memoryLowPowerLevel);
417 
418 /*!
419  * @brief Disables low power mode control, so the cache will not be affected by any low power modes.
420  *
421  * @param base CPC CACHE module base address.
422  */
PGMC_CPC_CACHE_DisableLowPower(PGMC_CPC_Type * base)423 static inline void PGMC_CPC_CACHE_DisableLowPower(PGMC_CPC_Type *base)
424 {
425     base->CPC_CACHE_MODE = PGMC_CPC_CPC_CACHE_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
426 }
427 
428 /*!
429  * @brief Requests CPC cache module's memory low power level change by software mode.
430  *
431  * @note If request memory low power level change, must wait the MLPL transition complete.
432  *
433  * @param base CPC LMEM module base address.
434  */
435 void PGMC_CPC_CACHE_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base);
436 
437 /*!
438  * @brief Makes the CPC LMEM module controlled by the target CPU power mode, such as Wait mode.
439  *
440  * This function makes the module controlled by four typical CPU power modes, it also can set memory low power level.
441  *
442  * @param base CPC LMEM module base address.
443  * @param mode Target CPU power mode.
444  * @param memoryLowPowerLevel Memory low power level.
445  */
446 void PGMC_CPC_LMEM_ControlByCpuPowerMode(PGMC_CPC_Type *base,
447                                          pgmc_cpu_mode_t mode,
448                                          pgmc_memory_low_power_level_t memoryLowPowerLevel);
449 
450 /*!
451  * @brief Makes the CPC LMEM module controlled by the target set points.
452  *
453  * This function makes the module controlled by specific set point, It also supports set memory lowe power level.
454  *
455  * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map.
456  *
457  * @param base CPC LMEM module base address.
458  * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map.
459  * @param memoryLowPowerLevel Memory low power level.
460  */
461 void PGMC_CPC_LMEM_ControlBySetPointMode(PGMC_CPC_Type *base,
462                                          uint32_t setPointMap,
463                                          pgmc_memory_low_power_level_t memoryLowPowerLevel);
464 
465 /*!
466  * @brief Disables low power mode control, so that the CPC LMEM will not be affected by any low power modes.
467  *
468  * @param base CPC LMEM module base address.
469  */
PGMC_CPC_LMEM_DisableLowPower(PGMC_CPC_Type * base)470 static inline void PGMC_CPC_LMEM_DisableLowPower(PGMC_CPC_Type *base)
471 {
472     base->CPC_LMEM_MODE = PGMC_CPC_CPC_LMEM_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
473 }
474 
475 /*!
476  * @brief Requests CPC LMEM module's memory low power level change in software mode.
477  *
478  * @note If request memory low power level change, must wait the MLPL transition complete.
479  *
480  * @param base CPC LMEM module base address.
481  */
482 void PGMC_CPC_LMEM_TriggerMLPLSoftwareChange(PGMC_CPC_Type *base);
483 
484 /*!
485  * @brief Allows user mode access or not for the CPC module.
486  *
487  * @note If locked access related settings, the setting via this function is useless.
488  *
489  * @param base CPC LMEM module base address.
490  * @param enable Used to control whether allow user mode access.
491  *           - \b true Allow both privilege and user mode to access CPU mode control registers.
492  *           - \b false Allow only privilege mode to access CPU mode control registers.
493  */
PGMC_CPC_AllowUserModeAccess(PGMC_CPC_Type * base,bool enable)494 static inline void PGMC_CPC_AllowUserModeAccess(PGMC_CPC_Type *base, bool enable)
495 {
496     if (enable)
497     {
498         base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK;
499     }
500     else
501     {
502         base->CPC_AUTHEN_CTRL &= ~PGMC_CPC_CPC_AUTHEN_CTRL_USER_MASK;
503     }
504 }
505 
506 /*!
507  * @brief Allows non-secure mode access or not for the CPC module.
508  *
509  * @note If locked access related settings, the setting via this function is useless.
510  *
511  * @param base CPC LMEM module base address.
512  * @param enable Used to control whether allow non-secure mode to access CPU mode control registers.
513  *           - \b true Allow both secure and non-secure mode to access CPU mode control registers.
514  *           - \b false Allow only secure mode to access CPU mode control registers.
515  */
PGMC_CPC_AllowNonSecureModeAccess(PGMC_CPC_Type * base,bool enable)516 static inline void PGMC_CPC_AllowNonSecureModeAccess(PGMC_CPC_Type *base, bool enable)
517 {
518     if (enable)
519     {
520         base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK;
521     }
522     else
523     {
524         base->CPC_AUTHEN_CTRL &= ~PGMC_CPC_CPC_AUTHEN_CTRL_NONSECURE_MASK;
525     }
526 }
527 
528 /*!
529  * @brief Locks access related settings, including secure access setting and user access setting, for the CPC module.
530  *
531  * @note This function used to lock access related settings. After locked the related bit field
532  * can not be written unless POR.
533  *
534  * @param base CPC LMEM module base address.
535  */
PGMC_CPC_LockAccessSetting(PGMC_CPC_Type * base)536 static inline void PGMC_CPC_LockAccessSetting(PGMC_CPC_Type *base)
537 {
538     base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_SETTING_MASK;
539 }
540 
541 /*!
542  * @brief Sets the corrsponding domain ID that can access CPU mode control registers for the CPC module.
543  *
544  * @note If the domain ID whitelist is locked, the setting via this function is useless.
545  *
546  * @param base CPC LMEM module base address.
547  * @param domainId Should be the OR'ed value of @ref pgmc_bpc_assign_domain_t.
548  */
PGMC_CPC_SetDomainIdWhiteList(PGMC_CPC_Type * base,uint8_t domainId)549 static inline void PGMC_CPC_SetDomainIdWhiteList(PGMC_CPC_Type *base, uint8_t domainId)
550 {
551     base->CPC_AUTHEN_CTRL = (base->CPC_AUTHEN_CTRL & (~PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST_MASK)) |
552                             PGMC_CPC_CPC_AUTHEN_CTRL_WHITE_LIST(domainId);
553 }
554 
555 /*!
556  * @brief Locks the value of Domain ID white list for CPC module.
557  *
558  * @note After locked the domain ID white list can not be written again unless POR.
559  *
560  * @param base CPC LMEM module base address.
561  */
PGMC_CPC_LockDomainIDWhiteList(PGMC_CPC_Type * base)562 static inline void PGMC_CPC_LockDomainIDWhiteList(PGMC_CPC_Type *base)
563 {
564     base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_LIST_MASK;
565 }
566 
567 /*!
568  * @brief Locks CPC realted low power configuration fields for CPC module.
569  *
570  * @note After locked the low power configurations fields can not be updated unless POR.
571  *
572  * @param base CPC LMEM module base address.
573  */
PGMC_CPC_LockLowPowerConfigurationFields(PGMC_CPC_Type * base)574 static inline void PGMC_CPC_LockLowPowerConfigurationFields(PGMC_CPC_Type *base)
575 {
576     base->CPC_AUTHEN_CTRL |= PGMC_CPC_CPC_AUTHEN_CTRL_LOCK_CFG_MASK;
577 }
578 
579 /*!
580  * @}
581  */
582 
583 /*!
584  * @name MIF Module Related APIs
585  * @{
586  */
587 
588 /*!
589  * @brief Sets the behaviour of each signal in MIF, such as Sleep signal.
590  *
591  * @note To control the memory low power operation, this function must be invoked after selecting the
592  *       memory low power level.
593  *       Use case:
594  *        @code
595  *              PGMC_BPC_ControlPowerDomainByCpuPowerMode(PGMC_BPC0_BASE, kPGMC_WaitMode, kPGMC_CM7Core,
596  *                  kPGMC_MLPLSleep, false);
597  *              PGMC_MIF_SetSignalBehaviour(PGMC_BPC0_MIF_BASE, kPGMC_MLPLSleep, kPGMC_AssertSleepSignal);
598  *        @endcode
599  *
600  * @param base PGMC MIF peripheral base address.
601  * @param memoryLevel The selected memory low power level. For details please refer to @ref
602  * pgmc_memory_low_power_level_t.
603  * @param mask The mask of MIF signal behaviour. Should be the OR'ed value of @ref _pgmc_mif_signal_behaviour
604  */
605 void PGMC_MIF_SetSignalBehaviour(PGMC_MIF_Type *base, pgmc_memory_low_power_level_t memoryLevel, uint32_t mask);
606 
607 /*!
608  * @brief Locks MIF realted low power configuration fields for MIF module.
609  *
610  * @note After locked the low power configurations fields can not be updated unless POR.
611  *
612  * @param base PGMC MIF peripheral base address.
613  */
PGMC_MIF_LockLowPowerConfigurationFields(PGMC_MIF_Type * base)614 static inline void PGMC_MIF_LockLowPowerConfigurationFields(PGMC_MIF_Type *base)
615 {
616     base->MIF_AUTHEN_CTRL |= PGMC_MIF_MIF_AUTHEN_CTRL_LOCK_CFG_MASK;
617 }
618 
619 /*! @} */
620 
621 /*!
622  * @name PMIC Power Related Interfaces
623  * @{
624  */
625 
626 /*!
627  * @brief Trigger PMIC standby ON/OFF.
628  *
629  * @param base PMIC module base address.
630  * @param enable Trigger on/off PMIC standby.
631  *          - \b true Trigger PMIC standby ON.
632  *          - \b false Trigger PMIC standby OFF.
633  */
PGMC_PPC_TriggerPMICStandbySoftMode(PGMC_PPC_Type * base,bool enable)634 static inline void PGMC_PPC_TriggerPMICStandbySoftMode(PGMC_PPC_Type *base, bool enable)
635 {
636     if (enable)
637     {
638         base->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_ON_SOFT_MASK;
639     }
640     else
641     {
642         base->PPC_STBY_CM_CTRL |= PGMC_PPC_PPC_STBY_CM_CTRL_STBY_OFF_SOFT_MASK;
643     }
644 }
645 
646 /*!
647  * @brief Makes the PMIC module controlled by the target CPU power mode, such as Wait mode.
648  *
649  * @param base PMIC module base address.
650  * @param mode Target CPU power mode.
651  */
652 void PGMC_PPC_ControlByCpuPowerMode(PGMC_PPC_Type *base, pgmc_cpu_mode_t mode);
653 
654 /*!
655  * @brief Makes the PMIC module controlled by the target set points.
656  *
657  * This function makes the module controlled by specific set point, It also supports PMIC standby on.
658  *
659  * @note When setting more than one set point, use "|" between the map values in @ref _pgmc_setpoint_map.
660  *
661  * @param base PMIC module base address.
662  * @param setPointMap Should be the OR'ed value of @ref _pgmc_setpoint_map.
663  * @param enableStandby true: PMIC standby on when system enters set point number and system is in standby mode.
664  *                      false: PMIC standby on when system enters set point number
665  */
666 void PGMC_PPC_ControlBySetPointMode(PGMC_PPC_Type *base, uint32_t setPointMap, bool enableStandby);
667 
668 /*!
669  * @brief Disables low power mode control.
670  *
671  * @param base PMIC module bsase address.
672  */
PGMC_PPC_DisableLowPower(PGMC_PPC_Type * base)673 static inline void PGMC_PPC_DisableLowPower(PGMC_PPC_Type *base)
674 {
675     base->PPC_MODE = PGMC_PPC_PPC_MODE_CTRL_MODE(kPGMC_DisableLowPowerControl);
676 }
677 
678 /*!
679  * @brief Allows user mode access or not for PMIC module.
680  *
681  * @note If locked access related settings, the setting via this function is useless.
682  *
683  * @param base PMIC module base address.
684  * @param enable Used to control whether allow user mode access.
685  *           - \b true Allow both privilege and user mode to access CPU mode control registers.
686  *           - \b false Allow only privilege mode to access CPU mode control registers.
687  */
PGMC_PPC_AllowUserModeAccess(PGMC_PPC_Type * base,bool enable)688 static inline void PGMC_PPC_AllowUserModeAccess(PGMC_PPC_Type *base, bool enable)
689 {
690     if (enable)
691     {
692         base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK;
693     }
694     else
695     {
696         base->PPC_AUTHEN_CTRL &= ~PGMC_PPC_PPC_AUTHEN_CTRL_USER_MASK;
697     }
698 }
699 
700 /*!
701  * @brief Allows non-secure mode access or not for the PMIC module.
702  *
703  * @note If locked access related settings, the setting via this function is useless.
704  *
705  * @param base PMIC module base address.
706  * @param enable Used to control whether allow non-secure mode to access CPU mode control registers.
707  *           - \b true Allow both secure and non-secure mode to access CPU mode control registers.
708  *           - \b false Allow only secure mode to access CPU mode control registers.
709  */
PGMC_PPC_AllowNonSecureModeAccess(PGMC_PPC_Type * base,bool enable)710 static inline void PGMC_PPC_AllowNonSecureModeAccess(PGMC_PPC_Type *base, bool enable)
711 {
712     if (enable)
713     {
714         base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK;
715     }
716     else
717     {
718         base->PPC_AUTHEN_CTRL &= ~PGMC_PPC_PPC_AUTHEN_CTRL_NONSECURE_MASK;
719     }
720 }
721 
722 /*!
723  * @brief Locks access related settings, including secure access setting and user access setting, for the PMIC module.
724  *
725  * @note This function used to lock access related settings. After locked the related bit field
726  * can not be written unless POR.
727  *
728  * @param base PMIC module base address.
729  */
PGMC_PPC_LockAccessSetting(PGMC_PPC_Type * base)730 static inline void PGMC_PPC_LockAccessSetting(PGMC_PPC_Type *base)
731 {
732     base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_SETTING_MASK;
733 }
734 
735 /*!
736  * @brief Sets the corrsponding domain ID that can access CPU mode control registers for the PMIC module.
737  *
738  * @note If the domain ID whitelist is locked, the setting via this function is useless.
739  *
740  * @param base PMIC module base address.
741  * @param domainId Should be the OR'ed value of @ref pgmc_bpc_assign_domain_t.
742  */
PGMC_PPC_SetDomainIdWhiteList(PGMC_PPC_Type * base,uint8_t domainId)743 static inline void PGMC_PPC_SetDomainIdWhiteList(PGMC_PPC_Type *base, uint8_t domainId)
744 {
745     base->PPC_AUTHEN_CTRL = (base->PPC_AUTHEN_CTRL & (~PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST_MASK)) |
746                             PGMC_PPC_PPC_AUTHEN_CTRL_WHITE_LIST(domainId);
747 }
748 
749 /*!
750  * @brief Locks the value of Domain ID white list for the PMIC module.
751  *
752  * @note After locked the domain ID white list can not be written again unless POR.
753  *
754  * @param base PMIC module base address.
755  */
PGMC_PPC_LockDomainIDWhiteList(PGMC_PPC_Type * base)756 static inline void PGMC_PPC_LockDomainIDWhiteList(PGMC_PPC_Type *base)
757 {
758     base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_LIST_MASK;
759 }
760 
761 /*!
762  * @brief Locks low power configuration fields for the PMIC module.
763  *
764  * @note After locked the low power configurations fields can not be updated unless POR.
765  *
766  * @param base PMIC module base address.
767  */
PGMC_PPC_LockLowPowerConfigurationFields(PGMC_PPC_Type * base)768 static inline void PGMC_PPC_LockLowPowerConfigurationFields(PGMC_PPC_Type *base)
769 {
770     base->PPC_AUTHEN_CTRL |= PGMC_PPC_PPC_AUTHEN_CTRL_LOCK_CFG_MASK;
771 }
772 
773 /*!
774  * @}
775  */
776 
777 #if defined(__cplusplus)
778 }
779 #endif
780 /*!
781  * @}
782  */
783 #endif /* _FSL_PGMC_H_ */
784