1 /*
2 * Copyright 2016-2021 NXP
3 * All rights reserved.
4 *
5 * SPDX-License-Identifier: BSD-3-Clause
6 */
7 #ifndef _FSL_CACHE_H_
8 #define _FSL_CACHE_H_
9
10 #include "fsl_common.h"
11
12 /*!
13 * @addtogroup cache_armv7_m7
14 * @{
15 */
16
17 /*******************************************************************************
18 * Definitions
19 ******************************************************************************/
20
21 /*! @name Driver version */
22 /*@{*/
23 /*! @brief cache driver version 2.0.4. */
24 #define FSL_CACHE_DRIVER_VERSION (MAKE_VERSION(2, 0, 4))
25 /*@}*/
26
27 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
28 #ifndef FSL_SDK_DISBLE_L2CACHE_PRESENT
29 #define FSL_SDK_DISBLE_L2CACHE_PRESENT 0
30 #endif
31 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
32 /*******************************************************************************
33 * Definitions
34 ******************************************************************************/
35 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
36
37 /*! @brief Number of level 2 cache controller ways. */
38 typedef enum _l2cache_way_num
39 {
40 kL2CACHE_8ways = 0, /*!< 8 ways. */
41 #if defined(FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY) && FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY
42 kL2CACHE_16ways /*!< 16 ways. */
43 #endif /* FSL_FEATURE_L2CACHE_SUPPORT_16_WAY_ASSOCIATIVITY */
44 } l2cache_way_num_t;
45
46 /*! @brief Level 2 cache controller way size. */
47 typedef enum _l2cache_way_size
48 {
49 kL2CACHE_16KBSize = 1, /*!< 16 KB way size. */
50 kL2CACHE_32KBSize = 2, /*!< 32 KB way size. */
51 kL2CACHE_64KBSize = 3, /*!< 64 KB way size. */
52 kL2CACHE_128KBSize = 4, /*!< 128 KB way size. */
53 kL2CACHE_256KBSize = 5, /*!< 256 KB way size. */
54 kL2CACHE_512KBSize = 6 /*!< 512 KB way size. */
55 } l2cache_way_size;
56
57 /*! @brief Level 2 cache controller replacement policy. */
58 typedef enum _l2cache_replacement
59 {
60 kL2CACHE_Pseudorandom = 0U, /*!< Peseudo-random replacement policy using an lfsr. */
61 kL2CACHE_Roundrobin /*!< Round-robin replacemnt policy. */
62 } l2cache_replacement_t;
63
64 /*! @brief Level 2 cache controller force write allocate options. */
65 typedef enum _l2cache_writealloc
66 {
67 kL2CACHE_UseAwcache = 0, /*!< Use AWCAHE attribute for the write allocate. */
68 kL2CACHE_NoWriteallocate, /*!< Force no write allocate. */
69 kL2CACHE_forceWriteallocate /*!< Force write allocate when write misses. */
70 } l2cache_writealloc_t;
71
72 /*! @brief Level 2 cache controller tag/data ram latency. */
73 typedef enum _l2cache_latency
74 {
75 kL2CACHE_1CycleLate = 0, /*!< 1 cycle of latency. */
76 kL2CACHE_2CycleLate, /*!< 2 cycle of latency. */
77 kL2CACHE_3CycleLate, /*!< 3 cycle of latency. */
78 kL2CACHE_4CycleLate, /*!< 4 cycle of latency. */
79 kL2CACHE_5CycleLate, /*!< 5 cycle of latency. */
80 kL2CACHE_6CycleLate, /*!< 6 cycle of latency. */
81 kL2CACHE_7CycleLate, /*!< 7 cycle of latency. */
82 kL2CACHE_8CycleLate /*!< 8 cycle of latency. */
83 } l2cache_latency_t;
84
85 /*! @brief Level 2 cache controller tag/data ram latency configure structure. */
86 typedef struct _l2cache_latency_config
87 {
88 l2cache_latency_t tagWriteLate; /*!< Tag write latency. */
89 l2cache_latency_t tagReadLate; /*!< Tag Read latency. */
90 l2cache_latency_t tagSetupLate; /*!< Tag setup latency. */
91 l2cache_latency_t dataWriteLate; /*!< Data write latency. */
92 l2cache_latency_t dataReadLate; /*!< Data Read latency. */
93 l2cache_latency_t dataSetupLate; /*!< Data setup latency. */
94 } L2cache_latency_config_t;
95
96 /*! @brief Level 2 cache controller configure structure. */
97 typedef struct _l2cache_config
98 {
99 /* ------------------------ l2 cachec basic settings ---------------------------- */
100 l2cache_way_num_t wayNum; /*!< The number of ways. */
101 l2cache_way_size waySize; /*!< The way size = Cache Ram size / wayNum. */
102 l2cache_replacement_t repacePolicy; /*!< Replacemnet policy. */
103 /* ------------------------ tag/data ram latency settings ----------------------- */
104 L2cache_latency_config_t *lateConfig; /*!< Tag/data latency configure. Set NUll if not required. */
105 /* ------------------------ Prefetch enable settings ---------------------------- */
106 bool istrPrefetchEnable; /*!< Instruction prefetch enable. */
107 bool dataPrefetchEnable; /*!< Data prefetch enable. */
108 /* ------------------------ Non-secure access settings -------------------------- */
109 bool nsLockdownEnable; /*!< None-secure lockdown enable. */
110 /* ------------------------ other settings -------------------------------------- */
111 l2cache_writealloc_t writeAlloc; /*!< Write allcoate force option. */
112 } l2cache_config_t;
113 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
114 /*******************************************************************************
115 * API
116 ******************************************************************************/
117
118 #if defined(__cplusplus)
119 extern "C" {
120 #endif
121
122 /*!
123 * @name Control for cortex-m7 L1 cache
124 *@{
125 */
126
127 /*!
128 * @brief Enables cortex-m7 L1 instruction cache.
129 *
130 */
L1CACHE_EnableICache(void)131 static inline void L1CACHE_EnableICache(void)
132 {
133 SCB_EnableICache();
134 }
135
136 /*!
137 * @brief Disables cortex-m7 L1 instruction cache.
138 *
139 */
L1CACHE_DisableICache(void)140 static inline void L1CACHE_DisableICache(void)
141 {
142 if (SCB_CCR_IC_Msk == (SCB_CCR_IC_Msk & SCB->CCR))
143 {
144 SCB_DisableICache();
145 }
146 }
147
148 /*!
149 * @brief Invalidate cortex-m7 L1 instruction cache.
150 *
151 */
L1CACHE_InvalidateICache(void)152 static inline void L1CACHE_InvalidateICache(void)
153 {
154 SCB_InvalidateICache();
155 }
156
157 /*!
158 * @brief Invalidate cortex-m7 L1 instruction cache by range.
159 *
160 * @param address The start address of the memory to be invalidated.
161 * @param size_byte The memory size.
162 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1ICACHE_LINESIZE_BYTE) aligned.
163 * The startAddr here will be forced to align to L1 I-cache line size if
164 * startAddr is not aligned. For the size_byte, application should make sure the
165 * alignment or make sure the right operation order if the size_byte is not aligned.
166 */
167 void L1CACHE_InvalidateICacheByRange(uint32_t address, uint32_t size_byte);
168
169 /*!
170 * @brief Enables cortex-m7 L1 data cache.
171 *
172 */
L1CACHE_EnableDCache(void)173 static inline void L1CACHE_EnableDCache(void)
174 {
175 SCB_EnableDCache();
176 }
177
178 /*!
179 * @brief Disables cortex-m7 L1 data cache.
180 *
181 */
L1CACHE_DisableDCache(void)182 static inline void L1CACHE_DisableDCache(void)
183 {
184 if (SCB_CCR_DC_Msk == (SCB_CCR_DC_Msk & SCB->CCR))
185 {
186 SCB_DisableDCache();
187 }
188 }
189
190 /*!
191 * @brief Invalidates cortex-m7 L1 data cache.
192 *
193 */
L1CACHE_InvalidateDCache(void)194 static inline void L1CACHE_InvalidateDCache(void)
195 {
196 SCB_InvalidateDCache();
197 }
198
199 /*!
200 * @brief Cleans cortex-m7 L1 data cache.
201 *
202 */
L1CACHE_CleanDCache(void)203 static inline void L1CACHE_CleanDCache(void)
204 {
205 SCB_CleanDCache();
206 }
207
208 /*!
209 * @brief Cleans and Invalidates cortex-m7 L1 data cache.
210 *
211 */
L1CACHE_CleanInvalidateDCache(void)212 static inline void L1CACHE_CleanInvalidateDCache(void)
213 {
214 SCB_CleanInvalidateDCache();
215 }
216
217 /*!
218 * @brief Invalidates cortex-m7 L1 data cache by range.
219 *
220 * @param address The start address of the memory to be invalidated.
221 * @param size_byte The memory size.
222 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
223 * The startAddr here will be forced to align to L1 D-cache line size if
224 * startAddr is not aligned. For the size_byte, application should make sure the
225 * alignment or make sure the right operation order if the size_byte is not aligned.
226 */
L1CACHE_InvalidateDCacheByRange(uint32_t address,uint32_t size_byte)227 static inline void L1CACHE_InvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
228 {
229 SCB_InvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
230 }
231
232 /*!
233 * @brief Cleans cortex-m7 L1 data cache by range.
234 *
235 * @param address The start address of the memory to be cleaned.
236 * @param size_byte The memory size.
237 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
238 * The startAddr here will be forced to align to L1 D-cache line size if
239 * startAddr is not aligned. For the size_byte, application should make sure the
240 * alignment or make sure the right operation order if the size_byte is not aligned.
241 */
L1CACHE_CleanDCacheByRange(uint32_t address,uint32_t size_byte)242 static inline void L1CACHE_CleanDCacheByRange(uint32_t address, uint32_t size_byte)
243 {
244 SCB_CleanDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
245 }
246
247 /*!
248 * @brief Cleans and Invalidates cortex-m7 L1 data cache by range.
249 *
250 * @param address The start address of the memory to be clean and invalidated.
251 * @param size_byte The memory size.
252 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L1DCACHE_LINESIZE_BYTE) aligned.
253 * The startAddr here will be forced to align to L1 D-cache line size if
254 * startAddr is not aligned. For the size_byte, application should make sure the
255 * alignment or make sure the right operation order if the size_byte is not aligned.
256 */
L1CACHE_CleanInvalidateDCacheByRange(uint32_t address,uint32_t size_byte)257 static inline void L1CACHE_CleanInvalidateDCacheByRange(uint32_t address, uint32_t size_byte)
258 {
259 SCB_CleanInvalidateDCache_by_Addr((uint32_t *)address, (int32_t)size_byte);
260 }
261 /*@}*/
262
263 #if defined(FSL_FEATURE_SOC_L2CACHEC_COUNT) && FSL_FEATURE_SOC_L2CACHEC_COUNT
264 /*!
265 * @name Control for L2 pl310 cache
266 *@{
267 */
268
269 /*!
270 * @brief Initializes the level 2 cache controller module.
271 *
272 * @param config Pointer to configuration structure. See "l2cache_config_t".
273 */
274 void L2CACHE_Init(l2cache_config_t *config);
275
276 /*!
277 * @brief Gets an available default settings for the cache controller.
278 *
279 * This function initializes the cache controller configuration structure with default settings.
280 * The default values are:
281 * @code
282 * config->waysNum = kL2CACHE_8ways;
283 * config->waySize = kL2CACHE_32KbSize;
284 * config->repacePolicy = kL2CACHE_Roundrobin;
285 * config->lateConfig = NULL;
286 * config->istrPrefetchEnable = false;
287 * config->dataPrefetchEnable = false;
288 * config->nsLockdownEnable = false;
289 * config->writeAlloc = kL2CACHE_UseAwcache;
290 * @endcode
291 * @param config Pointer to the configuration structure.
292 */
293 void L2CACHE_GetDefaultConfig(l2cache_config_t *config);
294
295 /*!
296 * @brief Enables the level 2 cache controller.
297 * This function enables the cache controller. Must be written using a secure access.
298 * If write with a Non-secure access will cause a DECERR response.
299 *
300 */
301 void L2CACHE_Enable(void);
302
303 /*!
304 * @brief Disables the level 2 cache controller.
305 * This function disables the cache controller. Must be written using a secure access.
306 * If write with a Non-secure access will cause a DECERR response.
307 *
308 */
309 void L2CACHE_Disable(void);
310
311 /*!
312 * @brief Invalidates the Level 2 cache.
313 * This function invalidates all entries in cache.
314 *
315 */
316 void L2CACHE_Invalidate(void);
317
318 /*!
319 * @brief Invalidates the Level 2 cache lines in the range of two physical addresses.
320 * This function invalidates all cache lines between two physical addresses.
321 *
322 * @param address The start address of the memory to be invalidated.
323 * @param size_byte The memory size.
324 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
325 * The startAddr here will be forced to align to L2 line size if startAddr
326 * is not aligned. For the size_byte, application should make sure the
327 * alignment or make sure the right operation order if the size_byte is not aligned.
328 */
329 void L2CACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
330
331 /*!
332 * @brief Cleans the level 2 cache controller.
333 * This function cleans all entries in the level 2 cache controller.
334 *
335 */
336 void L2CACHE_Clean(void);
337
338 /*!
339 * @brief Cleans the Level 2 cache lines in the range of two physical addresses.
340 * This function cleans all cache lines between two physical addresses.
341 *
342 * @param address The start address of the memory to be cleaned.
343 * @param size_byte The memory size.
344 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
345 * The startAddr here will be forced to align to L2 line size if startAddr
346 * is not aligned. For the size_byte, application should make sure the
347 * alignment or make sure the right operation order if the size_byte is not aligned.
348 */
349 void L2CACHE_CleanByRange(uint32_t address, uint32_t size_byte);
350
351 /*!
352 * @brief Cleans and invalidates the level 2 cache controller.
353 * This function cleans and invalidates all entries in the level 2 cache controller.
354 *
355 */
356 void L2CACHE_CleanInvalidate(void);
357
358 /*!
359 * @brief Cleans and invalidates the Level 2 cache lines in the range of two physical addresses.
360 * This function cleans and invalidates all cache lines between two physical addresses.
361 *
362 * @param address The start address of the memory to be cleaned and invalidated.
363 * @param size_byte The memory size.
364 * @note The start address and size_byte should be 32-byte(FSL_FEATURE_L2CACHE_LINESIZE_BYTE) aligned.
365 * The startAddr here will be forced to align to L2 line size if startAddr
366 * is not aligned. For the size_byte, application should make sure the
367 * alignment or make sure the right operation order if the size_byte is not aligned.
368 */
369 void L2CACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
370
371 /*!
372 * @brief Enables or disables to lock down the data and instruction by way.
373 * This function locks down the cached instruction/data by way and prevent the adresses from
374 * being allocated and prevent dara from being evicted out of the level 2 cache.
375 * But the normal cache maintenance operations that invalidate, clean or clean
376 * and validate cache contents affect the locked-down cache lines as normal.
377 *
378 * @param masterId The master id, range from 0 ~ 7.
379 * @param mask The ways to be enabled or disabled to lockdown.
380 * each bit in value is related to each way of the cache. for example:
381 * value: bit 0 ------ way 0.
382 * value: bit 1 ------ way 1.
383 * --------------------------
384 * value: bit 15 ------ way 15.
385 * Note: please make sure the value setting is align with your supported ways.
386 * @param enable True enable the lockdown, false to disable the lockdown.
387 */
388 void L2CACHE_LockdownByWayEnable(uint32_t masterId, uint32_t mask, bool enable);
389
390 /*@}*/
391 #endif /* FSL_FEATURE_SOC_L2CACHEC_COUNT */
392
393 /*!
394 * @name Unified Cache Control for all caches (cortex-m7 L1 cache + l2 pl310)
395 * Mainly used for many drivers for easy cache operation.
396 *@{
397 */
398
399 /*!
400 * @brief Invalidates all instruction caches by range.
401 *
402 * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
403 *
404 * @param address The physical address.
405 * @param size_byte size of the memory to be invalidated.
406 * @note address and size should be aligned to cache line size
407 * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
408 * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
409 * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
410 */
411 void ICACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
412
413 /*!
414 * @brief Invalidates all data caches by range.
415 *
416 * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
417 *
418 * @param address The physical address.
419 * @param size_byte size of the memory to be invalidated.
420 * @note address and size should be aligned to cache line size
421 * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
422 * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
423 * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
424 */
425 void DCACHE_InvalidateByRange(uint32_t address, uint32_t size_byte);
426
427 /*!
428 * @brief Cleans all data caches by range.
429 *
430 * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
431 *
432 * @param address The physical address.
433 * @param size_byte size of the memory to be cleaned.
434 * @note address and size should be aligned to cache line size
435 * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
436 * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
437 * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
438 */
439 void DCACHE_CleanByRange(uint32_t address, uint32_t size_byte);
440
441 /*!
442 * @brief Cleans and Invalidates all data caches by range.
443 *
444 * Both cortex-m7 L1 cache line and L2 PL310 cache line length is 32-byte.
445 *
446 * @param address The physical address.
447 * @param size_byte size of the memory to be cleaned and invalidated.
448 * @note address and size should be aligned to cache line size
449 * 32-Byte due to the cache operation unit is one cache line. The startAddr here will be forced
450 * to align to the cache line size if startAddr is not aligned. For the size_byte, application should
451 * make sure the alignment or make sure the right operation order if the size_byte is not aligned.
452 */
453 void DCACHE_CleanInvalidateByRange(uint32_t address, uint32_t size_byte);
454
455 /*@}*/
456
457 #if defined(__cplusplus)
458 }
459 #endif
460
461 /*! @}*/
462
463 #endif /* _FSL_CACHE_H_*/
464
