1 /*
2 * Copyright 2020-2021, 2023 NXP
3 * All rights reserved.
4 *
5 *
6 * SPDX-License-Identifier: BSD-3-Clause
7 */
8
9 #include "fsl_dcdc.h"
10
11 /* Component ID definition, used by tools. */
12 #ifndef FSL_COMPONENT_ID
13 #define FSL_COMPONENT_ID "platform.drivers.dcdc_soc"
14 #endif
15
16 /*******************************************************************************
17 * Prototypes
18 ******************************************************************************/
19 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
20 /*!
21 * brief Gets instance number for DCDC module.
22 *
23 * param base DCDC peripheral base address
24 */
25 static uint32_t DCDC_GetInstance(DCDC_Type *base);
26 #endif /* defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
27
28 /*!
29 * brief Converts the byte array to word.
30 *
31 * param ptrArray Pointer to the byte array.
32 * return The converted result.
33 */
34 static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray);
35
36 /*******************************************************************************
37 * Variables
38 ******************************************************************************/
39 /*! brief Pointers to DCDC bases for each instance. */
40 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
41 static DCDC_Type *const s_dcdcBases[] = DCDC_BASE_PTRS;
42 /*! brief Pointers to DCDC clocks for each instance. */
43 static const clock_ip_name_t s_dcdcClocks[] = DCDC_CLOCKS;
44 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
45
46 /*******************************************************************************
47 * CodDCDC_GetstatusFlagse
48 ******************************************************************************/
49
50 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
DCDC_GetInstance(DCDC_Type * base)51 static uint32_t DCDC_GetInstance(DCDC_Type *base)
52 {
53 uint32_t instance;
54
55 /* Find the instance index from base address mappings. */
56 for (instance = 0; instance < ARRAY_SIZE(s_dcdcBases); instance++)
57 {
58 if (s_dcdcBases[instance] == base)
59 {
60 break;
61 }
62 }
63
64 assert(instance < ARRAY_SIZE(s_dcdcBases));
65
66 return instance;
67 }
68 #endif /* defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
69
DCDC_ConvertByteArrayToWord(uint8_t * ptrArray)70 static uint32_t DCDC_ConvertByteArrayToWord(uint8_t *ptrArray)
71 {
72 assert(ptrArray != NULL);
73
74 uint32_t temp32 = 0UL;
75 uint32_t index;
76
77 for (index = 0U; index < 4U; index++)
78 {
79 temp32 |= (uint32_t)ptrArray[index] << ((index % 4UL) * 8UL);
80 }
81
82 return temp32;
83 }
84
85 /*!
86 * brief Initializes the basic resource of DCDC module, such as control mode, etc.
87 *
88 * param base DCDC peripheral base address.
89 * param config Pointer to the configuration structure.
90 */
DCDC_Init(DCDC_Type * base,const dcdc_config_t * config)91 void DCDC_Init(DCDC_Type *base, const dcdc_config_t *config)
92 {
93 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
94 /* Enable the clock. */
95 CLOCK_EnableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
96 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
97
98 uint32_t tmp32 = base->CTRL0;
99
100 tmp32 |= DCDC_CTRL0_CONTROL_MODE(config->controlMode) | DCDC_CTRL0_TRIM_HOLD(config->trimInputMode);
101
102 if (config->enableDcdcTimeout)
103 {
104 tmp32 |= DCDC_CTRL0_ENABLE_DCDC_CNT_MASK;
105 }
106 if (config->enableSwitchingConverterOutput)
107 {
108 tmp32 |= DCDC_CTRL0_DIG_EN_MASK;
109 }
110 tmp32 |= DCDC_CTRL0_ENABLE_MASK;
111 base->CTRL0 = tmp32;
112 }
113
114 /*!
115 * brief De-initializes the DCDC module.
116 *
117 * param base DCDC peripheral base address.
118 */
DCDC_Deinit(DCDC_Type * base)119 void DCDC_Deinit(DCDC_Type *base)
120 {
121 /* Disables DCDC. */
122 base->CTRL0 &= ~DCDC_CTRL0_ENABLE_MASK;
123 #if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
124 /* Disable the clock. */
125 CLOCK_DisableClock(s_dcdcClocks[DCDC_GetInstance(base)]);
126 #endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
127 }
128
129 /*!
130 * brief Gets the default setting for DCDC, such as control mode, etc.
131 *
132 * This function initializes the user configuration structure to a default value. The default values are:
133 * code
134 * config->controlMode = kDCDC_StaticControl;
135 * config->trimInputMode = kDCDC_SampleTrimInput;
136 * config->enableDcdcTimeout = false;
137 * config->enableSwitchingConverterOutput = false;
138 * endcode
139 *
140 * param config Pointer to configuration structure. See to dcdc_config_t.
141 */
DCDC_GetDefaultConfig(dcdc_config_t * config)142 void DCDC_GetDefaultConfig(dcdc_config_t *config)
143 {
144 assert(NULL != config);
145
146 /* Initializes the configure structure to zero. */
147 (void)memset(config, 0, sizeof(*config));
148
149 config->controlMode = kDCDC_StaticControl;
150 config->trimInputMode = kDCDC_SampleTrimInput;
151 config->enableDcdcTimeout = false;
152 config->enableSwitchingConverterOutput = false;
153 }
154
155 /*!
156 * brief Gets the default setting for detection configuration.
157 *
158 * The default configuration are set according to responding registers' setting when powered on.
159 * They are:
160 * code
161 * config->enableXtalokDetection = false;
162 * config->powerDownOverVoltageVdd1P8Detection = true;
163 * config->powerDownOverVoltageVdd1P0Detection = true;
164 * config->powerDownLowVoltageDetection = false;
165 * config->powerDownOverCurrentDetection = true;
166 * config->powerDownPeakCurrentDetection = true;
167 * config->powerDownZeroCrossDetection = true;
168 * config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
169 * endcode
170 *
171 * param config Pointer to configuration structure. See to "dcdc_detection_config_t"
172 */
DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t * config)173 void DCDC_GetDefaultDetectionConfig(dcdc_detection_config_t *config)
174 {
175 assert(NULL != config);
176
177 /* Initializes the configure structure to zero. */
178 (void)memset(config, 0, sizeof(*config));
179
180 config->enableXtalokDetection = false;
181 config->powerDownOverVoltageVdd1P8Detection = true;
182 config->powerDownOverVoltageVdd1P0Detection = true;
183 config->powerDownLowVoltageDetection = false;
184 config->powerDownOverCurrentDetection = true;
185 config->powerDownPeakCurrentDetection = true;
186 config->powerDownZeroCrossDetection = true;
187 config->PeakCurrentThreshold = kDCDC_PeakCurrentRunMode250mALPMode1P5A;
188 }
189
190 /*!
191 * breif Configures the DCDC detection.
192 *
193 * param base DCDC peripheral base address.
194 * param config Pointer to configuration structure. See to "dcdc_detection_config_t"
195 */
DCDC_SetDetectionConfig(DCDC_Type * base,const dcdc_detection_config_t * config)196 void DCDC_SetDetectionConfig(DCDC_Type *base, const dcdc_detection_config_t *config)
197 {
198 assert(NULL != config);
199
200 uint32_t tmp32;
201 /* Configure the DCDC_REG0 register. */
202 tmp32 = base->REG0 &
203 ~(DCDC_REG0_XTALOK_DISABLE_MASK | DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK | DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK |
204 DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK | DCDC_REG0_PWD_OVERCUR_DET_MASK | DCDC_REG0_PWD_CUR_SNS_CMP_MASK |
205 DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_CUR_SNS_THRSH_MASK);
206
207 tmp32 |= DCDC_REG0_CUR_SNS_THRSH(config->PeakCurrentThreshold);
208 if (false == config->enableXtalokDetection)
209 {
210 tmp32 |= DCDC_REG0_XTALOK_DISABLE_MASK;
211 }
212 if (config->powerDownOverVoltageVdd1P8Detection)
213 {
214 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P8_DET_MASK;
215 }
216 if (config->powerDownOverVoltageVdd1P0Detection)
217 {
218 tmp32 |= DCDC_REG0_PWD_HIGH_VDD1P0_DET_MASK;
219 }
220 if (config->powerDownLowVoltageDetection)
221 {
222 tmp32 |= DCDC_REG0_PWD_CMP_DCDC_IN_DET_MASK;
223 }
224 if (config->powerDownOverCurrentDetection)
225 {
226 tmp32 |= DCDC_REG0_PWD_OVERCUR_DET_MASK;
227 }
228 if (config->powerDownPeakCurrentDetection)
229 {
230 tmp32 |= DCDC_REG0_PWD_CUR_SNS_CMP_MASK;
231 }
232 if (config->powerDownZeroCrossDetection)
233 {
234 tmp32 |= DCDC_REG0_PWD_ZCD_MASK;
235 }
236 base->REG0 = tmp32;
237 }
238
239 /*!
240 * brief Configures the DCDC clock source.
241 *
242 * param base DCDC peripheral base address.
243 * param clockSource Clock source for DCDC. See to "dcdc_clock_source_t".
244 */
DCDC_SetClockSource(DCDC_Type * base,dcdc_clock_source_t clockSource)245 void DCDC_SetClockSource(DCDC_Type *base, dcdc_clock_source_t clockSource)
246 {
247 uint32_t tmp32;
248
249 /* Configure the DCDC_REG0 register. */
250 tmp32 = base->REG0 & ~(DCDC_REG0_XTAL_24M_OK_MASK | DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK |
251 DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK);
252 switch (clockSource)
253 {
254 case kDCDC_ClockInternalOsc:
255 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK;
256 break;
257 case kDCDC_ClockExternalOsc:
258 /* Choose the external clock and disable the internal clock. */
259 tmp32 |= DCDC_REG0_DISABLE_AUTO_CLK_SWITCH_MASK | DCDC_REG0_SEL_CLK_MASK | DCDC_REG0_PWD_OSC_INT_MASK;
260 break;
261 case kDCDC_ClockAutoSwitch:
262 /* Set to switch from internal ring osc to xtal 24M if auto mode is enabled. */
263 tmp32 |= DCDC_REG0_XTAL_24M_OK_MASK;
264 break;
265 default:
266 assert(false);
267 break;
268 }
269 base->REG0 = tmp32;
270 }
271
272 /*!
273 * brief Gets the default setting for low power configuration.
274 *
275 * The default configuration are set according to responding registers' setting when powered on.
276 * They are:
277 * code
278 * config->enableAdjustHystereticValue = false;
279 * endcode
280 *
281 * param config Pointer to configuration structure. See to "dcdc_low_power_config_t"
282 */
DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t * config)283 void DCDC_GetDefaultLowPowerConfig(dcdc_low_power_config_t *config)
284 {
285 assert(NULL != config);
286
287 /* Initializes the configure structure to zero. */
288 (void)memset(config, 0, sizeof(*config));
289 config->enableAdjustHystereticValue = false;
290 }
291
292 /*!
293 * brief Configures the DCDC low power.
294 *
295 * param base DCDC peripheral base address.
296 * param config Pointer to configuration structure. See to "dcdc_low_power_config_t".
297 */
DCDC_SetLowPowerConfig(DCDC_Type * base,const dcdc_low_power_config_t * config)298 void DCDC_SetLowPowerConfig(DCDC_Type *base, const dcdc_low_power_config_t *config)
299 {
300 assert(NULL != config);
301
302 uint32_t tmp32;
303 /* Configure the DCDC_REG0 register. */
304 tmp32 = base->REG0 & ~(DCDC_REG0_LP_HIGH_HYS_MASK);
305
306 if (config->enableAdjustHystereticValue)
307 {
308 tmp32 |= DCDC_REG0_LP_HIGH_HYS_MASK;
309 }
310 base->REG0 = tmp32;
311 }
312
313 /*!
314 * brief Gets the default setting for loop control configuration.
315 *
316 * The default configuration are set according to responding registers' setting when powered on.
317 * They are:
318 * code
319 * config->enableCommonHysteresis = false;
320 * config->enableCommonThresholdDetection = false;
321 * config->enableInvertHysteresisSign = false;
322 * config->enableRCThresholdDetection = false;
323 * config->enableRCScaleCircuit = 0U;
324 * config->complementFeedForwardStep = 0U;
325 * config->controlParameterMagnitude = 2U;
326 * config->integralProportionalRatio = 2U;
327 * endcode
328 *
329 * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t"
330 */
DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t * config)331 void DCDC_GetDefaultLoopControlConfig(dcdc_loop_control_config_t *config)
332 {
333 assert(NULL != config);
334
335 /* Initializes the configure structure to zero. */
336 (void)memset(config, 0, sizeof(*config));
337
338 config->enableCommonHysteresis = false;
339 config->enableCommonThresholdDetection = false;
340 config->enableInvertHysteresisSign = false;
341 config->enableRCThresholdDetection = false;
342 config->enableRCScaleCircuit = 0U;
343 config->complementFeedForwardStep = 0U;
344 config->controlParameterMagnitude = 2U;
345 config->integralProportionalRatio = 2U;
346 }
347
348 /*!
349 * brief Configures the DCDC loop control.
350 *
351 * param base DCDC peripheral base address.
352 * param config Pointer to configuration structure. See to "dcdc_loop_control_config_t".
353 */
DCDC_SetLoopControlConfig(DCDC_Type * base,const dcdc_loop_control_config_t * config)354 void DCDC_SetLoopControlConfig(DCDC_Type *base, const dcdc_loop_control_config_t *config)
355 {
356 assert(NULL != config);
357
358 uint32_t tmp32;
359
360 /* Configure the DCDC_REG1 register. */
361 tmp32 = base->REG1 & ~(DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK | DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK |
362 DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK | DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK);
363 if (config->enableCommonHysteresis)
364 {
365 tmp32 |= DCDC_REG1_LOOPCTRL_EN_CM_HYST_MASK;
366 }
367 if (config->enableCommonThresholdDetection)
368 {
369 tmp32 |= DCDC_REG1_LOOPCTRL_CM_HST_THRESH_MASK;
370 }
371 if (config->enableDifferentialHysteresis)
372 {
373 tmp32 |= DCDC_REG1_LOOPCTRL_EN_DF_HYST_MASK;
374 }
375 if (config->enableDifferentialThresholdDetection)
376 {
377 tmp32 |= DCDC_REG1_LOOPCTRL_DF_HST_THRESH_MASK;
378 }
379
380 base->REG1 = tmp32;
381
382 /* configure the DCDC_REG2 register. */
383 tmp32 = base->REG2 & ~(DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK | DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK |
384 DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK | DCDC_REG2_LOOPCTRL_DC_FF_MASK |
385 DCDC_REG2_LOOPCTRL_DC_R_MASK | DCDC_REG2_LOOPCTRL_DC_C_MASK);
386 tmp32 |= DCDC_REG2_LOOPCTRL_DC_FF(config->complementFeedForwardStep) |
387 DCDC_REG2_LOOPCTRL_DC_R(config->controlParameterMagnitude) |
388 DCDC_REG2_LOOPCTRL_DC_C(config->integralProportionalRatio) |
389 DCDC_REG2_LOOPCTRL_EN_RCSCALE(config->enableRCScaleCircuit);
390 if (config->enableInvertHysteresisSign)
391 {
392 tmp32 |= DCDC_REG2_LOOPCTRL_HYST_SIGN_MASK;
393 }
394 if (config->enableRCThresholdDetection)
395 {
396 tmp32 |= DCDC_REG2_LOOPCTRL_RCSCALE_THRSH_MASK;
397 }
398 base->REG2 = tmp32;
399 }
400
401 /*!
402 * brief Configures for the min power.
403 *
404 * param base DCDC peripheral base address.
405 * param config Pointer to configuration structure. See to "dcdc_min_power_config_t".
406 */
DCDC_SetMinPowerConfig(DCDC_Type * base,const dcdc_min_power_config_t * config)407 void DCDC_SetMinPowerConfig(DCDC_Type *base, const dcdc_min_power_config_t *config)
408 {
409 assert(NULL != config);
410
411 uint32_t tmp32;
412
413 tmp32 = base->REG3 & ~DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
414 if (config->enableUseHalfFreqForContinuous)
415 {
416 tmp32 |= DCDC_REG3_MINPWR_DC_HALFCLK_MASK;
417 }
418 base->REG3 = tmp32;
419 }
420
421 /*!
422 * brief Configures the DCDC internal regulator.
423 *
424 * param base DCDC peripheral base address.
425 * param config Pointer to configuration structure. See to "dcdc_internal_regulator_config_t".
426 */
DCDC_SetInternalRegulatorConfig(DCDC_Type * base,const dcdc_internal_regulator_config_t * config)427 void DCDC_SetInternalRegulatorConfig(DCDC_Type *base, const dcdc_internal_regulator_config_t *config)
428 {
429 assert(NULL != config);
430
431 uint32_t tmp32;
432
433 tmp32 = base->REG3 & ~DCDC_REG3_REG_FBK_SEL_MASK;
434 tmp32 |= DCDC_REG3_REG_FBK_SEL(config->feedbackPoint);
435 base->REG3 = tmp32;
436 }
437
438 /*!
439 * brief Initializes DCDC module when the control mode selected as setpoint mode.
440 *
441 * note The function should be invoked in the initial step to config the
442 * DCDC via setpoint control mode.
443 *
444 * param base DCDC peripheral base address.
445 * param config The pointer to the structure dcdc_setpoint_config_t.
446 */
DCDC_SetPointInit(DCDC_Type * base,const dcdc_setpoint_config_t * config)447 void DCDC_SetPointInit(DCDC_Type *base, const dcdc_setpoint_config_t *config)
448 {
449 assert(config != NULL);
450
451 /* Enable DCDC Dig Logic. */
452 base->REG5 = config->enableDigLogicMap;
453
454 /* Set DCDC power mode. */
455 base->REG6 = config->lowpowerMap;
456 base->REG7 = config->standbyMap;
457 base->REG7P = config->standbyLowpowerMap;
458
459 /* Set target voltage of VDD1P8 in buck mode. */
460 base->REG8 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage);
461 base->REG9 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 4U);
462 base->REG10 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 8U);
463 base->REG11 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P8TargetVoltage + 12U);
464
465 /* Set target voltage of VDD1P0 in buck mode. */
466 base->REG12 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage);
467 base->REG13 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 4U);
468 base->REG14 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 8U);
469 base->REG15 = DCDC_ConvertByteArrayToWord((uint8_t *)config->buckVDD1P0TargetVoltage + 12U);
470
471 /* Set target voltage of VDD1P8 in low power mode. */
472 base->REG16 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage);
473 base->REG17 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 4U);
474 base->REG18 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 8U);
475 base->REG19 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P8TargetVoltage + 12U);
476
477 /* Set target voltage of VDD1P0 in low power mode. */
478 base->REG20 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage);
479 base->REG21 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 4U);
480 base->REG22 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 8U);
481 base->REG23 = DCDC_ConvertByteArrayToWord((uint8_t *)config->standbyVDD1P0TargetVoltage + 12U);
482
483 /* Enable DCDC module. */
484 base->REG4 = config->enableDCDCMap;
485 }
486
487 /*!
488 * brief Boots DCDC into DCM(discontinous conduction mode).
489 *
490 * pwd_zcd=0x0;
491 * DM_CTRL = 1'b1;
492 * pwd_cmp_offset=0x0;
493 * dcdc_loopctrl_en_rcscale=0x3 or 0x5;
494 * DCM_set_ctrl=1'b1;
495 *
496 * param base DCDC peripheral base address.
497 */
DCDC_BootIntoDCM(DCDC_Type * base)498 void DCDC_BootIntoDCM(DCDC_Type *base)
499 {
500 base->REG0 &= ~(DCDC_REG0_PWD_ZCD_MASK | DCDC_REG0_PWD_CMP_OFFSET_MASK);
501 base->REG1 &= ~DCDC_REG1_RLOAD_REG_EN_LPSR_MASK;
502 base->REG1 |= DCDC_REG1_DM_CTRL_MASK;
503 base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x5U);
504 base->REG3 &= ~(DCDC_REG3_DISABLE_IDLE_SKIP_MASK | DCDC_REG3_DISABLE_PULSE_SKIP_MASK);
505 base->REG3 |= DCDC_REG3_ENABLE_FF_MASK;
506 }
507
508 /*!
509 * brief Boots DCDC into CCM(continous conduction mode).
510 *
511 * pwd_zcd=0x1;
512 * pwd_cmp_offset=0x0;
513 * dcdc_loopctrl_en_rcscale=0x3;
514 *
515 * param base DCDC peripheral base address.
516 */
DCDC_BootIntoCCM(DCDC_Type * base)517 void DCDC_BootIntoCCM(DCDC_Type *base)
518 {
519 base->REG0 = (~DCDC_REG0_PWD_CMP_OFFSET_MASK & base->REG0) | DCDC_REG0_PWD_ZCD_MASK;
520 base->REG2 = (~DCDC_REG2_LOOPCTRL_EN_RCSCALE_MASK & base->REG2) | DCDC_REG2_LOOPCTRL_EN_RCSCALE(0x3U);
521 }
522
