1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1064CVJ5A
4 ** MIMXRT1064CVL5A
5 ** MIMXRT1064DVJ6A
6 ** MIMXRT1064DVL6A
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1064RM Rev.2, 07/2021 | IMXRT106XSRM Rev.0
15 ** Version: rev. 1.3, 2021-08-10
16 ** Build: b210811
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2021 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 0.1 (2018-06-22)
34 ** Initial version.
35 ** - rev. 1.0 (2018-11-16)
36 ** Update header files to align with IMXRT1064RM Rev.0.
37 ** - rev. 1.1 (2018-11-27)
38 ** Update header files to align with IMXRT1064RM Rev.0.1.
39 ** - rev. 1.2 (2019-04-29)
40 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
41 ** - rev. 1.3 (2021-08-10)
42 ** Update header files to align with IMXRT1064RM Rev.2.
43 **
44 ** ###################################################################
45 */
46
47 /*!
48 * @file MIMXRT1064
49 * @version 1.3
50 * @date 2021-08-10
51 * @brief Device specific configuration file for MIMXRT1064 (implementation file)
52 *
53 * Provides a system configuration function and a global variable that contains
54 * the system frequency. It configures the device and initializes the oscillator
55 * (PLL) that is part of the microcontroller device.
56 */
57
58 #include <stdint.h>
59 #include "fsl_device_registers.h"
60
61
62
63 /* ----------------------------------------------------------------------------
64 -- Core clock
65 ---------------------------------------------------------------------------- */
66
67 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
68
69 /* ----------------------------------------------------------------------------
70 -- SystemInit()
71 ---------------------------------------------------------------------------- */
72
SystemInit(void)73 void SystemInit (void) {
74 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
75 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
76 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
77
78 #if defined(__MCUXPRESSO)
79 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
80 SCB->VTOR = (uint32_t)g_pfnVectors;
81 #endif
82
83 /* Disable Watchdog Power Down Counter */
84 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
85 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
86
87 /* Watchdog disable */
88
89 #if (DISABLE_WDOG)
90 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
91 {
92 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
93 }
94 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
95 {
96 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
97 }
98 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
99 {
100 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
101 }
102 else
103 {
104 RTWDOG->CNT = 0xC520U;
105 RTWDOG->CNT = 0xD928U;
106 }
107 RTWDOG->TOVAL = 0xFFFF;
108 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
109 #endif /* (DISABLE_WDOG) */
110
111 /* Disable Systick which might be enabled by bootrom */
112 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
113 {
114 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
115 }
116
117 /* Enable instruction and data caches */
118 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
119 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
120 SCB_EnableICache();
121 }
122 #endif
123
124 SystemInitHook();
125 }
126
127 /* ----------------------------------------------------------------------------
128 -- SystemCoreClockUpdate()
129 ---------------------------------------------------------------------------- */
130
SystemCoreClockUpdate(void)131 void SystemCoreClockUpdate (void) {
132
133 uint32_t freq;
134 uint32_t PLL1MainClock;
135 uint32_t PLL2MainClock;
136
137 /* Periph_clk2_clk ---> Periph_clk */
138 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
139 {
140 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
141 {
142 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
143 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
144 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
145 {
146 freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
147 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
148 }
149 else
150 {
151 freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
152 }
153 break;
154
155 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
156 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
157 freq = CPU_XTAL_CLK_HZ;
158 break;
159
160 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
161 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
162 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
163 break;
164
165 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
166 default:
167 freq = 0U;
168 break;
169 }
170
171 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
172 }
173 /* Pre_Periph_clk ---> Periph_clk */
174 else
175 {
176 /* check if pll is bypassed */
177 if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U)
178 {
179 PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
180 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
181 }
182 else
183 {
184 PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
185 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
186 }
187
188 /* check if pll is bypassed */
189 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
190 {
191 PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
192 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
193 }
194 else
195 {
196 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
197 }
198 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
199
200 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
201 {
202 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
203 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
204 freq = PLL2MainClock;
205 break;
206
207 /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
208 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
209 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
210 break;
211
212 /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
213 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
214 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
215 break;
216
217 /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
218 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
219 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
220 break;
221
222 default:
223 freq = 0U;
224 break;
225 }
226 }
227
228 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
229
230 }
231
232 /* ----------------------------------------------------------------------------
233 -- SystemInitHook()
234 ---------------------------------------------------------------------------- */
235
SystemInitHook(void)236 __attribute__ ((weak)) void SystemInitHook (void) {
237 /* Void implementation of the weak function. */
238 }
239
