1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1062CVJ5A
4 ** MIMXRT1062CVJ5B
5 ** MIMXRT1062CVL5A
6 ** MIMXRT1062CVL5B
7 ** MIMXRT1062DVJ6A
8 ** MIMXRT1062DVJ6B
9 ** MIMXRT1062DVL6A
10 ** MIMXRT1062DVL6B
11 ** MIMXRT1062DVN6B
12 ** MIMXRT1062XVN5B
13 **
14 ** Compilers: Freescale C/C++ for Embedded ARM
15 ** GNU C Compiler
16 ** IAR ANSI C/C++ Compiler for ARM
17 ** Keil ARM C/C++ Compiler
18 ** MCUXpresso Compiler
19 **
20 ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
21 ** Version: rev. 1.4, 2022-03-25
22 ** Build: b221009
23 **
24 ** Abstract:
25 ** Provides a system configuration function and a global variable that
26 ** contains the system frequency. It configures the device and initializes
27 ** the oscillator (PLL) that is part of the microcontroller device.
28 **
29 ** Copyright 2016 Freescale Semiconductor, Inc.
30 ** Copyright 2016-2022 NXP
31 ** All rights reserved.
32 **
33 ** SPDX-License-Identifier: BSD-3-Clause
34 **
35 ** http: www.nxp.com
36 ** mail: support@nxp.com
37 **
38 ** Revisions:
39 ** - rev. 0.1 (2017-01-10)
40 ** Initial version.
41 ** - rev. 1.0 (2018-11-16)
42 ** Update header files to align with IMXRT1060RM Rev.0.
43 ** - rev. 1.1 (2018-11-27)
44 ** Update header files to align with IMXRT1060RM Rev.1.
45 ** - rev. 1.2 (2019-04-29)
46 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
47 ** - rev. 1.3 (2021-08-10)
48 ** Update header files to align with IMXRT1060RM Rev.3.
49 ** - rev. 1.4 (2022-03-25)
50 ** Add RT1060X device
51 **
52 ** ###################################################################
53 */
54
55 /*!
56 * @file MIMXRT1062
57 * @version 1.4
58 * @date 2022-03-25
59 * @brief Device specific configuration file for MIMXRT1062 (implementation file)
60 *
61 * Provides a system configuration function and a global variable that contains
62 * the system frequency. It configures the device and initializes the oscillator
63 * (PLL) that is part of the microcontroller device.
64 */
65
66 #include <stdint.h>
67 #include "fsl_device_registers.h"
68
69
70
71 /* ----------------------------------------------------------------------------
72 -- Core clock
73 ---------------------------------------------------------------------------- */
74
75 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
76
77 /* ----------------------------------------------------------------------------
78 -- SystemInit()
79 ---------------------------------------------------------------------------- */
80
SystemInit(void)81 void SystemInit (void) {
82 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
83 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
84 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
85
86 #if defined(__MCUXPRESSO)
87 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
88 SCB->VTOR = (uint32_t)g_pfnVectors;
89 #endif
90
91 /* Disable Watchdog Power Down Counter */
92 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
93 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
94
95 /* Watchdog disable */
96
97 #if (DISABLE_WDOG)
98 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
99 {
100 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
101 }
102 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
103 {
104 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
105 }
106 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
107 {
108 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
109 }
110 else
111 {
112 RTWDOG->CNT = 0xC520U;
113 RTWDOG->CNT = 0xD928U;
114 }
115 RTWDOG->TOVAL = 0xFFFF;
116 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
117 #endif /* (DISABLE_WDOG) */
118
119 /* Disable Systick which might be enabled by bootrom */
120 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
121 {
122 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
123 }
124
125 /* Enable instruction and data caches */
126 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
127 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
128 SCB_EnableICache();
129 }
130 #endif
131
132 SystemInitHook();
133 }
134
135 /* ----------------------------------------------------------------------------
136 -- SystemCoreClockUpdate()
137 ---------------------------------------------------------------------------- */
138
SystemCoreClockUpdate(void)139 void SystemCoreClockUpdate (void) {
140
141 uint32_t freq;
142 uint32_t PLL1MainClock;
143 uint32_t PLL2MainClock;
144
145 /* Periph_clk2_clk ---> Periph_clk */
146 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
147 {
148 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
149 {
150 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
151 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
152 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
153 {
154 freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
155 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
156 }
157 else
158 {
159 freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
160 }
161 break;
162
163 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
164 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
165 freq = CPU_XTAL_CLK_HZ;
166 break;
167
168 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
169 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
170 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
171 break;
172
173 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
174 default:
175 freq = 0U;
176 break;
177 }
178
179 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
180 }
181 /* Pre_Periph_clk ---> Periph_clk */
182 else
183 {
184 /* check if pll is bypassed */
185 if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U)
186 {
187 PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
188 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
189 }
190 else
191 {
192 PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
193 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
194 }
195
196 /* check if pll is bypassed */
197 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
198 {
199 PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
200 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
201 }
202 else
203 {
204 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
205 }
206 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
207
208 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
209 {
210 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
211 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
212 freq = PLL2MainClock;
213 break;
214
215 /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
216 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
217 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
218 break;
219
220 /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
221 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
222 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
223 break;
224
225 /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
226 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
227 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
228 break;
229
230 default:
231 freq = 0U;
232 break;
233 }
234 }
235
236 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
237
238 }
239
240 /* ----------------------------------------------------------------------------
241 -- SystemInitHook()
242 ---------------------------------------------------------------------------- */
243
SystemInitHook(void)244 __attribute__ ((weak)) void SystemInitHook (void) {
245 /* Void implementation of the weak function. */
246 }
247
