1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1061CVJ5A
4 ** MIMXRT1061CVJ5B
5 ** MIMXRT1061CVL5A
6 ** MIMXRT1061CVL5B
7 ** MIMXRT1061DVJ6A
8 ** MIMXRT1061DVJ6B
9 ** MIMXRT1061DVL6A
10 ** MIMXRT1061DVL6B
11 ** MIMXRT1061XVN5B
12 **
13 ** Compilers: Freescale C/C++ for Embedded ARM
14 ** GNU C Compiler
15 ** IAR ANSI C/C++ Compiler for ARM
16 ** Keil ARM C/C++ Compiler
17 ** MCUXpresso Compiler
18 **
19 ** Reference manual: IMXRT1060RM Rev.3, 07/2021 | IMXRT106XSRM Rev.0
20 ** Version: rev. 1.4, 2022-03-25
21 ** Build: b221009
22 **
23 ** Abstract:
24 ** Provides a system configuration function and a global variable that
25 ** contains the system frequency. It configures the device and initializes
26 ** the oscillator (PLL) that is part of the microcontroller device.
27 **
28 ** Copyright 2016 Freescale Semiconductor, Inc.
29 ** Copyright 2016-2022 NXP
30 ** All rights reserved.
31 **
32 ** SPDX-License-Identifier: BSD-3-Clause
33 **
34 ** http: www.nxp.com
35 ** mail: support@nxp.com
36 **
37 ** Revisions:
38 ** - rev. 0.1 (2017-01-10)
39 ** Initial version.
40 ** - rev. 1.0 (2018-11-16)
41 ** Update header files to align with IMXRT1060RM Rev.0.
42 ** - rev. 1.1 (2018-11-27)
43 ** Update header files to align with IMXRT1060RM Rev.1.
44 ** - rev. 1.2 (2019-04-29)
45 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
46 ** - rev. 1.3 (2021-08-10)
47 ** Update header files to align with IMXRT1060RM Rev.3.
48 ** - rev. 1.4 (2022-03-25)
49 ** Add RT1060X device
50 **
51 ** ###################################################################
52 */
53
54 /*!
55 * @file MIMXRT1061
56 * @version 1.4
57 * @date 2022-03-25
58 * @brief Device specific configuration file for MIMXRT1061 (implementation file)
59 *
60 * Provides a system configuration function and a global variable that contains
61 * the system frequency. It configures the device and initializes the oscillator
62 * (PLL) that is part of the microcontroller device.
63 */
64
65 #include <stdint.h>
66 #include "fsl_device_registers.h"
67
68
69
70 /* ----------------------------------------------------------------------------
71 -- Core clock
72 ---------------------------------------------------------------------------- */
73
74 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
75
76 /* ----------------------------------------------------------------------------
77 -- SystemInit()
78 ---------------------------------------------------------------------------- */
79
SystemInit(void)80 void SystemInit (void) {
81 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
82 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
83 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
84
85 #if defined(__MCUXPRESSO)
86 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
87 SCB->VTOR = (uint32_t)g_pfnVectors;
88 #endif
89
90 /* Disable Watchdog Power Down Counter */
91 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
92 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
93
94 /* Watchdog disable */
95
96 #if (DISABLE_WDOG)
97 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
98 {
99 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
100 }
101 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
102 {
103 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
104 }
105 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
106 {
107 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
108 }
109 else
110 {
111 RTWDOG->CNT = 0xC520U;
112 RTWDOG->CNT = 0xD928U;
113 }
114 RTWDOG->TOVAL = 0xFFFF;
115 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
116 #endif /* (DISABLE_WDOG) */
117
118 /* Disable Systick which might be enabled by bootrom */
119 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
120 {
121 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
122 }
123
124 /* Enable instruction and data caches */
125 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
126 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
127 SCB_EnableICache();
128 }
129 #endif
130
131 SystemInitHook();
132 }
133
134 /* ----------------------------------------------------------------------------
135 -- SystemCoreClockUpdate()
136 ---------------------------------------------------------------------------- */
137
SystemCoreClockUpdate(void)138 void SystemCoreClockUpdate (void) {
139
140 uint32_t freq;
141 uint32_t PLL1MainClock;
142 uint32_t PLL2MainClock;
143
144 /* Periph_clk2_clk ---> Periph_clk */
145 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
146 {
147 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
148 {
149 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
150 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
151 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
152 {
153 freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
154 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
155 }
156 else
157 {
158 freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
159 }
160 break;
161
162 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
163 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
164 freq = CPU_XTAL_CLK_HZ;
165 break;
166
167 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
168 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
169 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
170 break;
171
172 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
173 default:
174 freq = 0U;
175 break;
176 }
177
178 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
179 }
180 /* Pre_Periph_clk ---> Periph_clk */
181 else
182 {
183 /* check if pll is bypassed */
184 if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U)
185 {
186 PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
187 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
188 }
189 else
190 {
191 PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
192 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
193 }
194
195 /* check if pll is bypassed */
196 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
197 {
198 PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
199 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
200 }
201 else
202 {
203 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
204 }
205 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
206
207 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
208 {
209 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
210 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
211 freq = PLL2MainClock;
212 break;
213
214 /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
215 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
216 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
217 break;
218
219 /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
220 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
221 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
222 break;
223
224 /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
225 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
226 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
227 break;
228
229 default:
230 freq = 0U;
231 break;
232 }
233 }
234
235 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
236
237 }
238
239 /* ----------------------------------------------------------------------------
240 -- SystemInitHook()
241 ---------------------------------------------------------------------------- */
242
SystemInitHook(void)243 __attribute__ ((weak)) void SystemInitHook (void) {
244 /* Void implementation of the weak function. */
245 }
246
