1 /*
2 ** ###################################################################
3 ** Processors: MIMXRT1052CVJ5B
4 ** MIMXRT1052CVL5B
5 ** MIMXRT1052DVJ6B
6 ** MIMXRT1052DVL6B
7 **
8 ** Compilers: Freescale C/C++ for Embedded ARM
9 ** GNU C Compiler
10 ** IAR ANSI C/C++ Compiler for ARM
11 ** Keil ARM C/C++ Compiler
12 ** MCUXpresso Compiler
13 **
14 ** Reference manual: IMXRT1050RM Rev.5, 07/2021 | IMXRT1050SRM Rev.2
15 ** Version: rev. 1.4, 2021-08-10
16 ** Build: b210811
17 **
18 ** Abstract:
19 ** Provides a system configuration function and a global variable that
20 ** contains the system frequency. It configures the device and initializes
21 ** the oscillator (PLL) that is part of the microcontroller device.
22 **
23 ** Copyright 2016 Freescale Semiconductor, Inc.
24 ** Copyright 2016-2021 NXP
25 ** All rights reserved.
26 **
27 ** SPDX-License-Identifier: BSD-3-Clause
28 **
29 ** http: www.nxp.com
30 ** mail: support@nxp.com
31 **
32 ** Revisions:
33 ** - rev. 0.1 (2017-01-10)
34 ** Initial version.
35 ** - rev. 1.0 (2018-09-21)
36 ** Update interrupt vector table and dma request source.
37 ** Update register BEE_ADDR_OFFSET1's bitfield name to ADDR_OFFSET1.
38 ** Split GPIO_COMBINED_IRQS to GPIO_COMBINED_LOW_IRQS and GPIO_COMBINED_HIGH_IRQS.
39 ** - rev. 1.1 (2018-11-16)
40 ** Update header files to align with IMXRT1050RM Rev.1.
41 ** - rev. 1.2 (2018-11-27)
42 ** Update header files to align with IMXRT1050RM Rev.2.1.
43 ** - rev. 1.3 (2019-04-29)
44 ** Add SET/CLR/TOG register group to register CTRL, STAT, CHANNELCTRL, CH0STAT, CH0OPTS, CH1STAT, CH1OPTS, CH2STAT, CH2OPTS, CH3STAT, CH3OPTS of DCP module.
45 ** - rev. 1.4 (2021-08-10)
46 ** Update header files to align with IMXRT1050RM Rev.5.
47 **
48 ** ###################################################################
49 */
50
51 /*!
52 * @file MIMXRT1052
53 * @version 1.4
54 * @date 2021-08-10
55 * @brief Device specific configuration file for MIMXRT1052 (implementation file)
56 *
57 * Provides a system configuration function and a global variable that contains
58 * the system frequency. It configures the device and initializes the oscillator
59 * (PLL) that is part of the microcontroller device.
60 */
61
62 #include <stdint.h>
63 #include "fsl_device_registers.h"
64
65
66
67 /* ----------------------------------------------------------------------------
68 -- Core clock
69 ---------------------------------------------------------------------------- */
70
71 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
72
73 /* ----------------------------------------------------------------------------
74 -- SystemInit()
75 ---------------------------------------------------------------------------- */
76
SystemInit(void)77 void SystemInit (void) {
78 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
79 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
80 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
81
82 #if defined(__MCUXPRESSO)
83 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code
84 SCB->VTOR = (uint32_t)g_pfnVectors;
85 #endif
86
87 /* Disable Watchdog Power Down Counter */
88 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
89 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK;
90
91 /* Watchdog disable */
92
93 #if (DISABLE_WDOG)
94 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U)
95 {
96 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
97 }
98 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U)
99 {
100 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK;
101 }
102 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U)
103 {
104 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */
105 }
106 else
107 {
108 RTWDOG->CNT = 0xC520U;
109 RTWDOG->CNT = 0xD928U;
110 }
111 RTWDOG->TOVAL = 0xFFFF;
112 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK;
113 #endif /* (DISABLE_WDOG) */
114
115 /* Disable Systick which might be enabled by bootrom */
116 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U)
117 {
118 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk;
119 }
120
121 /* Enable instruction and data caches */
122 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT
123 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) {
124 SCB_EnableICache();
125 }
126 #endif
127
128 SystemInitHook();
129 }
130
131 /* ----------------------------------------------------------------------------
132 -- SystemCoreClockUpdate()
133 ---------------------------------------------------------------------------- */
134
SystemCoreClockUpdate(void)135 void SystemCoreClockUpdate (void) {
136
137 uint32_t freq;
138 uint32_t PLL1MainClock;
139 uint32_t PLL2MainClock;
140
141 /* Periph_clk2_clk ---> Periph_clk */
142 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U)
143 {
144 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK)
145 {
146 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */
147 case CCM_CBCMR_PERIPH_CLK2_SEL(0U):
148 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U)
149 {
150 freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ?
151 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
152 }
153 else
154 {
155 freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
156 }
157 break;
158
159 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */
160 case CCM_CBCMR_PERIPH_CLK2_SEL(1U):
161 freq = CPU_XTAL_CLK_HZ;
162 break;
163
164 case CCM_CBCMR_PERIPH_CLK2_SEL(2U):
165 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
166 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
167 break;
168
169 case CCM_CBCMR_PERIPH_CLK2_SEL(3U):
170 default:
171 freq = 0U;
172 break;
173 }
174
175 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U);
176 }
177 /* Pre_Periph_clk ---> Periph_clk */
178 else
179 {
180 /* check if pll is bypassed */
181 if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U)
182 {
183 PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ?
184 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
185 }
186 else
187 {
188 PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >>
189 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U);
190 }
191
192 /* check if pll is bypassed */
193 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U)
194 {
195 PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ?
196 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ;
197 }
198 else
199 {
200 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U));
201 }
202 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM)));
203
204 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK)
205 {
206 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */
207 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U):
208 freq = PLL2MainClock;
209 break;
210
211 /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */
212 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U):
213 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U;
214 break;
215
216 /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */
217 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U):
218 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U;
219 break;
220
221 /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */
222 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U):
223 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U);
224 break;
225
226 default:
227 freq = 0U;
228 break;
229 }
230 }
231
232 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U));
233
234 }
235
236 /* ----------------------------------------------------------------------------
237 -- SystemInitHook()
238 ---------------------------------------------------------------------------- */
239
SystemInitHook(void)240 __attribute__ ((weak)) void SystemInitHook (void) {
241 /* Void implementation of the weak function. */
242 }
243
