1 /* 2 * Copyright 2017-2020 NXP 3 * All rights reserved. 4 * 5 * SPDX-License-Identifier: BSD-3-Clause 6 */ 7 8 #ifndef _FSL_ROMAPI_H_ 9 #define _FSL_ROMAPI_H_ 10 11 #include "fsl_common.h" 12 13 /*! 14 * @addtogroup romapi 15 * @{ 16 */ 17 18 /*! @brief ROMAPI version 1.1.1. */ 19 #define FSL_ROM_ROMAPI_VERSION (MAKE_VERSION(1U, 1U, 1U)) 20 /*! @brief ROM FLEXSPI NOR driver version 1.4.0. */ 21 #define FSL_ROM_FLEXSPINOR_DRIVER_VERSION (MAKE_VERSION(1U, 4U, 0U)) 22 23 /*! 24 * @name Common ROMAPI fearures info defines 25 * @{ 26 */ 27 /* @brief ROM has FLEXSPI NOR API. */ 28 #define FSL_ROM_HAS_FLEXSPINOR_API (1) 29 /* @brief ROM has run bootloader API. */ 30 #define FSL_ROM_HAS_RUNBOOTLOADER_API (0) 31 /* @brief ROM has FLEXSPI NOR get config API. */ 32 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_GET_CONFIG (0) 33 /* @brief ROM has flash init API. */ 34 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_FLASH_INIT (1) 35 /* @brief ROM has erase API. */ 36 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE (1) 37 /* @brief ROM has erase sector API. */ 38 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR (1) 39 /* @brief ROM has erase block API. */ 40 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_BLOCK (0) 41 /* @brief ROM has erase all API. */ 42 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL (1) 43 /* @brief ROM has page program API. */ 44 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_PAGE_PROGRAM (1) 45 /* @brief ROM has update lut API. */ 46 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT (1) 47 /* @brief ROM has FLEXSPI command API. */ 48 #define FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER (1) 49 50 /*@}*/ 51 52 #define kROM_StatusGroup_FLEXSPI 60U /*!< ROM FLEXSPI status group number.*/ 53 #define kROM_StatusGroup_FLEXSPINOR 200U /*!< ROM FLEXSPI NOR status group number.*/ 54 55 #define FSL_ROM_FLEXSPI_LUT_SEQ(cmd0, pad0, op0, cmd1, pad1, op1) \ 56 (FLEXSPI_LUT_OPERAND0(op0) | FLEXSPI_LUT_NUM_PADS0(pad0) | FLEXSPI_LUT_OPCODE0(cmd0) | FLEXSPI_LUT_OPERAND1(op1) | \ 57 FLEXSPI_LUT_NUM_PADS1(pad1) | FLEXSPI_LUT_OPCODE1(cmd1)) 58 59 /*! @brief Generate bit mask */ 60 #define FSL_ROM_FLEXSPI_BITMASK(bit_offset) (1U << (bit_offset)) 61 62 /*! @brief FLEXSPI memory config block related defintions */ 63 #define FLEXSPI_CFG_BLK_TAG (0x42464346UL) /*!< ascii "FCFB" Big Endian */ 64 #define FLEXSPI_CFG_BLK_VERSION (0x56010400UL) /*!< V1.4.0 */ 65 66 #define CMD_SDR 0x01U 67 #define CMD_DDR 0x21U 68 #define RADDR_SDR 0x02U 69 #define RADDR_DDR 0x22U 70 #define CADDR_SDR 0x03U 71 #define CADDR_DDR 0x23U 72 #define MODE1_SDR 0x04U 73 #define MODE1_DDR 0x24U 74 #define MODE2_SDR 0x05U 75 #define MODE2_DDR 0x25U 76 #define MODE4_SDR 0x06U 77 #define MODE4_DDR 0x26U 78 #define MODE8_SDR 0x07U 79 #define MODE8_DDR 0x27U 80 #define WRITE_SDR 0x08U 81 #define WRITE_DDR 0x28U 82 #define READ_SDR 0x09U 83 #define READ_DDR 0x29U 84 #define LEARN_SDR 0x0AU 85 #define LEARN_DDR 0x2AU 86 #define DATSZ_SDR 0x0BU 87 #define DATSZ_DDR 0x2BU 88 #define DUMMY_SDR 0x0CU 89 #define DUMMY_DDR 0x2CU 90 #define DUMMY_RWDS_SDR 0x0DU 91 #define DUMMY_RWDS_DDR 0x2DU 92 #define JMP_ON_CS 0x1FU 93 #define STOP 0U 94 95 #define FLEXSPI_1PAD 0U 96 #define FLEXSPI_2PAD 1U 97 #define FLEXSPI_4PAD 2U 98 #define FLEXSPI_8PAD 3U 99 100 /* Lookup table related defintions */ 101 #define NOR_CMD_INDEX_READ 0U 102 #define NOR_CMD_INDEX_READSTATUS 1U 103 #define NOR_CMD_INDEX_WRITEENABLE 2U 104 #define NOR_CMD_INDEX_ERASESECTOR 3U 105 #define NOR_CMD_INDEX_PAGEPROGRAM 4U 106 #define NOR_CMD_INDEX_CHIPERASE 5U 107 #define NOR_CMD_INDEX_DUMMY 6U 108 #define NOR_CMD_INDEX_ERASEBLOCK 7U 109 110 /*! 111 * NOR LUT sequence index used for default LUT assignment 112 * NOTE: 113 * The will take effect if the lut sequences are not customized. 114 */ 115 #define NOR_CMD_LUT_SEQ_IDX_READ 0U /*!< READ LUT sequence id in lookupTable stored in config block */ 116 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS 1U /*!< Read Status LUT sequence id in lookupTable stored in config block */ 117 #define NOR_CMD_LUT_SEQ_IDX_READSTATUS_XPI \ 118 2U /*!< Read status DPI/QPI/OPI sequence id in lookupTable stored in config block */ 119 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE 3U /*!< Write Enable sequence id in lookupTable stored in config block */ 120 #define NOR_CMD_LUT_SEQ_IDX_WRITEENABLE_XPI \ 121 4U /*!< Write Enable DPI/QPI/OPI sequence id in lookupTable stored in config block */ 122 #define NOR_CMD_LUT_SEQ_IDX_ERASESECTOR 5U /*!< Erase Sector sequence id in lookupTable stored in config block */ 123 #define NOR_CMD_LUT_SEQ_IDX_ERASEBLOCK 8U /*!< Erase Block sequence id in lookupTable stored in config block */ 124 #define NOR_CMD_LUT_SEQ_IDX_PAGEPROGRAM 9U /*!< Program sequence id in lookupTable stored in config block */ 125 #define NOR_CMD_LUT_SEQ_IDX_CHIPERASE 11U /*!< Chip Erase sequence in lookupTable id stored in config block */ 126 #define NOR_CMD_LUT_SEQ_IDX_READ_SFDP 13U /*!< Read SFDP sequence in lookupTable id stored in config block */ 127 #define NOR_CMD_LUT_SEQ_IDX_RESTORE_NOCMD \ 128 14U /*!< Restore 0-4-4/0-8-8 mode sequence id in lookupTable stored in config block */ 129 #define NOR_CMD_LUT_SEQ_IDX_EXIT_NOCMD \ 130 15U /*!< Exit 0-4-4/0-8-8 mode sequence id in lookupTable stored in config blobk */ 131 132 /*! 133 * @name Support for init FLEXSPI NOR configuration 134 * @{ 135 */ 136 /*! @brief Flash Pad Definitions */ 137 enum 138 { 139 kSerialFlash_1Pad = 1U, 140 kSerialFlash_2Pads = 2U, 141 kSerialFlash_4Pads = 4U, 142 kSerialFlash_8Pads = 8U, 143 }; 144 145 /*! @brief FLEXSPI clock configuration type */ 146 enum 147 { 148 kFLEXSPIClk_SDR, /*!< Clock configure for SDR mode */ 149 kFLEXSPIClk_DDR, /*!< Clock configurat for DDR mode */ 150 }; 151 152 /*! @brief FLEXSPI Read Sample Clock Source definition */ 153 enum _flexspi_read_sample_clk 154 { 155 kFLEXSPIReadSampleClk_LoopbackInternally = 0U, 156 kFLEXSPIReadSampleClk_LoopbackFromDqsPad = 1U, 157 kFLEXSPIReadSampleClk_LoopbackFromSckPad = 2U, 158 kFLEXSPIReadSampleClk_ExternalInputFromDqsPad = 3U, 159 }; 160 161 /*! @brief Flash Type Definition */ 162 enum 163 { 164 kFLEXSPIDeviceType_SerialNOR = 1U, /*!< Flash device is Serial NOR */ 165 }; 166 167 /*! @brief Flash Configuration Command Type */ 168 enum 169 { 170 kDeviceConfigCmdType_Generic, /*!< Generic command, for example: configure dummy cycles, drive strength, etc */ 171 kDeviceConfigCmdType_QuadEnable, /*!< Quad Enable command */ 172 kDeviceConfigCmdType_Spi2Xpi, /*!< Switch from SPI to DPI/QPI/OPI mode */ 173 kDeviceConfigCmdType_Xpi2Spi, /*!< Switch from DPI/QPI/OPI to SPI mode */ 174 kDeviceConfigCmdType_Spi2NoCmd, /*!< Switch to 0-4-4/0-8-8 mode */ 175 kDeviceConfigCmdType_Reset, /*!< Reset device command */ 176 }; 177 178 /*! @brief Defintions for FLEXSPI Serial Clock Frequency */ 179 enum _flexspi_serial_clk_freq 180 { 181 kFLEXSPISerialClk_NoChange = 0U, 182 kFLEXSPISerialClk_30MHz = 1U, 183 kFLEXSPISerialClk_50MHz = 2U, 184 kFLEXSPISerialClk_60MHz = 3U, 185 kFLEXSPISerialClk_75MHz = 4U, 186 kFLEXSPISerialClk_80MHz = 5U, 187 kFLEXSPISerialClk_100MHz = 6U, 188 kFLEXSPISerialClk_133MHz = 7U, 189 kFLEXSPISerialClk_166MHz = 8U, 190 kFLEXSPISerialClk_200MHz = 9U, 191 }; 192 193 /*! @brief Misc feature bit definitions */ 194 enum 195 { 196 kFLEXSPIMiscOffset_DiffClkEnable = 0U, /*!< Bit for Differential clock enable */ 197 kFLEXSPIMiscOffset_Ck2Enable = 1U, /*!< Bit for CK2 enable */ 198 kFLEXSPIMiscOffset_ParallelEnable = 2U, /*!< Bit for Parallel mode enable */ 199 kFLEXSPIMiscOffset_WordAddressableEnable = 3U, /*!< Bit for Word Addressable enable */ 200 kFLEXSPIMiscOffset_SafeConfigFreqEnable = 4U, /*!< Bit for Safe Configuration Frequency enable */ 201 kFLEXSPIMiscOffset_PadSettingOverrideEnable = 5U, /*!< Bit for Pad setting override enable */ 202 kFLEXSPIMiscOffset_DdrModeEnable = 6U, /*!< Bit for DDR clock confiuration indication. */ 203 kFLEXSPIMiscOffset_UseValidTimeForAllFreq = 7U, /*!< Bit for DLLCR settings under all modes */ 204 }; 205 206 enum 207 { 208 kSerialNorType_StandardSPI, /*!< Device that support Standard SPI and Extended SPI mode */ 209 kSerialNorType_HyperBus, /*!< Device that supports HyperBus only */ 210 kSerialNorType_XPI, /*!< Device that works under DPI, QPI or OPI mode */ 211 kSerialNorType_NoCmd, /*!< Device that works under No command mode (XIP mode/Performance Enhance 212 mode/continous read mode) */ 213 }; 214 215 /*@}*/ 216 217 /*! 218 * @name FLEXSPI NOR Configuration 219 * @{ 220 */ 221 222 /*! @brief FLEXSPI LUT Sequence structure */ 223 typedef struct _flexspi_lut_seq 224 { 225 uint8_t seqNum; /*!< Sequence Number, valid number: 1-16 */ 226 uint8_t seqId; /*!< Sequence Index, valid number: 0-15 */ 227 uint16_t reserved; 228 } flexspi_lut_seq_t; 229 230 typedef struct 231 { 232 uint8_t time_100ps; /*!< Data valid time, in terms of 100ps */ 233 uint8_t delay_cells; /*!< Data valid time, in terms of delay cells */ 234 } flexspi_dll_time_t; 235 236 /*! @brief FLEXSPI Memory Configuration Block */ 237 typedef struct _flexspi_mem_config 238 { 239 uint32_t tag; /*!< [0x000-0x003] Tag, fixed value 0x42464346UL */ 240 uint32_t version; /*!< [0x004-0x007] Version,[31:24] -'V', [23:16] - Major, [15:8] - Minor, [7:0] - bugfix */ 241 uint32_t reserved0; /*!< [0x008-0x00b] Reserved for future use */ 242 uint8_t readSampleClkSrc; /*!< [0x00c-0x00c] Read Sample Clock Source, valid value: 0/1/3 */ 243 uint8_t csHoldTime; /*!< [0x00d-0x00d] Data hold time, default value: 3 */ 244 uint8_t csSetupTime; /*!< [0x00e-0x00e] Date setup time, default value: 3 */ 245 uint8_t columnAddressWidth; /*!< [0x00f-0x00f] Column Address with, for HyperBus protocol, it is fixed to 3, For 246 Serial NAND, need to refer to datasheet */ 247 uint8_t deviceModeCfgEnable; /*!< [0x010-0x010] Device Mode Configure enable flag, 1 - Enable, 0 - Disable */ 248 uint8_t deviceModeType; /*!< [0x011-0x011] Specify the configuration command type:Quad Enable, DPI/QPI/OPI switch, 249 Generic configuration, etc. */ 250 uint16_t waitTimeCfgCommands; /*!< [0x012-0x013] Wait time for all configuration commands, unit: 100us, Used for 251 DPI/QPI/OPI switch or reset command */ 252 flexspi_lut_seq_t deviceModeSeq; /*!< [0x014-0x017] Device mode sequence info, [7:0] - LUT sequence id, [15:8] - LUt 253 sequence number, [31:16] Reserved */ 254 uint32_t deviceModeArg; /*!< [0x018-0x01b] Argument/Parameter for device configuration */ 255 uint8_t configCmdEnable; /*!< [0x01c-0x01c] Configure command Enable Flag, 1 - Enable, 0 - Disable */ 256 uint8_t configModeType[3]; /*!< [0x01d-0x01f] Configure Mode Type, similar as deviceModeTpe */ 257 flexspi_lut_seq_t 258 configCmdSeqs[3]; /*!< [0x020-0x02b] Sequence info for Device Configuration command, similar as deviceModeSeq */ 259 uint32_t reserved1; /*!< [0x02c-0x02f] Reserved for future use */ 260 uint32_t configCmdArgs[3]; /*!< [0x030-0x03b] Arguments/Parameters for device Configuration commands */ 261 uint32_t reserved2; /*!< [0x03c-0x03f] Reserved for future use */ 262 uint32_t controllerMiscOption; /*!< [0x040-0x043] Controller Misc Options, see Misc feature bit definitions for more 263 details */ 264 uint8_t deviceType; /*!< [0x044-0x044] Device Type: See Flash Type Definition for more details */ 265 uint8_t sflashPadType; /*!< [0x045-0x045] Serial Flash Pad Type: 1 - Single, 2 - Dual, 4 - Quad, 8 - Octal */ 266 uint8_t serialClkFreq; /*!< [0x046-0x046] Serial Flash Frequencey, device specific definitions, See System Boot 267 Chapter for more details */ 268 uint8_t 269 lutCustomSeqEnable; /*!< [0x047-0x047] LUT customization Enable, it is required if the program/erase cannot 270 be done using 1 LUT sequence, currently, only applicable to HyperFLASH */ 271 uint32_t reserved3[2]; /*!< [0x048-0x04f] Reserved for future use */ 272 uint32_t sflashA1Size; /*!< [0x050-0x053] Size of Flash connected to A1 */ 273 uint32_t sflashA2Size; /*!< [0x054-0x057] Size of Flash connected to A2 */ 274 uint32_t sflashB1Size; /*!< [0x058-0x05b] Size of Flash connected to B1 */ 275 uint32_t sflashB2Size; /*!< [0x05c-0x05f] Size of Flash connected to B2 */ 276 uint32_t csPadSettingOverride; /*!< [0x060-0x063] CS pad setting override value */ 277 uint32_t sclkPadSettingOverride; /*!< [0x064-0x067] SCK pad setting override value */ 278 uint32_t dataPadSettingOverride; /*!< [0x068-0x06b] data pad setting override value */ 279 uint32_t dqsPadSettingOverride; /*!< [0x06c-0x06f] DQS pad setting override value */ 280 uint32_t timeoutInMs; /*!< [0x070-0x073] Timeout threshold for read status command */ 281 uint32_t commandInterval; /*!< [0x074-0x077] CS deselect interval between two commands */ 282 flexspi_dll_time_t dataValidTime[2]; /*!< [0x078-0x07b] CLK edge to data valid time for PORT A and PORT B */ 283 uint16_t busyOffset; /*!< [0x07c-0x07d] Busy offset, valid value: 0-31 */ 284 uint16_t busyBitPolarity; /*!< [0x07e-0x07f] Busy flag polarity, 0 - busy flag is 1 when flash device is busy, 1 - 285 busy flag is 0 when flash device is busy */ 286 uint32_t lookupTable[64]; /*!< [0x080-0x17f] Lookup table holds Flash command sequences */ 287 flexspi_lut_seq_t lutCustomSeq[12]; /*!< [0x180-0x1af] Customizable LUT Sequences */ 288 uint32_t reserved4[4]; /*!< [0x1b0-0x1bf] Reserved for future use */ 289 } flexspi_mem_config_t; 290 291 /*! @brief Serial NOR configuration block */ 292 typedef struct _flexspi_nor_config 293 { 294 flexspi_mem_config_t memConfig; /*!< Common memory configuration info via FLEXSPI */ 295 uint32_t pageSize; /*!< Page size of Serial NOR */ 296 uint32_t sectorSize; /*!< Sector size of Serial NOR */ 297 uint8_t ipcmdSerialClkFreq; /*!< Clock frequency for IP command */ 298 uint8_t isUniformBlockSize; /*!< Sector/Block size is the same */ 299 uint8_t isDataOrderSwapped; /*!< Data order (D0, D1, D2, D3) is swapped (D1,D0, D3, D2) */ 300 uint8_t reserved0[1]; /*!< Reserved for future use */ 301 uint8_t serialNorType; /*!< Serial NOR Flash type: 0/1/2/3 */ 302 uint8_t needExitNoCmdMode; /*!< Need to exit NoCmd mode before other IP command */ 303 uint8_t halfClkForNonReadCmd; /*!< Half the Serial Clock for non-read command: true/false */ 304 uint8_t needRestoreNoCmdMode; /*!< Need to Restore NoCmd mode after IP commmand execution */ 305 uint32_t blockSize; /*!< Block size */ 306 uint32_t reserve2[11]; /*!< Reserved for future use */ 307 } flexspi_nor_config_t; 308 309 /*@}*/ 310 311 /*! @brief Manufacturer ID */ 312 enum 313 { 314 kSerialFlash_ISSI_ManufacturerID = 0x9DU, /*!< Manufacturer ID of the ISSI serial flash */ 315 kSerialFlash_Adesto_ManufacturerID = 0x1F, /*!< Manufacturer ID of the Adesto Technologies serial flash*/ 316 kSerialFlash_Winbond_ManufacturerID = 0xEFU, /*!< Manufacturer ID of the Winbond serial flash */ 317 kSerialFlash_Cypress_ManufacturerID = 0x01U, /*!< Manufacturer ID for Cypress */ 318 }; 319 320 /*! @brief ROM FLEXSPI NOR flash status */ 321 enum _flexspi_nor_status 322 { 323 kStatus_ROM_FLEXSPI_SequenceExecutionTimeout = 324 MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 0), /*!< Status for Sequence Execution timeout */ 325 kStatus_ROM_FLEXSPI_InvalidSequence = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 1), /*!< Status for Invalid Sequence */ 326 kStatus_ROM_FLEXSPI_DeviceTimeout = MAKE_STATUS(kROM_StatusGroup_FLEXSPI, 2), /*!< Status for Device timeout */ 327 kStatus_FLEXSPINOR_DTRRead_DummyProbeFailed = 328 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 10), /*!< Status for DDR Read dummy probe failure */ 329 kStatus_ROM_FLEXSPINOR_SFDP_NotFound = 330 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 7), /*!< Status for SFDP read failure */ 331 kStatus_ROM_FLEXSPINOR_Flash_NotFound = 332 MAKE_STATUS(kROM_StatusGroup_FLEXSPINOR, 9), /*!< Status for Flash detection failure */ 333 }; 334 335 typedef enum _flexspi_operation 336 { 337 kFLEXSPIOperation_Command, /*!< FLEXSPI operation: Only command, both TX and RX buffer are ignored. */ 338 kFLEXSPIOperation_Config, /*!< FLEXSPI operation: Configure device mode, the TX FIFO size is fixed in LUT. */ 339 kFLEXSPIOperation_Write, /*!< FLEXSPI operation: Write, only TX buffer is effective */ 340 kFLEXSPIOperation_Read, /*!< FLEXSPI operation: Read, only Rx Buffer is effective. */ 341 kFLEXSPIOperation_End = kFLEXSPIOperation_Read, 342 } flexspi_operation_t; 343 344 /*! @brief FLEXSPI Transfer Context */ 345 typedef struct _flexspi_xfer 346 { 347 flexspi_operation_t operation; /*!< FLEXSPI operation */ 348 uint32_t baseAddress; /*!< FLEXSPI operation base address */ 349 uint32_t seqId; /*!< Sequence Id */ 350 uint32_t seqNum; /*!< Sequence Number */ 351 bool isParallelModeEnable; /*!< Is a parallel transfer */ 352 uint32_t *txBuffer; /*!< Tx buffer */ 353 uint32_t txSize; /*!< Tx size in bytes */ 354 uint32_t *rxBuffer; /*!< Rx buffer */ 355 uint32_t rxSize; /*!< Rx size in bytes */ 356 } flexspi_xfer_t; 357 358 #ifdef __cplusplus 359 extern "C" { 360 #endif 361 362 #if defined(FSL_FEATURE_BOOT_ROM_HAS_ROMAPI) && FSL_FEATURE_BOOT_ROM_HAS_ROMAPI 363 364 /*! 365 * @name Initialization 366 * @{ 367 */ 368 369 /*! 370 * @brief Initialize Serial NOR flash via FLEXSPI 371 * 372 * This function checks and initializes the FLEXSPI module for the other FLEXSPI APIs. 373 * 374 * @param instance storage the instance of FLEXSPI. 375 * @param config A pointer to the storage for the driver runtime state. 376 * 377 * @retval kStatus_Success Api was executed succesfuly. 378 * @retval kStatus_InvalidArgument A invalid argument is provided. 379 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 380 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 381 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout 382 */ 383 status_t ROM_FLEXSPI_NorFlash_Init(uint32_t instance, flexspi_nor_config_t *config); 384 385 /*@}*/ 386 387 /*! 388 * @name Programming 389 * @{ 390 */ 391 /*! 392 * @brief Program data to Serial NOR flash via FLEXSPI. 393 * 394 * This function programs the NOR flash memory with the dest address for a given 395 * flash area as determined by the dst address and the length. 396 * 397 * @param instance storage the instance of FLEXSPI. 398 * @param config A pointer to the storage for the driver runtime state. 399 * @param dstAddr A pointer to the desired flash memory to be programmed. 400 * NOTE: 401 * It is recommended that use page aligned access; 402 * If the dstAddr is not aligned to page,the driver automatically 403 * aligns address down with the page address. 404 * @param src A pointer to the source buffer of data that is to be programmed 405 * into the NOR flash. 406 * 407 * @retval kStatus_Success Api was executed succesfuly. 408 * @retval kStatus_InvalidArgument A invalid argument is provided. 409 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 410 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 411 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout 412 */ 413 status_t ROM_FLEXSPI_NorFlash_ProgramPage(uint32_t instance, 414 flexspi_nor_config_t *config, 415 uint32_t dstAddr, 416 const uint32_t *src); 417 418 /*@}*/ 419 420 /*! 421 * @name Erasing 422 * @{ 423 */ 424 #if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR 425 /*! 426 * @brief Erase one sector specified by address 427 * 428 * This function erases one of NOR flash sectors based on the desired address. 429 * 430 * @param instance storage the index of FLEXSPI. 431 * @param config A pointer to the storage for the driver runtime state. 432 * @param address The start address of the desired NOR flash memory to be erased. 433 * NOTE: 434 * It is recommended that use sector-aligned access nor device; 435 * If dstAddr is not aligned with the sector,The driver automatically 436 * aligns address down with the sector address. 437 * 438 * @retval kStatus_Success Api was executed succesfuly. 439 * @retval kStatus_InvalidArgument A invalid argument is provided. 440 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 441 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 442 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout 443 */ 444 status_t ROM_FLEXSPI_NorFlash_EraseSector(uint32_t instance, flexspi_nor_config_t *config, uint32_t address); 445 #endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_SECTOR */ 446 447 #if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL 448 /*! 449 * @brief Erase all the Serial NOR flash connected on FLEXSPI. 450 * 451 * @param instance storage the instance of FLEXSPI. 452 * @param config A pointer to the storage for the driver runtime state. 453 * 454 * @retval kStatus_Success Api was executed succesfuly. 455 * @retval kStatus_InvalidArgument A invalid argument is provided. 456 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 457 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 458 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout 459 */ 460 status_t ROM_FLEXSPI_NorFlash_EraseAll(uint32_t instance, flexspi_nor_config_t *config); 461 #endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_ERASE_ALL */ 462 463 /*! 464 * @brief Erase Flash Region specified by address and length 465 * 466 * This function erases the appropriate number of flash sectors based on the 467 * desired start address and length. 468 * 469 * @param instance storage the index of FLEXSPI. 470 * @param config A pointer to the storage for the driver runtime state. 471 * @param start The start address of the desired NOR flash memory to be erased. 472 * NOTE: 473 * It is recommended that use sector-aligned access NOR flash; 474 * If dstAddr is not aligned with the sector,the driver automatically 475 * aligns address down with the sector address. 476 * @param length The length, given in bytes to be erased. 477 * NOTE: 478 * It is recommended that use sector-aligned access NOR flash; 479 * If length is not aligned with the sector,the driver automatically 480 * aligns up with the sector. 481 * @retval kStatus_Success Api was executed succesfuly. 482 * @retval kStatus_InvalidArgument A invalid argument is provided. 483 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 484 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 485 * @retval kStatus_ROM_FLEXSPI_DeviceTimeout the device timeout 486 */ 487 status_t ROM_FLEXSPI_NorFlash_Erase(uint32_t instance, flexspi_nor_config_t *config, uint32_t start, uint32_t length); 488 489 /*@}*/ 490 491 /*! 492 * @name Command 493 * @{ 494 */ 495 496 #if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER 497 /*! 498 * @brief FLEXSPI command 499 * 500 * This function is used to perform the command write sequence to the NOR flash. 501 * 502 * @param instance storage the index of FLEXSPI. 503 * @param xfer A pointer to the storage FLEXSPI Transfer Context. 504 * 505 * @retval kStatus_Success Api was executed succesfuly. 506 * @retval kStatus_InvalidArgument A invalid argument is provided. 507 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 508 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 509 */ 510 status_t ROM_FLEXSPI_NorFlash_CommandXfer(uint32_t instance, flexspi_xfer_t *xfer); 511 #endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_CMD_XFER */ 512 /*@}*/ 513 514 /*! 515 * @name UpdateLut 516 * @{ 517 */ 518 #if defined(FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT) && FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT 519 /*! 520 * @brief Configure FLEXSPI Lookup table 521 * 522 * @param instance storage the index of FLEXSPI. 523 * @param seqIndex storage the sequence Id. 524 * @param lutBase A pointer to the look-up-table for command sequences. 525 * @param seqNumber storage sequence number. 526 * 527 * @retval kStatus_Success Api was executed succesfuly. 528 * @retval kStatus_InvalidArgument A invalid argument is provided. 529 * @retval kStatus_ROM_FLEXSPI_InvalidSequence A invalid Sequence is provided. 530 * @retval kStatus_ROM_FLEXSPI_SequenceExecutionTimeout Sequence Execution timeout. 531 */ 532 status_t ROM_FLEXSPI_NorFlash_UpdateLut(uint32_t instance, 533 uint32_t seqIndex, 534 const uint32_t *lutBase, 535 uint32_t seqNumber); 536 #endif /* FSL_ROM_FLEXSPINOR_API_HAS_FEATURE_UPDATE_LUT */ 537 538 /*@}*/ 539 540 /*! 541 * @name ClearCache 542 * @{ 543 */ 544 545 /*! 546 * @brief Software reset for the FLEXSPI logic. 547 * 548 * This function sets the software reset flags for both AHB and buffer domain and 549 * resets both AHB buffer and also IP FIFOs. 550 * 551 * @param instance storage the index of FLEXSPI. 552 */ 553 void ROM_FLEXSPI_NorFlash_ClearCache(uint32_t instance); 554 555 /*@}*/ 556 557 #endif /* FSL_FEATURE_BOOT_ROM_HAS_ROMAPI */ 558 559 #ifdef __cplusplus 560 } 561 #endif 562 563 /*! @}*/ 564 565 #endif /* _FSL_ROMAPI_H_ */ 566
