1 /* 2 ** ################################################################### 3 ** Processors: MIMXRT1042DFP6B 4 ** MIMXRT1042XFP5B 5 ** MIMXRT1042XJM5B 6 ** 7 ** Compilers: Freescale C/C++ for Embedded ARM 8 ** GNU C Compiler 9 ** IAR ANSI C/C++ Compiler for ARM 10 ** Keil ARM C/C++ Compiler 11 ** MCUXpresso Compiler 12 ** 13 ** Reference manual: IMXRT1040RM Rev.1, 09/2022 14 ** Version: rev. 0.1, 2021-07-20 15 ** Build: b221011 16 ** 17 ** Abstract: 18 ** Provides a system configuration function and a global variable that 19 ** contains the system frequency. It configures the device and initializes 20 ** the oscillator (PLL) that is part of the microcontroller device. 21 ** 22 ** Copyright 2016 Freescale Semiconductor, Inc. 23 ** Copyright 2016-2022 NXP 24 ** All rights reserved. 25 ** 26 ** SPDX-License-Identifier: BSD-3-Clause 27 ** 28 ** http: www.nxp.com 29 ** mail: support@nxp.com 30 ** 31 ** Revisions: 32 ** - rev. 0.1 (2021-07-20) 33 ** Initial version. 34 ** 35 ** ################################################################### 36 */ 37 38 /*! 39 * @file MIMXRT1042 40 * @version 0.1 41 * @date 2021-07-20 42 * @brief Device specific configuration file for MIMXRT1042 (implementation file) 43 * 44 * Provides a system configuration function and a global variable that contains 45 * the system frequency. It configures the device and initializes the oscillator 46 * (PLL) that is part of the microcontroller device. 47 */ 48 49 #include <stdint.h> 50 #include "fsl_device_registers.h" 51 52 53 54 /* ---------------------------------------------------------------------------- 55 -- Core clock 56 ---------------------------------------------------------------------------- */ 57 58 uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK; 59 60 /* ---------------------------------------------------------------------------- 61 -- SystemInit() 62 ---------------------------------------------------------------------------- */ 63 SystemInit(void)64void SystemInit (void) { 65 #if ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) 66 SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */ 67 #endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */ 68 69 #if defined(__MCUXPRESSO) 70 extern uint32_t g_pfnVectors[]; // Vector table defined in startup code 71 SCB->VTOR = (uint32_t)g_pfnVectors; 72 #endif 73 74 /* Disable Watchdog Power Down Counter */ 75 WDOG1->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 76 WDOG2->WMCR &= ~(uint16_t) WDOG_WMCR_PDE_MASK; 77 78 /* Watchdog disable */ 79 80 #if (DISABLE_WDOG) 81 if ((WDOG1->WCR & WDOG_WCR_WDE_MASK) != 0U) 82 { 83 WDOG1->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 84 } 85 if ((WDOG2->WCR & WDOG_WCR_WDE_MASK) != 0U) 86 { 87 WDOG2->WCR &= ~(uint16_t) WDOG_WCR_WDE_MASK; 88 } 89 if ((RTWDOG->CS & RTWDOG_CS_CMD32EN_MASK) != 0U) 90 { 91 RTWDOG->CNT = 0xD928C520U; /* 0xD928C520U is the update key */ 92 } 93 else 94 { 95 RTWDOG->CNT = 0xC520U; 96 RTWDOG->CNT = 0xD928U; 97 } 98 RTWDOG->TOVAL = 0xFFFF; 99 RTWDOG->CS = (uint32_t) ((RTWDOG->CS) & ~RTWDOG_CS_EN_MASK) | RTWDOG_CS_UPDATE_MASK; 100 #endif /* (DISABLE_WDOG) */ 101 102 /* Disable Systick which might be enabled by bootrom */ 103 if ((SysTick->CTRL & SysTick_CTRL_ENABLE_Msk) != 0U) 104 { 105 SysTick->CTRL &= ~SysTick_CTRL_ENABLE_Msk; 106 } 107 108 /* Enable instruction and data caches */ 109 #if defined(__ICACHE_PRESENT) && __ICACHE_PRESENT 110 if (SCB_CCR_IC_Msk != (SCB_CCR_IC_Msk & SCB->CCR)) { 111 SCB_EnableICache(); 112 } 113 #endif 114 115 SystemInitHook(); 116 } 117 118 /* ---------------------------------------------------------------------------- 119 -- SystemCoreClockUpdate() 120 ---------------------------------------------------------------------------- */ 121 SystemCoreClockUpdate(void)122void SystemCoreClockUpdate (void) { 123 124 uint32_t freq; 125 uint32_t PLL1MainClock; 126 uint32_t PLL2MainClock; 127 128 /* Periph_clk2_clk ---> Periph_clk */ 129 if ((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK_SEL_MASK) != 0U) 130 { 131 switch (CCM->CBCMR & CCM_CBCMR_PERIPH_CLK2_SEL_MASK) 132 { 133 /* Pll3_sw_clk ---> Periph_clk2_clk ---> Periph_clk */ 134 case CCM_CBCMR_PERIPH_CLK2_SEL(0U): 135 if((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_MASK) != 0U) 136 { 137 freq = (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_USB1_BYPASS_CLK_SRC_SHIFT) == 0U) ? 138 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; 139 } 140 else 141 { 142 freq = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_USB1 & CCM_ANALOG_PLL_USB1_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 143 } 144 break; 145 146 /* Osc_clk ---> Periph_clk2_clk ---> Periph_clk */ 147 case CCM_CBCMR_PERIPH_CLK2_SEL(1U): 148 freq = CPU_XTAL_CLK_HZ; 149 break; 150 151 case CCM_CBCMR_PERIPH_CLK2_SEL(2U): 152 freq = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? 153 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; 154 break; 155 156 case CCM_CBCMR_PERIPH_CLK2_SEL(3U): 157 default: 158 freq = 0U; 159 break; 160 } 161 162 freq /= (((CCM->CBCDR & CCM_CBCDR_PERIPH_CLK2_PODF_MASK) >> CCM_CBCDR_PERIPH_CLK2_PODF_SHIFT) + 1U); 163 } 164 /* Pre_Periph_clk ---> Periph_clk */ 165 else 166 { 167 /* check if pll is bypassed */ 168 if((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_MASK) != 0U) 169 { 170 PLL1MainClock = (((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_ARM_BYPASS_CLK_SRC_SHIFT) == 0U) ? 171 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; 172 } 173 else 174 { 175 PLL1MainClock = ((CPU_XTAL_CLK_HZ * ((CCM_ANALOG->PLL_ARM & CCM_ANALOG_PLL_ARM_DIV_SELECT_MASK) >> 176 CCM_ANALOG_PLL_ARM_DIV_SELECT_SHIFT)) >> 1U); 177 } 178 179 /* check if pll is bypassed */ 180 if((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_MASK) != 0U) 181 { 182 PLL2MainClock = (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_MASK) >> CCM_ANALOG_PLL_SYS_BYPASS_CLK_SRC_SHIFT) == 0U) ? 183 CPU_XTAL_CLK_HZ : CPU_CLK1_HZ; 184 } 185 else 186 { 187 PLL2MainClock = (CPU_XTAL_CLK_HZ * (((CCM_ANALOG->PLL_SYS & CCM_ANALOG_PLL_SYS_DIV_SELECT_MASK) != 0U) ? 22U : 20U)); 188 } 189 PLL2MainClock += (uint32_t)(((uint64_t)CPU_XTAL_CLK_HZ * ((uint64_t)(CCM_ANALOG->PLL_SYS_NUM))) / ((uint64_t)(CCM_ANALOG->PLL_SYS_DENOM))); 190 191 switch (CCM->CBCMR & CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK) 192 { 193 /* PLL2 ---> Pre_Periph_clk ---> Periph_clk */ 194 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(0U): 195 freq = PLL2MainClock; 196 break; 197 198 /* PLL2 PFD2 ---> Pre_Periph_clk ---> Periph_clk */ 199 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(1U): 200 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD2_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD2_FRAC_SHIFT) * 18U; 201 break; 202 203 /* PLL2 PFD0 ---> Pre_Periph_clk ---> Periph_clk */ 204 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(2U): 205 freq = PLL2MainClock / ((CCM_ANALOG->PFD_528 & CCM_ANALOG_PFD_528_PFD0_FRAC_MASK) >> CCM_ANALOG_PFD_528_PFD0_FRAC_SHIFT) * 18U; 206 break; 207 208 /* PLL1 divided(/2) ---> Pre_Periph_clk ---> Periph_clk */ 209 case CCM_CBCMR_PRE_PERIPH_CLK_SEL(3U): 210 freq = PLL1MainClock / (((CCM->CACRR & CCM_CACRR_ARM_PODF_MASK) >> CCM_CACRR_ARM_PODF_SHIFT) + 1U); 211 break; 212 213 default: 214 freq = 0U; 215 break; 216 } 217 } 218 219 SystemCoreClock = (freq / (((CCM->CBCDR & CCM_CBCDR_AHB_PODF_MASK) >> CCM_CBCDR_AHB_PODF_SHIFT) + 1U)); 220 221 } 222 223 /* ---------------------------------------------------------------------------- 224 -- SystemInitHook() 225 ---------------------------------------------------------------------------- */ 226 SystemInitHook(void)227__attribute__ ((weak)) void SystemInitHook (void) { 228 /* Void implementation of the weak function. */ 229 } 230
